drm/panel-edp: Add STA 116QHD024002
[drm/drm-misc.git] / include / dt-bindings / interconnect / qcom,sc8180x.h
blob0bdc8d6cb401bba79a57604ee60718f3ce83d749
1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2 /*
3 * Qualcomm SC8180x interconnect IDs
5 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
6 */
8 #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SC8180X_H
9 #define __DT_BINDINGS_INTERCONNECT_QCOM_SC8180X_H
11 #define MASTER_A1NOC_CFG 0
12 #define MASTER_UFS_CARD 1
13 #define MASTER_UFS_GEN4 2
14 #define MASTER_UFS_MEM 3
15 #define MASTER_USB3 4
16 #define MASTER_USB3_1 5
17 #define MASTER_USB3_2 6
18 #define A1NOC_SNOC_SLV 7
19 #define SLAVE_SERVICE_A1NOC 8
21 #define MASTER_A2NOC_CFG 0
22 #define MASTER_QDSS_BAM 1
23 #define MASTER_QSPI_0 2
24 #define MASTER_QSPI_1 3
25 #define MASTER_QUP_0 4
26 #define MASTER_QUP_1 5
27 #define MASTER_QUP_2 6
28 #define MASTER_SENSORS_AHB 7
29 #define MASTER_CRYPTO_CORE_0 8
30 #define MASTER_IPA 9
31 #define MASTER_EMAC 10
32 #define MASTER_PCIE 11
33 #define MASTER_PCIE_1 12
34 #define MASTER_PCIE_2 13
35 #define MASTER_PCIE_3 14
36 #define MASTER_QDSS_ETR 15
37 #define MASTER_SDCC_2 16
38 #define MASTER_SDCC_4 17
39 #define A2NOC_SNOC_SLV 18
40 #define SLAVE_ANOC_PCIE_GEM_NOC 19
41 #define SLAVE_SERVICE_A2NOC 20
43 #define MASTER_CAMNOC_HF0_UNCOMP 0
44 #define MASTER_CAMNOC_HF1_UNCOMP 1
45 #define MASTER_CAMNOC_SF_UNCOMP 2
46 #define SLAVE_CAMNOC_UNCOMP 3
48 #define MASTER_NPU 0
49 #define SLAVE_CDSP_MEM_NOC 1
51 #define SNOC_CNOC_MAS 0
52 #define SLAVE_A1NOC_CFG 1
53 #define SLAVE_A2NOC_CFG 2
54 #define SLAVE_AHB2PHY_CENTER 3
55 #define SLAVE_AHB2PHY_EAST 4
56 #define SLAVE_AHB2PHY_WEST 5
57 #define SLAVE_AHB2PHY_SOUTH 6
58 #define SLAVE_AOP 7
59 #define SLAVE_AOSS 8
60 #define SLAVE_CAMERA_CFG 9
61 #define SLAVE_CLK_CTL 10
62 #define SLAVE_CDSP_CFG 11
63 #define SLAVE_RBCPR_CX_CFG 12
64 #define SLAVE_RBCPR_MMCX_CFG 13
65 #define SLAVE_RBCPR_MX_CFG 14
66 #define SLAVE_CRYPTO_0_CFG 15
67 #define SLAVE_CNOC_DDRSS 16
68 #define SLAVE_DISPLAY_CFG 17
69 #define SLAVE_EMAC_CFG 18
70 #define SLAVE_GLM 19
71 #define SLAVE_GRAPHICS_3D_CFG 20
72 #define SLAVE_IMEM_CFG 21
73 #define SLAVE_IPA_CFG 22
74 #define SLAVE_CNOC_MNOC_CFG 23
75 #define SLAVE_NPU_CFG 24
76 #define SLAVE_PCIE_0_CFG 25
77 #define SLAVE_PCIE_1_CFG 26
78 #define SLAVE_PCIE_2_CFG 27
79 #define SLAVE_PCIE_3_CFG 28
80 #define SLAVE_PDM 29
81 #define SLAVE_PIMEM_CFG 30
82 #define SLAVE_PRNG 31
83 #define SLAVE_QDSS_CFG 32
84 #define SLAVE_QSPI_0 33
85 #define SLAVE_QSPI_1 34
86 #define SLAVE_QUP_1 35
87 #define SLAVE_QUP_2 36
88 #define SLAVE_QUP_0 37
89 #define SLAVE_SDCC_2 38
90 #define SLAVE_SDCC_4 39
91 #define SLAVE_SECURITY 40
92 #define SLAVE_SNOC_CFG 41
93 #define SLAVE_SPSS_CFG 42
94 #define SLAVE_TCSR 43
95 #define SLAVE_TLMM_EAST 44
96 #define SLAVE_TLMM_SOUTH 45
97 #define SLAVE_TLMM_WEST 46
98 #define SLAVE_TSIF 47
99 #define SLAVE_UFS_CARD_CFG 48
100 #define SLAVE_UFS_MEM_0_CFG 49
101 #define SLAVE_UFS_MEM_1_CFG 50
102 #define SLAVE_USB3 51
103 #define SLAVE_USB3_1 52
104 #define SLAVE_USB3_2 53
105 #define SLAVE_VENUS_CFG 54
106 #define SLAVE_VSENSE_CTRL_CFG 55
107 #define SLAVE_SERVICE_CNOC 56
109 #define MASTER_CNOC_DC_NOC 0
110 #define SLAVE_GEM_NOC_CFG 1
111 #define SLAVE_LLCC_CFG 2
113 #define MASTER_AMPSS_M0 0
114 #define MASTER_GPU_TCU 1
115 #define MASTER_SYS_TCU 2
116 #define MASTER_GEM_NOC_CFG 3
117 #define MASTER_COMPUTE_NOC 4
118 #define MASTER_GRAPHICS_3D 5
119 #define MASTER_MNOC_HF_MEM_NOC 6
120 #define MASTER_MNOC_SF_MEM_NOC 7
121 #define MASTER_GEM_NOC_PCIE_SNOC 8
122 #define MASTER_SNOC_GC_MEM_NOC 9
123 #define MASTER_SNOC_SF_MEM_NOC 10
124 #define MASTER_ECC 11
125 #define SLAVE_MSS_PROC_MS_MPU_CFG 12
126 #define SLAVE_ECC 13
127 #define SLAVE_GEM_NOC_SNOC 14
128 #define SLAVE_LLCC 15
129 #define SLAVE_SERVICE_GEM_NOC 16
130 #define SLAVE_SERVICE_GEM_NOC_1 17
132 #define MASTER_LLCC 0
133 #define SLAVE_EBI_CH0 1
135 #define MASTER_CNOC_MNOC_CFG 0
136 #define MASTER_CAMNOC_HF0 1
137 #define MASTER_CAMNOC_HF1 2
138 #define MASTER_CAMNOC_SF 3
139 #define MASTER_MDP_PORT0 4
140 #define MASTER_MDP_PORT1 5
141 #define MASTER_ROTATOR 6
142 #define MASTER_VIDEO_P0 7
143 #define MASTER_VIDEO_P1 8
144 #define MASTER_VIDEO_PROC 9
145 #define SLAVE_MNOC_SF_MEM_NOC 10
146 #define SLAVE_MNOC_HF_MEM_NOC 11
147 #define SLAVE_SERVICE_MNOC 12
149 #define MASTER_SNOC_CFG 0
150 #define A1NOC_SNOC_MAS 1
151 #define A2NOC_SNOC_MAS 2
152 #define MASTER_GEM_NOC_SNOC 3
153 #define MASTER_PIMEM 4
154 #define MASTER_GIC 5
155 #define SLAVE_APPSS 6
156 #define SNOC_CNOC_SLV 7
157 #define SLAVE_SNOC_GEM_NOC_GC 8
158 #define SLAVE_SNOC_GEM_NOC_SF 9
159 #define SLAVE_OCIMEM 10
160 #define SLAVE_PIMEM 11
161 #define SLAVE_SERVICE_SNOC 12
162 #define SLAVE_PCIE_0 13
163 #define SLAVE_PCIE_1 14
164 #define SLAVE_PCIE_2 15
165 #define SLAVE_PCIE_3 16
166 #define SLAVE_QDSS_STM 17
167 #define SLAVE_TCU 18
169 #define MASTER_MNOC_HF_MEM_NOC_DISPLAY 0
170 #define MASTER_MNOC_SF_MEM_NOC_DISPLAY 1
171 #define SLAVE_LLCC_DISPLAY 2
173 #define MASTER_LLCC_DISPLAY 0
174 #define SLAVE_EBI_CH0_DISPLAY 1
176 #define MASTER_MDP_PORT0_DISPLAY 0
177 #define MASTER_MDP_PORT1_DISPLAY 1
178 #define MASTER_ROTATOR_DISPLAY 2
179 #define SLAVE_MNOC_SF_MEM_NOC_DISPLAY 3
180 #define SLAVE_MNOC_HF_MEM_NOC_DISPLAY 4
182 #define MASTER_QUP_CORE_0 0
183 #define MASTER_QUP_CORE_1 1
184 #define MASTER_QUP_CORE_2 2
185 #define SLAVE_QUP_CORE_0 3
186 #define SLAVE_QUP_CORE_1 4
187 #define SLAVE_QUP_CORE_2 5
189 #endif