1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
3 * Qualcomm SM7150 interconnect IDs
5 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
9 #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM7150_H
10 #define __DT_BINDINGS_INTERCONNECT_QCOM_SM7150_H
12 #define MASTER_A1NOC_CFG 0
13 #define MASTER_QUP_0 1
16 #define MASTER_SDCC_2 4
17 #define MASTER_SDCC_4 5
18 #define MASTER_UFS_MEM 6
19 #define A1NOC_SNOC_SLV 7
20 #define SLAVE_SERVICE_A1NOC 8
22 #define MASTER_A2NOC_CFG 0
23 #define MASTER_QDSS_BAM 1
24 #define MASTER_QUP_1 2
25 #define MASTER_CNOC_A2NOC 3
26 #define MASTER_CRYPTO_CORE_0 4
29 #define MASTER_QDSS_ETR 7
31 #define A2NOC_SNOC_SLV 9
32 #define SLAVE_ANOC_PCIE_GEM_NOC 10
33 #define SLAVE_SERVICE_A2NOC 11
35 #define MASTER_CAMNOC_HF0_UNCOMP 0
36 #define MASTER_CAMNOC_RT_UNCOMP 1
37 #define MASTER_CAMNOC_SF_UNCOMP 2
38 #define MASTER_CAMNOC_NRT_UNCOMP 3
39 #define SLAVE_CAMNOC_UNCOMP 4
42 #define SLAVE_CDSP_GEM_NOC 1
45 #define SNOC_CNOC_MAS 1
46 #define MASTER_QDSS_DAP 2
47 #define SLAVE_A1NOC_CFG 3
48 #define SLAVE_A2NOC_CFG 4
49 #define SLAVE_AHB2PHY_NORTH 5
50 #define SLAVE_AHB2PHY_SOUTH 6
51 #define SLAVE_AHB2PHY_WEST 7
54 #define SLAVE_CAMERA_CFG 10
55 #define SLAVE_CAMERA_NRT_THROTTLE_CFG 11
56 #define SLAVE_CAMERA_RT_THROTTLE_CFG 12
57 #define SLAVE_CLK_CTL 13
58 #define SLAVE_CDSP_CFG 14
59 #define SLAVE_RBCPR_CX_CFG 15
60 #define SLAVE_RBCPR_MX_CFG 16
61 #define SLAVE_CRYPTO_0_CFG 17
62 #define SLAVE_CNOC_DDRSS 18
63 #define SLAVE_DISPLAY_CFG 19
64 #define SLAVE_DISPLAY_THROTTLE_CFG 20
65 #define SLAVE_EMMC_CFG 21
67 #define SLAVE_GRAPHICS_3D_CFG 23
68 #define SLAVE_IMEM_CFG 24
69 #define SLAVE_IPA_CFG 25
70 #define SLAVE_CNOC_MNOC_CFG 26
71 #define SLAVE_PCIE_CFG 27
73 #define SLAVE_PIMEM_CFG 29
75 #define SLAVE_QDSS_CFG 31
76 #define SLAVE_QUP_0 32
77 #define SLAVE_QUP_1 33
78 #define SLAVE_SDCC_2 34
79 #define SLAVE_SDCC_4 35
80 #define SLAVE_SNOC_CFG 36
81 #define SLAVE_SPDM_WRAPPER 37
83 #define SLAVE_TLMM_NORTH 39
84 #define SLAVE_TLMM_SOUTH 40
85 #define SLAVE_TLMM_WEST 41
87 #define SLAVE_UFS_MEM_CFG 43
89 #define SLAVE_VENUS_CFG 45
90 #define SLAVE_VENUS_CVP_THROTTLE_CFG 46
91 #define SLAVE_VENUS_THROTTLE_CFG 47
92 #define SLAVE_VSENSE_CTRL_CFG 48
93 #define SLAVE_CNOC_A2NOC 49
94 #define SLAVE_SERVICE_CNOC 50
96 #define MASTER_CNOC_DC_NOC 0
97 #define SLAVE_GEM_NOC_CFG 1
98 #define SLAVE_LLCC_CFG 2
100 #define MASTER_AMPSS_M0 0
101 #define MASTER_SYS_TCU 1
102 #define MASTER_GEM_NOC_CFG 2
103 #define MASTER_COMPUTE_NOC 3
104 #define MASTER_MNOC_HF_MEM_NOC 4
105 #define MASTER_MNOC_SF_MEM_NOC 5
106 #define MASTER_GEM_NOC_PCIE_SNOC 6
107 #define MASTER_SNOC_GC_MEM_NOC 7
108 #define MASTER_SNOC_SF_MEM_NOC 8
109 #define MASTER_GRAPHICS_3D 9
110 #define SLAVE_MSS_PROC_MS_MPU_CFG 10
111 #define SLAVE_GEM_NOC_SNOC 11
112 #define SLAVE_LLCC 12
113 #define SLAVE_SERVICE_GEM_NOC 13
116 #define MASTER_LLCC 0
117 #define SLAVE_EBI_CH0 1
119 #define MASTER_CNOC_MNOC_CFG 0
120 #define MASTER_CAMNOC_HF0 1
121 #define MASTER_CAMNOC_NRT 2
122 #define MASTER_CAMNOC_RT 3
123 #define MASTER_CAMNOC_SF 4
124 #define MASTER_MDP_PORT0 5
125 #define MASTER_MDP_PORT1 6
126 #define MASTER_ROTATOR 7
127 #define MASTER_VIDEO_P0 8
128 #define MASTER_VIDEO_P1 9
129 #define MASTER_VIDEO_PROC 10
130 #define SLAVE_MNOC_SF_MEM_NOC 11
131 #define SLAVE_MNOC_HF_MEM_NOC 12
132 #define SLAVE_SERVICE_MNOC 13
134 #define MASTER_SNOC_CFG 0
135 #define A1NOC_SNOC_MAS 1
136 #define A2NOC_SNOC_MAS 2
137 #define MASTER_GEM_NOC_SNOC 3
138 #define MASTER_PIMEM 4
140 #define SLAVE_APPSS 6
141 #define SNOC_CNOC_SLV 7
142 #define SLAVE_SNOC_GEM_NOC_GC 8
143 #define SLAVE_SNOC_GEM_NOC_SF 9
144 #define SLAVE_OCIMEM 10
145 #define SLAVE_PIMEM 11
146 #define SLAVE_SERVICE_SNOC 12
147 #define SLAVE_QDSS_STM 13