include/linux/habanalabs/hl_boot_if.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright 2018-2023 HabanaLabs, Ltd.
   4  * All Rights Reserved.
   5  *
   6  */
   7
   8 #ifndef HL_BOOT_IF_H
   9 #define HL_BOOT_IF_H
  10
  11 #define LKD_HARD_RESET_MAGIC            0xED7BD694 /* deprecated - do not use */
  12 #define HL_POWER9_HOST_MAGIC            0x1DA30009
  13
  14 #define BOOT_FIT_SRAM_OFFSET            0x200000
  15
  16 #define VERSION_MAX_LEN                 128
  17
  18 enum cpu_boot_err {
  19         CPU_BOOT_ERR_DRAM_INIT_FAIL = 0,
  20         CPU_BOOT_ERR_FIT_CORRUPTED = 1,
  21         CPU_BOOT_ERR_TS_INIT_FAIL = 2,
  22         CPU_BOOT_ERR_DRAM_SKIPPED = 3,
  23         CPU_BOOT_ERR_BMC_WAIT_SKIPPED = 4,
  24         CPU_BOOT_ERR_NIC_DATA_NOT_RDY = 5,
  25         CPU_BOOT_ERR_NIC_FW_FAIL = 6,
  26         CPU_BOOT_ERR_SECURITY_NOT_RDY = 7,
  27         CPU_BOOT_ERR_SECURITY_FAIL = 8,
  28         CPU_BOOT_ERR_EFUSE_FAIL = 9,
  29         CPU_BOOT_ERR_PRI_IMG_VER_FAIL = 10,
  30         CPU_BOOT_ERR_SEC_IMG_VER_FAIL = 11,
  31         CPU_BOOT_ERR_PLL_FAIL = 12,
  32         CPU_BOOT_ERR_DEVICE_UNUSABLE_FAIL = 13,
  33         CPU_BOOT_ERR_BOOT_FW_CRIT_ERR = 18,
  34         CPU_BOOT_ERR_BINNING_FAIL = 19,
  35         CPU_BOOT_ERR_TPM_FAIL = 20,
  36         CPU_BOOT_ERR_TMP_THRESH_INIT_FAIL = 21,
  37         CPU_BOOT_ERR_EEPROM_FAIL = 22,
  38         CPU_BOOT_ERR_ENG_ARC_MEM_SCRUB_FAIL = 23,
  39         CPU_BOOT_ERR_ENABLED = 31,
  40         CPU_BOOT_ERR_SCND_EN = 63,
  41         CPU_BOOT_ERR_LAST = 64 /* we have 2 registers of 32 bits */
  42 };
  43
  44 /*
  45  * Mask for fatal failures
  46  * This mask contains all possible fatal failures, and a dynamic code
  47  * will clear the non-relevant ones.
  48  */
  49 #define CPU_BOOT_ERR_FATAL_MASK                                 \
  50                 ((1 << CPU_BOOT_ERR_DRAM_INIT_FAIL) |           \
  51                  (1 << CPU_BOOT_ERR_PLL_FAIL) |                 \
  52                  (1 << CPU_BOOT_ERR_BINNING_FAIL) |             \
  53                  (1 << CPU_BOOT_ERR_DRAM_SKIPPED) |             \
  54                  (1 << CPU_BOOT_ERR_ENG_ARC_MEM_SCRUB_FAIL) |   \
  55                  (1 << CPU_BOOT_ERR_EEPROM_FAIL))
  56
  57 /*
  58  * CPU error bits in BOOT_ERROR registers
  59  *
  60  * CPU_BOOT_ERR0_DRAM_INIT_FAIL         DRAM initialization failed.
  61  *                                      DRAM is not reliable to use.
  62  *
  63  * CPU_BOOT_ERR0_FIT_CORRUPTED          FIT data integrity verification of the
  64  *                                      image provided by the host has failed.
  65  *
  66  * CPU_BOOT_ERR0_TS_INIT_FAIL           Thermal Sensor initialization failed.
  67  *                                      Boot continues as usual, but keep in
  68  *                                      mind this is a warning.
  69  *
  70  * CPU_BOOT_ERR0_DRAM_SKIPPED           DRAM initialization has been skipped.
  71  *                                      Skipping DRAM initialization has been
  72  *                                      requested (e.g. strap, command, etc.)
  73  *                                      and FW skipped the DRAM initialization.
  74  *                                      Host can initialize the DRAM.
  75  *
  76  * CPU_BOOT_ERR0_BMC_WAIT_SKIPPED       Waiting for BMC data will be skipped.
  77  *                                      Meaning the BMC data might not be
  78  *                                      available until reset.
  79  *
  80  * CPU_BOOT_ERR0_NIC_DATA_NOT_RDY       NIC data from BMC is not ready.
  81  *                                      BMC has not provided the NIC data yet.
  82  *                                      Once provided this bit will be cleared.
  83  *
  84  * CPU_BOOT_ERR0_NIC_FW_FAIL            NIC FW loading failed.
  85  *                                      The NIC FW loading and initialization
  86  *                                      failed. This means NICs are not usable.
  87  *
  88  * CPU_BOOT_ERR0_SECURITY_NOT_RDY       Chip security initialization has been
  89  *                                      started, but is not ready yet - chip
  90  *                                      cannot be accessed.
  91  *
  92  * CPU_BOOT_ERR0_SECURITY_FAIL          Security related tasks have failed.
  93  *                                      The tasks are security init (root of
  94  *                                      trust), boot authentication (chain of
  95  *                                      trust), data packets authentication.
  96  *
  97  * CPU_BOOT_ERR0_EFUSE_FAIL             Reading from eFuse failed.
  98  *                                      The PCI device ID might be wrong.
  99  *
 100  * CPU_BOOT_ERR0_PRI_IMG_VER_FAIL       Verification of primary image failed.
 101  *                                      It mean that ppboot checksum
 102  *                                      verification for the preboot primary
 103  *                                      image has failed to match expected
 104  *                                      checksum. Trying to program image again
 105  *                                      might solve this.
 106  *
 107  * CPU_BOOT_ERR0_SEC_IMG_VER_FAIL       Verification of secondary image failed.
 108  *                                      It mean that ppboot checksum
 109  *                                      verification for the preboot secondary
 110  *                                      image has failed to match expected
 111  *                                      checksum. Trying to program image again
 112  *                                      might solve this.
 113  *
 114  * CPU_BOOT_ERR0_PLL_FAIL               PLL settings failed, meaning that one
 115  *                                      of the PLLs remains in REF_CLK
 116  *
 117  * CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL   Device is unusable and customer support
 118  *                                      should be contacted.
 119  *
 120  * CPU_BOOT_ERR0_BOOT_FW_CRIT_ERR       Critical error was detected during
 121  *                                      the execution of ppboot or preboot.
 122  *                                      for example: stack overflow.
 123  *
 124  * CPU_BOOT_ERR0_BINNING_FAIL           Binning settings failed, meaning
 125  *                                      malfunctioning components might still be
 126  *                                      in use.
 127  *
 128  * CPU_BOOT_ERR0_TPM_FAIL               TPM verification flow failed.
 129  *
 130  * CPU_BOOT_ERR0_TMP_THRESH_INIT_FAIL   Failed to set threshold for tmperature
 131  *                                      sensor.
 132  *
 133  * CPU_BOOT_ERR_EEPROM_FAIL             Failed reading EEPROM data. Defaults
 134  *                                      are used.
 135  *
 136  * CPU_BOOT_ERR_ENG_ARC_MEM_SCRUB_FAIL  Failed scrubbing the Engines/ARCFarm
 137  *                                      memories. Boot disabled until reset.
 138  *
 139  * CPU_BOOT_ERR0_ENABLED                Error registers enabled.
 140  *                                      This is a main indication that the
 141  *                                      running FW populates the error
 142  *                                      registers. Meaning the error bits are
 143  *                                      not garbage, but actual error statuses.
 144  */
 145 #define CPU_BOOT_ERR0_DRAM_INIT_FAIL            (1 << CPU_BOOT_ERR_DRAM_INIT_FAIL)
 146 #define CPU_BOOT_ERR0_FIT_CORRUPTED             (1 << CPU_BOOT_ERR_FIT_CORRUPTED)
 147 #define CPU_BOOT_ERR0_TS_INIT_FAIL              (1 << CPU_BOOT_ERR_TS_INIT_FAIL)
 148 #define CPU_BOOT_ERR0_DRAM_SKIPPED              (1 << CPU_BOOT_ERR_DRAM_SKIPPED)
 149 #define CPU_BOOT_ERR0_BMC_WAIT_SKIPPED          (1 << CPU_BOOT_ERR_BMC_WAIT_SKIPPED)
 150 #define CPU_BOOT_ERR0_NIC_DATA_NOT_RDY          (1 << CPU_BOOT_ERR_NIC_DATA_NOT_RDY)
 151 #define CPU_BOOT_ERR0_NIC_FW_FAIL               (1 << CPU_BOOT_ERR_NIC_FW_FAIL)
 152 #define CPU_BOOT_ERR0_SECURITY_NOT_RDY          (1 << CPU_BOOT_ERR_SECURITY_NOT_RDY)
 153 #define CPU_BOOT_ERR0_SECURITY_FAIL             (1 << CPU_BOOT_ERR_SECURITY_FAIL)
 154 #define CPU_BOOT_ERR0_EFUSE_FAIL                (1 << CPU_BOOT_ERR_EFUSE_FAIL)
 155 #define CPU_BOOT_ERR0_PRI_IMG_VER_FAIL          (1 << CPU_BOOT_ERR_PRI_IMG_VER_FAIL)
 156 #define CPU_BOOT_ERR0_SEC_IMG_VER_FAIL          (1 << CPU_BOOT_ERR_SEC_IMG_VER_FAIL)
 157 #define CPU_BOOT_ERR0_PLL_FAIL                  (1 << CPU_BOOT_ERR_PLL_FAIL)
 158 #define CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL      (1 << CPU_BOOT_ERR_DEVICE_UNUSABLE_FAIL)
 159 #define CPU_BOOT_ERR0_BOOT_FW_CRIT_ERR          (1 << CPU_BOOT_ERR_BOOT_FW_CRIT_ERR)
 160 #define CPU_BOOT_ERR0_BINNING_FAIL              (1 << CPU_BOOT_ERR_BINNING_FAIL)
 161 #define CPU_BOOT_ERR0_TPM_FAIL                  (1 << CPU_BOOT_ERR_TPM_FAIL)
 162 #define CPU_BOOT_ERR0_TMP_THRESH_INIT_FAIL      (1 << CPU_BOOT_ERR_TMP_THRESH_INIT_FAIL)
 163 #define CPU_BOOT_ERR0_EEPROM_FAIL               (1 << CPU_BOOT_ERR_EEPROM_FAIL)
 164 #define CPU_BOOT_ERR0_ENG_ARC_MEM_SCRUB_FAIL    (1 << CPU_BOOT_ERR_ENG_ARC_MEM_SCRUB_FAIL)
 165 #define CPU_BOOT_ERR0_ENABLED                   (1 << CPU_BOOT_ERR_ENABLED)
 166 #define CPU_BOOT_ERR1_ENABLED                   (1 << CPU_BOOT_ERR_ENABLED)
 167
 168 enum cpu_boot_dev_sts {
 169         CPU_BOOT_DEV_STS_SECURITY_EN = 0,
 170         CPU_BOOT_DEV_STS_DEBUG_EN = 1,
 171         CPU_BOOT_DEV_STS_WATCHDOG_EN = 2,
 172         CPU_BOOT_DEV_STS_DRAM_INIT_EN = 3,
 173         CPU_BOOT_DEV_STS_BMC_WAIT_EN = 4,
 174         CPU_BOOT_DEV_STS_E2E_CRED_EN = 5,
 175         CPU_BOOT_DEV_STS_HBM_CRED_EN = 6,
 176         CPU_BOOT_DEV_STS_RL_EN = 7,
 177         CPU_BOOT_DEV_STS_SRAM_SCR_EN = 8,
 178         CPU_BOOT_DEV_STS_DRAM_SCR_EN = 9,
 179         CPU_BOOT_DEV_STS_FW_HARD_RST_EN = 10,
 180         CPU_BOOT_DEV_STS_PLL_INFO_EN = 11,
 181         CPU_BOOT_DEV_STS_SP_SRAM_EN = 12,
 182         CPU_BOOT_DEV_STS_CLK_GATE_EN = 13,
 183         CPU_BOOT_DEV_STS_HBM_ECC_EN = 14,
 184         CPU_BOOT_DEV_STS_PKT_PI_ACK_EN = 15,
 185         CPU_BOOT_DEV_STS_FW_LD_COM_EN = 16,
 186         CPU_BOOT_DEV_STS_FW_IATU_CONF_EN = 17,
 187         CPU_BOOT_DEV_STS_FW_NIC_MAC_EN = 18,
 188         CPU_BOOT_DEV_STS_DYN_PLL_EN = 19,
 189         CPU_BOOT_DEV_STS_GIC_PRIVILEGED_EN = 20,
 190         CPU_BOOT_DEV_STS_EQ_INDEX_EN = 21,
 191         CPU_BOOT_DEV_STS_MULTI_IRQ_POLL_EN = 22,
 192         CPU_BOOT_DEV_STS_FW_NIC_STAT_XPCS91_EN = 23,
 193         CPU_BOOT_DEV_STS_FW_NIC_STAT_EXT_EN = 24,
 194         CPU_BOOT_DEV_STS_IS_IDLE_CHECK_EN = 25,
 195         CPU_BOOT_DEV_STS_MAP_HWMON_EN = 26,
 196         CPU_BOOT_DEV_STS_NIC_MEM_CLEAR_EN = 27,
 197         CPU_BOOT_DEV_STS_MMU_PGTBL_DRAM_EN = 28,
 198         CPU_BOOT_DEV_STS_ENABLED = 31,
 199         CPU_BOOT_DEV_STS_SCND_EN = 63,
 200         CPU_BOOT_DEV_STS_LAST = 64 /* we have 2 registers of 32 bits */
 201 };
 202
 203 /*
 204  * BOOT DEVICE STATUS bits in BOOT_DEVICE_STS registers
 205  *
 206  * CPU_BOOT_DEV_STS0_SECURITY_EN        Security is Enabled.
 207  *                                      This is an indication for security
 208  *                                      enabled in FW, which means that
 209  *                                      all conditions for security are met:
 210  *                                      device is indicated as security enabled,
 211  *                                      registers are protected, and device
 212  *                                      uses keys for image verification.
 213  *                                      Initialized in: preboot
 214  *
 215  * CPU_BOOT_DEV_STS0_DEBUG_EN           Debug is enabled.
 216  *                                      Enabled when JTAG or DEBUG is enabled
 217  *                                      in FW.
 218  *                                      Initialized in: preboot
 219  *
 220  * CPU_BOOT_DEV_STS0_WATCHDOG_EN        Watchdog is enabled.
 221  *                                      Watchdog is enabled in FW.
 222  *                                      Initialized in: preboot
 223  *
 224  * CPU_BOOT_DEV_STS0_DRAM_INIT_EN       DRAM initialization is enabled.
 225  *                                      DRAM initialization has been done in FW.
 226  *                                      Initialized in: u-boot
 227  *
 228  * CPU_BOOT_DEV_STS0_BMC_WAIT_EN        Waiting for BMC data enabled.
 229  *                                      If set, it means that during boot,
 230  *                                      FW waited for BMC data.
 231  *                                      Initialized in: u-boot
 232  *
 233  * CPU_BOOT_DEV_STS0_E2E_CRED_EN        E2E credits initialized.
 234  *                                      FW initialized E2E credits.
 235  *                                      Initialized in: u-boot
 236  *
 237  * CPU_BOOT_DEV_STS0_HBM_CRED_EN        HBM credits initialized.
 238  *                                      FW initialized HBM credits.
 239  *                                      Initialized in: u-boot
 240  *
 241  * CPU_BOOT_DEV_STS0_RL_EN              Rate limiter initialized.
 242  *                                      FW initialized rate limiter.
 243  *                                      Initialized in: u-boot
 244  *
 245  * CPU_BOOT_DEV_STS0_SRAM_SCR_EN        SRAM scrambler enabled.
 246  *                                      FW initialized SRAM scrambler.
 247  *                                      Initialized in: linux
 248  *
 249  * CPU_BOOT_DEV_STS0_DRAM_SCR_EN        DRAM scrambler enabled.
 250  *                                      FW initialized DRAM scrambler.
 251  *                                      Initialized in: u-boot
 252  *
 253  * CPU_BOOT_DEV_STS0_FW_HARD_RST_EN     FW hard reset procedure is enabled.
 254  *                                      FW has the hard reset procedure
 255  *                                      implemented. This means that FW will
 256  *                                      perform hard reset procedure on
 257  *                                      receiving the halt-machine event.
 258  *                                      Initialized in: preboot, u-boot, linux
 259  *
 260  * CPU_BOOT_DEV_STS0_PLL_INFO_EN        FW retrieval of PLL info is enabled.
 261  *                                      Initialized in: linux
 262  *
 263  * CPU_BOOT_DEV_STS0_SP_SRAM_EN         SP SRAM is initialized and available
 264  *                                      for use.
 265  *                                      Initialized in: preboot
 266  *
 267  * CPU_BOOT_DEV_STS0_CLK_GATE_EN        Clock Gating enabled.
 268  *                                      FW initialized Clock Gating.
 269  *                                      Initialized in: preboot
 270  *
 271  * CPU_BOOT_DEV_STS0_HBM_ECC_EN         HBM ECC handling Enabled.
 272  *                                      FW handles HBM ECC indications.
 273  *                                      Initialized in: linux
 274  *
 275  * CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN      Packets ack value used in the armcpd
 276  *                                      is set to the PI counter.
 277  *                                      Initialized in: linux
 278  *
 279  * CPU_BOOT_DEV_STS0_FW_LD_COM_EN       Flexible FW loading communication
 280  *                                      protocol is enabled.
 281  *                                      Initialized in: preboot
 282  *
 283  * CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN    FW iATU configuration is enabled.
 284  *                                      This bit if set, means the iATU has been
 285  *                                      configured and is ready for use.
 286  *                                      Initialized in: ppboot
 287  *
 288  * CPU_BOOT_DEV_STS0_FW_NIC_MAC_EN      NIC MAC channels init is done by FW and
 289  *                                      any access to them is done via the FW.
 290  *                                      Initialized in: linux
 291  *
 292  * CPU_BOOT_DEV_STS0_DYN_PLL_EN         Dynamic PLL configuration is enabled.
 293  *                                      FW sends to host a bitmap of supported
 294  *                                      PLLs.
 295  *                                      Initialized in: linux
 296  *
 297  * CPU_BOOT_DEV_STS0_GIC_PRIVILEGED_EN  GIC access permission only from
 298  *                                      previleged entity. FW sets this status
 299  *                                      bit for host. If this bit is set then
 300  *                                      GIC can not be accessed from host.
 301  *                                      Initialized in: linux
 302  *
 303  * CPU_BOOT_DEV_STS0_EQ_INDEX_EN        Event Queue (EQ) index is a running
 304  *                                      index for each new event sent to host.
 305  *                                      This is used as a method in host to
 306  *                                      identify that the waiting event in
 307  *                                      queue is actually a new event which
 308  *                                      was not served before.
 309  *                                      Initialized in: linux
 310  *
 311  * CPU_BOOT_DEV_STS0_MULTI_IRQ_POLL_EN  Use multiple scratchpad interfaces to
 312  *                                      prevent IRQs overriding each other.
 313  *                                      Initialized in: linux
 314  *
 315  * CPU_BOOT_DEV_STS0_FW_NIC_STAT_XPCS91_EN
 316  *                                      NIC STAT and XPCS91 access is restricted
 317  *                                      and is done via FW only.
 318  *                                      Initialized in: linux
 319  *
 320  * CPU_BOOT_DEV_STS0_FW_NIC_STAT_EXT_EN
 321  *                                      NIC STAT get all is supported.
 322  *                                      Initialized in: linux
 323  *
 324  * CPU_BOOT_DEV_STS0_IS_IDLE_CHECK_EN
 325  *                                      F/W checks if the device is idle by reading defined set
 326  *                                      of registers. It returns a bitmask of all the engines,
 327  *                                      where a bit is set if the engine is not idle.
 328  *                                      Initialized in: linux
 329  *
 330  * CPU_BOOT_DEV_STS0_MAP_HWMON_EN
 331  *                                      If set, means f/w supports proprietary
 332  *                                      HWMON enum mapping to cpucp enums.
 333  *                                      Initialized in: linux
 334  *
 335  * CPU_BOOT_DEV_STS0_NIC_MEM_CLEAR_EN
 336  *                                      If set, means f/w supports nic hbm memory clear and
 337  *                                      tmr,txs hbm memory init.
 338  *                                      Initialized in: zephyr-mgmt
 339  *
 340  * CPU_BOOT_DEV_STS_MMU_PGTBL_DRAM_EN
 341  *                                      MMU page tables are located in DRAM.
 342  *                                      F/W initializes security settings for MMU
 343  *                                      page tables to reside in DRAM.
 344  *                                      Initialized in: zephyr-mgmt
 345  *
 346  * CPU_BOOT_DEV_STS0_ENABLED            Device status register enabled.
 347  *                                      This is a main indication that the
 348  *                                      running FW populates the device status
 349  *                                      register. Meaning the device status
 350  *                                      bits are not garbage, but actual
 351  *                                      statuses.
 352  *                                      Initialized in: preboot
 353  *
 354  */
 355 #define CPU_BOOT_DEV_STS0_SECURITY_EN           (1 << CPU_BOOT_DEV_STS_SECURITY_EN)
 356 #define CPU_BOOT_DEV_STS0_DEBUG_EN              (1 << CPU_BOOT_DEV_STS_DEBUG_EN)
 357 #define CPU_BOOT_DEV_STS0_WATCHDOG_EN           (1 << CPU_BOOT_DEV_STS_WATCHDOG_EN)
 358 #define CPU_BOOT_DEV_STS0_DRAM_INIT_EN          (1 << CPU_BOOT_DEV_STS_DRAM_INIT_EN)
 359 #define CPU_BOOT_DEV_STS0_BMC_WAIT_EN           (1 << CPU_BOOT_DEV_STS_BMC_WAIT_EN)
 360 #define CPU_BOOT_DEV_STS0_E2E_CRED_EN           (1 << CPU_BOOT_DEV_STS_E2E_CRED_EN)
 361 #define CPU_BOOT_DEV_STS0_HBM_CRED_EN           (1 << CPU_BOOT_DEV_STS_HBM_CRED_EN)
 362 #define CPU_BOOT_DEV_STS0_RL_EN                 (1 << CPU_BOOT_DEV_STS_RL_EN)
 363 #define CPU_BOOT_DEV_STS0_SRAM_SCR_EN           (1 << CPU_BOOT_DEV_STS_SRAM_SCR_EN)
 364 #define CPU_BOOT_DEV_STS0_DRAM_SCR_EN           (1 << CPU_BOOT_DEV_STS_DRAM_SCR_EN)
 365 #define CPU_BOOT_DEV_STS0_FW_HARD_RST_EN        (1 << CPU_BOOT_DEV_STS_FW_HARD_RST_EN)
 366 #define CPU_BOOT_DEV_STS0_PLL_INFO_EN           (1 << CPU_BOOT_DEV_STS_PLL_INFO_EN)
 367 #define CPU_BOOT_DEV_STS0_SP_SRAM_EN            (1 << CPU_BOOT_DEV_STS_SP_SRAM_EN)
 368 #define CPU_BOOT_DEV_STS0_CLK_GATE_EN           (1 << CPU_BOOT_DEV_STS_CLK_GATE_EN)
 369 #define CPU_BOOT_DEV_STS0_HBM_ECC_EN            (1 << CPU_BOOT_DEV_STS_HBM_ECC_EN)
 370 #define CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN         (1 << CPU_BOOT_DEV_STS_PKT_PI_ACK_EN)
 371 #define CPU_BOOT_DEV_STS0_FW_LD_COM_EN          (1 << CPU_BOOT_DEV_STS_FW_LD_COM_EN)
 372 #define CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN       (1 << CPU_BOOT_DEV_STS_FW_IATU_CONF_EN)
 373 #define CPU_BOOT_DEV_STS0_FW_NIC_MAC_EN         (1 << CPU_BOOT_DEV_STS_FW_NIC_MAC_EN)
 374 #define CPU_BOOT_DEV_STS0_DYN_PLL_EN            (1 << CPU_BOOT_DEV_STS_DYN_PLL_EN)
 375 #define CPU_BOOT_DEV_STS0_GIC_PRIVILEGED_EN     (1 << CPU_BOOT_DEV_STS_GIC_PRIVILEGED_EN)
 376 #define CPU_BOOT_DEV_STS0_EQ_INDEX_EN           (1 << CPU_BOOT_DEV_STS_EQ_INDEX_EN)
 377 #define CPU_BOOT_DEV_STS0_MULTI_IRQ_POLL_EN     (1 << CPU_BOOT_DEV_STS_MULTI_IRQ_POLL_EN)
 378 #define CPU_BOOT_DEV_STS0_FW_NIC_STAT_XPCS91_EN (1 << CPU_BOOT_DEV_STS_FW_NIC_STAT_XPCS91_EN)
 379 #define CPU_BOOT_DEV_STS0_FW_NIC_STAT_EXT_EN    (1 << CPU_BOOT_DEV_STS_FW_NIC_STAT_EXT_EN)
 380 #define CPU_BOOT_DEV_STS0_IS_IDLE_CHECK_EN      (1 << CPU_BOOT_DEV_STS_IS_IDLE_CHECK_EN)
 381 #define CPU_BOOT_DEV_STS0_MAP_HWMON_EN          (1 << CPU_BOOT_DEV_STS_MAP_HWMON_EN)
 382 #define CPU_BOOT_DEV_STS0_NIC_MEM_CLEAR_EN      (1 << CPU_BOOT_DEV_STS_NIC_MEM_CLEAR_EN)
 383 #define CPU_BOOT_DEV_STS0_MMU_PGTBL_DRAM_EN     (1 << CPU_BOOT_DEV_STS_MMU_PGTBL_DRAM_EN)
 384 #define CPU_BOOT_DEV_STS0_ENABLED               (1 << CPU_BOOT_DEV_STS_ENABLED)
 385 #define CPU_BOOT_DEV_STS1_ENABLED               (1 << CPU_BOOT_DEV_STS_ENABLED)
 386
 387 enum cpu_boot_status {
 388         CPU_BOOT_STATUS_NA = 0,         /* Default value after reset of chip */
 389         CPU_BOOT_STATUS_IN_WFE = 1,
 390         CPU_BOOT_STATUS_DRAM_RDY = 2,
 391         CPU_BOOT_STATUS_SRAM_AVAIL = 3,
 392         CPU_BOOT_STATUS_IN_BTL = 4,     /* BTL is H/W FSM */
 393         CPU_BOOT_STATUS_IN_PREBOOT = 5,
 394         CPU_BOOT_STATUS_IN_SPL,         /* deprecated - not reported */
 395         CPU_BOOT_STATUS_IN_UBOOT = 7,
 396         CPU_BOOT_STATUS_DRAM_INIT_FAIL, /* deprecated - will be removed */
 397         CPU_BOOT_STATUS_FIT_CORRUPTED,  /* deprecated - will be removed */
 398         /* U-Boot console prompt activated, commands are not processed */
 399         CPU_BOOT_STATUS_UBOOT_NOT_READY = 10,
 400         /* Finished NICs init, reported after DRAM and NICs */
 401         CPU_BOOT_STATUS_NIC_FW_RDY = 11,
 402         CPU_BOOT_STATUS_TS_INIT_FAIL,   /* deprecated - will be removed */
 403         CPU_BOOT_STATUS_DRAM_SKIPPED,   /* deprecated - will be removed */
 404         CPU_BOOT_STATUS_BMC_WAITING_SKIPPED, /* deprecated - will be removed */
 405         /* Last boot loader progress status, ready to receive commands */
 406         CPU_BOOT_STATUS_READY_TO_BOOT = 15,
 407         /* Internal Boot finished, ready for boot-fit */
 408         CPU_BOOT_STATUS_WAITING_FOR_BOOT_FIT = 16,
 409         /* Internal Security has been initialized, device can be accessed */
 410         CPU_BOOT_STATUS_SECURITY_READY = 17,
 411         /* FW component is preparing to shutdown and communication with host is not available */
 412         CPU_BOOT_STATUS_FW_SHUTDOWN_PREP = 18,
 413 };
 414
 415 enum kmd_msg {
 416         KMD_MSG_NA = 0,
 417         KMD_MSG_GOTO_WFE,
 418         KMD_MSG_FIT_RDY,
 419         KMD_MSG_SKIP_BMC,
 420         RESERVED,
 421         KMD_MSG_RST_DEV,
 422         KMD_MSG_LAST
 423 };
 424
 425 enum cpu_msg_status {
 426         CPU_MSG_CLR = 0,
 427         CPU_MSG_OK,
 428         CPU_MSG_ERR,
 429 };
 430
 431 /* communication registers mapping - consider ABI when changing */
 432 struct cpu_dyn_regs {
 433         __le32 cpu_pq_base_addr_low;
 434         __le32 cpu_pq_base_addr_high;
 435         __le32 cpu_pq_length;
 436         __le32 cpu_pq_init_status;
 437         __le32 cpu_eq_base_addr_low;
 438         __le32 cpu_eq_base_addr_high;
 439         __le32 cpu_eq_length;
 440         __le32 cpu_eq_ci;
 441         __le32 cpu_cq_base_addr_low;
 442         __le32 cpu_cq_base_addr_high;
 443         __le32 cpu_cq_length;
 444         __le32 cpu_pf_pq_pi;
 445         __le32 cpu_boot_dev_sts0;
 446         __le32 cpu_boot_dev_sts1;
 447         __le32 cpu_boot_err0;
 448         __le32 cpu_boot_err1;
 449         __le32 cpu_boot_status;
 450         __le32 fw_upd_sts;
 451         __le32 fw_upd_cmd;
 452         __le32 fw_upd_pending_sts;
 453         __le32 fuse_ver_offset;
 454         __le32 preboot_ver_offset;
 455         __le32 uboot_ver_offset;
 456         __le32 hw_state;
 457         __le32 kmd_msg_to_cpu;
 458         __le32 cpu_cmd_status_to_host;
 459         __le32 gic_host_pi_upd_irq;
 460         __le32 gic_tpc_qm_irq_ctrl;
 461         __le32 gic_mme_qm_irq_ctrl;
 462         __le32 gic_dma_qm_irq_ctrl;
 463         __le32 gic_nic_qm_irq_ctrl;
 464         __le32 gic_dma_core_irq_ctrl;
 465         __le32 gic_host_halt_irq;
 466         __le32 gic_host_ints_irq;
 467         __le32 reserved0;
 468         __le32 gic_rot_qm_irq_ctrl;
 469         __le32 reserved1;
 470         __le32 eng_arc_irq_ctrl;
 471         __le32 reserved2[20];           /* reserve for future use */
 472 };
 473
 474 /* TODO: remove the desc magic after the code is updated to use message */
 475 /* HCDM - Habana Communications Descriptor Magic */
 476 #define HL_COMMS_DESC_MAGIC     0x4843444D
 477 #define HL_COMMS_DESC_VER       3
 478
 479 /* HCMv - Habana Communications Message + header version */
 480 #define HL_COMMS_MSG_MAGIC_VALUE        0x48434D00
 481 #define HL_COMMS_MSG_MAGIC_MASK         0xFFFFFF00
 482 #define HL_COMMS_MSG_MAGIC_VER_MASK     0xFF
 483
 484 #define HL_COMMS_MSG_MAGIC_VER(ver)     (HL_COMMS_MSG_MAGIC_VALUE |     \
 485                                         ((ver) & HL_COMMS_MSG_MAGIC_VER_MASK))
 486 #define HL_COMMS_MSG_MAGIC_V0           HL_COMMS_DESC_MAGIC
 487 #define HL_COMMS_MSG_MAGIC_V1           HL_COMMS_MSG_MAGIC_VER(1)
 488 #define HL_COMMS_MSG_MAGIC_V2           HL_COMMS_MSG_MAGIC_VER(2)
 489 #define HL_COMMS_MSG_MAGIC_V3           HL_COMMS_MSG_MAGIC_VER(3)
 490
 491 #define HL_COMMS_MSG_MAGIC              HL_COMMS_MSG_MAGIC_V3
 492
 493 #define HL_COMMS_MSG_MAGIC_VALIDATE_MAGIC(magic)                        \
 494                 (((magic) & HL_COMMS_MSG_MAGIC_MASK) ==                 \
 495                 HL_COMMS_MSG_MAGIC_VALUE)
 496
 497 #define HL_COMMS_MSG_MAGIC_VALIDATE_VERSION(magic, ver)                 \
 498                 (((magic) & HL_COMMS_MSG_MAGIC_VER_MASK) >=             \
 499                 ((ver) & HL_COMMS_MSG_MAGIC_VER_MASK))
 500
 501 #define HL_COMMS_MSG_MAGIC_VALIDATE(magic, ver)                         \
 502                 (HL_COMMS_MSG_MAGIC_VALIDATE_MAGIC((magic)) &&          \
 503                 HL_COMMS_MSG_MAGIC_VALIDATE_VERSION((magic), (ver)))
 504
 505 enum comms_msg_type {
 506         HL_COMMS_DESC_TYPE = 0,
 507         HL_COMMS_RESET_CAUSE_TYPE = 1,
 508         HL_COMMS_FW_CFG_SKIP_TYPE = 2,
 509         HL_COMMS_BINNING_CONF_TYPE = 3,
 510 };
 511
 512 /*
 513  * Binning information shared between LKD and FW
 514  * @tpc_mask_l - TPC binning information lower 64 bit
 515  * @dec_mask - Decoder binning information
 516  * @dram_mask - DRAM binning information
 517  * @edma_mask - EDMA binning information
 518  * @mme_mask_l - MME binning information lower 32
 519  * @mme_mask_h - MME binning information upper 32
 520  * @rot_mask - Rotator binning information
 521  * @xbar_mask - xBAR binning information
 522  * @reserved - reserved field for future binning info w/o ABI change
 523  * @tpc_mask_h - TPC binning information upper 64 bit
 524  * @nic_mask - NIC binning information
 525  */
 526 struct lkd_fw_binning_info {
 527         __le64 tpc_mask_l;
 528         __le32 dec_mask;
 529         __le32 dram_mask;
 530         __le32 edma_mask;
 531         __le32 mme_mask_l;
 532         __le32 mme_mask_h;
 533         __le32 rot_mask;
 534         __le32 xbar_mask;
 535         __le32 reserved0;
 536         __le64 tpc_mask_h;
 537         __le64 nic_mask;
 538         __le32 reserved1[8];
 539 };
 540
 541 /* TODO: remove this struct after the code is updated to use message */
 542 /* this is the comms descriptor header - meta data */
 543 struct comms_desc_header {
 544         __le32 magic;           /* magic for validation */
 545         __le32 crc32;           /* CRC32 of the descriptor w/o header */
 546         __le16 size;            /* size of the descriptor w/o header */
 547         __u8 version;   /* descriptor version */
 548         __u8 reserved[5];       /* pad to 64 bit */
 549 };
 550
 551 /* this is the comms message header - meta data */
 552 struct comms_msg_header {
 553         __le32 magic;           /* magic for validation */
 554         __le32 crc32;           /* CRC32 of the message w/o header */
 555         __le16 size;            /* size of the message w/o header */
 556         __u8 version;   /* message payload version */
 557         __u8 type;              /* message type */
 558         __u8 reserved[4];       /* pad to 64 bit */
 559 };
 560
 561 enum lkd_fw_ascii_msg_lvls {
 562         LKD_FW_ASCII_MSG_ERR = 0,
 563         LKD_FW_ASCII_MSG_WRN = 1,
 564         LKD_FW_ASCII_MSG_INF = 2,
 565         LKD_FW_ASCII_MSG_DBG = 3,
 566 };
 567
 568 #define LKD_FW_ASCII_MSG_MAX_LEN                128
 569 #define LKD_FW_ASCII_MSG_MAX                    4       /* consider ABI when changing */
 570 #define LKD_FW_ASCII_MSG_MIN_DESC_VERSION       3
 571
 572 struct lkd_fw_ascii_msg {
 573         __u8 valid;
 574         __u8 msg_lvl;
 575         __u8 reserved[6];
 576         char msg[LKD_FW_ASCII_MSG_MAX_LEN];
 577 };
 578
 579 /* this is the main FW descriptor - consider ABI when changing */
 580 struct lkd_fw_comms_desc {
 581         struct comms_desc_header header;
 582         struct cpu_dyn_regs cpu_dyn_regs;
 583         char fuse_ver[VERSION_MAX_LEN];
 584         char cur_fw_ver[VERSION_MAX_LEN];
 585         /* can be used for 1 more version w/o ABI change */
 586         char reserved0[VERSION_MAX_LEN];
 587         __le64 img_addr;        /* address for next FW component load */
 588         struct lkd_fw_binning_info binning_info;
 589         struct lkd_fw_ascii_msg ascii_msg[LKD_FW_ASCII_MSG_MAX];
 590         __le32 rsvd_mem_size_mb; /* reserved memory size [MB] for FW/SVE */
 591         char reserved1[4];
 592 };
 593
 594 enum comms_reset_cause {
 595         HL_RESET_CAUSE_UNKNOWN = 0,
 596         HL_RESET_CAUSE_HEARTBEAT = 1,
 597         HL_RESET_CAUSE_TDR = 2,
 598 };
 599
 600 /* TODO: remove define after struct name is aligned on all projects */
 601 #define lkd_msg_comms lkd_fw_comms_msg
 602
 603 /* this is the comms message descriptor */
 604 struct lkd_fw_comms_msg {
 605         struct comms_msg_header header;
 606         /* union for future expantions of new messages */
 607         union {
 608                 struct {
 609                         struct cpu_dyn_regs cpu_dyn_regs;
 610                         char fuse_ver[VERSION_MAX_LEN];
 611                         char cur_fw_ver[VERSION_MAX_LEN];
 612                         /* can be used for 1 more version w/o ABI change */
 613                         char reserved0[VERSION_MAX_LEN];
 614                         /* address for next FW component load */
 615                         __le64 img_addr;
 616                         struct lkd_fw_binning_info binning_info;
 617                         struct lkd_fw_ascii_msg ascii_msg[LKD_FW_ASCII_MSG_MAX];
 618                         /* reserved memory size [MB] for FW/SVE */
 619                         __le32 rsvd_mem_size_mb;
 620                         char reserved1[4];
 621                 };
 622                 struct {
 623                         __u8 reset_cause;
 624                 };
 625                 struct {
 626                         __u8 fw_cfg_skip; /* 1 - skip, 0 - don't skip */
 627                 };
 628                 struct lkd_fw_binning_info binning_conf;
 629         };
 630 };
 631
 632 /*
 633  * LKD commands:
 634  *
 635  * COMMS_NOOP                   Used to clear the command register and no actual
 636  *                              command is send.
 637  *
 638  * COMMS_CLR_STS                Clear status command - FW should clear the
 639  *                              status register. Used for synchronization
 640  *                              between the commands as part of the race free
 641  *                              protocol.
 642  *
 643  * COMMS_RST_STATE              Reset the current communication state which is
 644  *                              kept by FW for proper responses.
 645  *                              Should be used in the beginning of the
 646  *                              communication cycle to clean any leftovers from
 647  *                              previous communication attempts.
 648  *
 649  * COMMS_PREP_DESC              Prepare descriptor for setting up the
 650  *                              communication and other dynamic data:
 651  *                              struct lkd_fw_comms_desc.
 652  *                              This command has a parameter stating the next FW
 653  *                              component size, so the FW can actually prepare a
 654  *                              space for it and in the status response provide
 655  *                              the descriptor offset. The Offset of the next FW
 656  *                              data component is a part of the descriptor
 657  *                              structure.
 658  *
 659  * COMMS_DATA_RDY               The FW data has been uploaded and is ready for
 660  *                              validation.
 661  *
 662  * COMMS_EXEC                   Execute the next FW component.
 663  *
 664  * COMMS_RST_DEV                Reset the device.
 665  *
 666  * COMMS_GOTO_WFE               Execute WFE command. Allowed only on non-secure
 667  *                              devices.
 668  *
 669  * COMMS_SKIP_BMC               Perform actions required for BMC-less servers.
 670  *                              Do not wait for BMC response.
 671  *
 672  * COMMS_PREP_DESC_ELBI         Same as COMMS_PREP_DESC only that the memory
 673  *                              space is allocated in a ELBI access only
 674  *                              address range.
 675  *
 676  */
 677 enum comms_cmd {
 678         COMMS_NOOP = 0,
 679         COMMS_CLR_STS = 1,
 680         COMMS_RST_STATE = 2,
 681         COMMS_PREP_DESC = 3,
 682         COMMS_DATA_RDY = 4,
 683         COMMS_EXEC = 5,
 684         COMMS_RST_DEV = 6,
 685         COMMS_GOTO_WFE = 7,
 686         COMMS_SKIP_BMC = 8,
 687         COMMS_PREP_DESC_ELBI = 10,
 688         COMMS_INVLD_LAST
 689 };
 690
 691 #define COMMS_COMMAND_SIZE_SHIFT        0
 692 #define COMMS_COMMAND_SIZE_MASK         0x1FFFFFF
 693 #define COMMS_COMMAND_CMD_SHIFT         27
 694 #define COMMS_COMMAND_CMD_MASK          0xF8000000
 695
 696 /*
 697  * LKD command to FW register structure
 698  * @size        - FW component size
 699  * @cmd         - command from enum comms_cmd
 700  */
 701 struct comms_command {
 702         union {         /* bit fields are only for FW use */
 703                 struct {
 704                         u32 size :25;           /* 32MB max. */
 705                         u32 reserved :2;
 706                         enum comms_cmd cmd :5;          /* 32 commands */
 707                 };
 708                 __le32 val;
 709         };
 710 };
 711
 712 /*
 713  * FW status
 714  *
 715  * COMMS_STS_NOOP               Used to clear the status register and no actual
 716  *                              status is provided.
 717  *
 718  * COMMS_STS_ACK                Command has been received and recognized.
 719  *
 720  * COMMS_STS_OK                 Command execution has finished successfully.
 721  *
 722  * COMMS_STS_ERR                Command execution was unsuccessful and resulted
 723  *                              in error.
 724  *
 725  * COMMS_STS_VALID_ERR          FW validation has failed.
 726  *
 727  * COMMS_STS_TIMEOUT_ERR        Command execution has timed out.
 728  */
 729 enum comms_sts {
 730         COMMS_STS_NOOP = 0,
 731         COMMS_STS_ACK = 1,
 732         COMMS_STS_OK = 2,
 733         COMMS_STS_ERR = 3,
 734         COMMS_STS_VALID_ERR = 4,
 735         COMMS_STS_TIMEOUT_ERR = 5,
 736         COMMS_STS_INVLD_LAST
 737 };
 738
 739 /* RAM types for FW components loading - defines the base address */
 740 enum comms_ram_types {
 741         COMMS_SRAM = 0,
 742         COMMS_DRAM = 1,
 743 };
 744
 745 #define COMMS_STATUS_OFFSET_SHIFT       0
 746 #define COMMS_STATUS_OFFSET_MASK        0x03FFFFFF
 747 #define COMMS_STATUS_OFFSET_ALIGN_SHIFT 2
 748 #define COMMS_STATUS_RAM_TYPE_SHIFT     26
 749 #define COMMS_STATUS_RAM_TYPE_MASK      0x0C000000
 750 #define COMMS_STATUS_STATUS_SHIFT       28
 751 #define COMMS_STATUS_STATUS_MASK        0xF0000000
 752
 753 /*
 754  * FW status to LKD register structure
 755  * @offset      - an offset from the base of the ram_type shifted right by
 756  *                2 bits (always aligned to 32 bits).
 757  *                Allows a maximum addressable offset of 256MB from RAM base.
 758  *                Example: for real offset in RAM of 0x800000 (8MB), the value
 759  *                in offset field is (0x800000 >> 2) = 0x200000.
 760  * @ram_type    - the RAM type that should be used for offset from
 761  *                enum comms_ram_types
 762  * @status      - status from enum comms_sts
 763  */
 764 struct comms_status {
 765         union {         /* bit fields are only for FW use */
 766                 struct {
 767                         u32 offset :26;
 768                         enum comms_ram_types ram_type :2;
 769                         enum comms_sts status :4;       /* 16 statuses */
 770                 };
 771                 __le32 val;
 772         };
 773 };
 774
 775 #define NAME_MAX_LEN    32 /* bytes */
 776 struct hl_module_data {
 777         __u8 name[NAME_MAX_LEN];
 778         __u8 version[VERSION_MAX_LEN];
 779 };
 780
 781 /**
 782  * struct hl_component_versions - versions associated with hl component.
 783  * @struct_size: size of all the struct (including dynamic size of modules).
 784  * @modules_offset: offset of the modules field in this struct.
 785  * @component: version of the component itself.
 786  * @fw_os: Firmware OS Version.
 787  * @comp_name: Name of the component.
 788  * @modules_counter: number of set bits in modules_mask.
 789  * @reserved: reserved for future use.
 790  * @modules: versions of the component's modules. Elborated explanation in
 791  *              struct cpucp_versions.
 792  */
 793 struct hl_component_versions {
 794         __le16 struct_size;
 795         __le16 modules_offset;
 796         __u8 component[VERSION_MAX_LEN];
 797         __u8 fw_os[VERSION_MAX_LEN];
 798         __u8 comp_name[NAME_MAX_LEN];
 799         __u8 modules_counter;
 800         __u8 reserved[3];
 801         struct hl_module_data modules[];
 802 };
 803
 804 /* Max size of fit size */
 805 #define HL_FW_VERSIONS_FIT_SIZE 4096
 806
 807 #endif /* HL_BOOT_IF_H */