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drm/bridge: dw-hdmi: Sync comment block with actual bus formats order
[drm/drm-misc.git] / sound / soc / codecs / wsa884x.c
blob86df5152c547bc5abd005a37f0418b8bef76cf59
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2023, Linaro Ltd.
5 */
6
7 #include <linux/bitfield.h>
8 #include <linux/cleanup.h>
9 #include <linux/device.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/hwmon.h>
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/reset.h>
20 #include <linux/slab.h>
21 #include <linux/soundwire/sdw.h>
22 #include <linux/soundwire/sdw_registers.h>
23 #include <linux/soundwire/sdw_type.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/soc.h>
28 #include <sound/tlv.h>
29
30 #define WSA884X_BASE 0x3000
31 #define WSA884X_ANA_BG_TSADC_BASE (WSA884X_BASE + 0x0001)
32 #define WSA884X_BG_CTRL (WSA884X_ANA_BG_TSADC_BASE + 0x00)
33 #define WSA884X_ADC_CTRL (WSA884X_ANA_BG_TSADC_BASE + 0x01)
34 #define WSA884X_BOP1_PROG (WSA884X_ANA_BG_TSADC_BASE + 0x02)
35 #define WSA884X_BOP2_PROG (WSA884X_ANA_BG_TSADC_BASE + 0x03)
36 #define WSA884X_BOP2_PROG_BOP2_VTH_MASK 0xf0
37 #define WSA884X_BOP2_PROG_BOP2_VTH_SHIFT 4
38 #define WSA884X_BOP2_PROG_BOP2_HYST_MASK 0x0f
39 #define WSA884X_BOP2_PROG_BOP2_HYST_SHIFT 0
40 #define WSA884X_UVLO_PROG (WSA884X_ANA_BG_TSADC_BASE + 0x04)
41 #define WSA884X_UVLO_PROG1 (WSA884X_ANA_BG_TSADC_BASE + 0x05)
42 #define WSA884X_SPARE_CTRL_0 (WSA884X_ANA_BG_TSADC_BASE + 0x06)
43 #define WSA884X_SPARE_CTRL_1 (WSA884X_ANA_BG_TSADC_BASE + 0x07)
44 #define WSA884X_SPARE_CTRL_2 (WSA884X_ANA_BG_TSADC_BASE + 0x08)
45 #define WSA884X_SPARE_CTRL_3 (WSA884X_ANA_BG_TSADC_BASE + 0x09)
46 #define WSA884X_REF_CTRL (WSA884X_ANA_BG_TSADC_BASE + 0x0a)
47 #define WSA884X_REF_CTRL_BG_RDY_SEL_MASK 0x03
48 #define WSA884X_REF_CTRL_BG_RDY_SEL_SHIFT 0
49 #define WSA884X_BG_TEST_CTL (WSA884X_ANA_BG_TSADC_BASE + 0x0b)
50 #define WSA884X_BG_BIAS (WSA884X_ANA_BG_TSADC_BASE + 0x0c)
51 #define WSA884X_ADC_PROG (WSA884X_ANA_BG_TSADC_BASE + 0x0d)
52 #define WSA884X_ADC_IREF_CTL (WSA884X_ANA_BG_TSADC_BASE + 0x0e)
53 #define WSA884X_ADC_ISENS_CTL (WSA884X_ANA_BG_TSADC_BASE + 0x0f)
54 #define WSA884X_ADC_CLK_CTL (WSA884X_ANA_BG_TSADC_BASE + 0x10)
55 #define WSA884X_ADC_TEST_CTL (WSA884X_ANA_BG_TSADC_BASE + 0x11)
56 #define WSA884X_ADC_BIAS (WSA884X_ANA_BG_TSADC_BASE + 0x12)
57 #define WSA884X_VBAT_SNS (WSA884X_ANA_BG_TSADC_BASE + 0x13)
58 #define WSA884X_DOUT_MSB (WSA884X_ANA_BG_TSADC_BASE + 0x14)
59 #define WSA884X_DOUT_LSB (WSA884X_ANA_BG_TSADC_BASE + 0x15)
60 #define WSA884X_BOP_ATEST_SEL (WSA884X_ANA_BG_TSADC_BASE + 0x16)
61 #define WSA884X_MISC0 (WSA884X_ANA_BG_TSADC_BASE + 0x17)
62 #define WSA884X_MISC1 (WSA884X_ANA_BG_TSADC_BASE + 0x18)
63 #define WSA884X_MISC2 (WSA884X_ANA_BG_TSADC_BASE + 0x19)
64 #define WSA884X_MISC3 (WSA884X_ANA_BG_TSADC_BASE + 0x1a)
65 #define WSA884X_SPARE_TSBG_0 (WSA884X_ANA_BG_TSADC_BASE + 0x1b)
66 #define WSA884X_SPARE_TUNE_0 (WSA884X_ANA_BG_TSADC_BASE + 0x1c)
67 #define WSA884X_SPARE_TUNE_1 (WSA884X_ANA_BG_TSADC_BASE + 0x1d)
68
69 #define WSA884X_ANA_IVSENSE_BASE (WSA884X_BASE + 0x0020)
70 #define WSA884X_VSENSE1 (WSA884X_ANA_IVSENSE_BASE + 0x00)
71 #define WSA884X_VSENSE1_GAIN_VSENSE_FE_MASK 0xe0
72 #define WSA884X_VSENSE1_GAIN_VSENSE_FE_SHIFT 5
73 #define WSA884X_ISENSE2 (WSA884X_ANA_IVSENSE_BASE + 0x01)
74 #define WSA884X_ISENSE2_ISENSE_GAIN_CTL_MASK 0xe0
75 #define WSA884X_ISENSE2_ISENSE_GAIN_CTL_SHIFT 5
76
77 #define WSA884X_SPARE_CTL_1 (WSA884X_ANA_IVSENSE_BASE + 0x02)
78 #define WSA884X_SPARE_CTL_2 (WSA884X_ANA_IVSENSE_BASE + 0x03)
79 #define WSA884X_SPARE_CTL_3 (WSA884X_ANA_IVSENSE_BASE + 0x04)
80 #define WSA884X_SPARE_CTL_4 (WSA884X_ANA_IVSENSE_BASE + 0x05)
81 #define WSA884X_EN (WSA884X_ANA_IVSENSE_BASE + 0x06)
82 #define WSA884X_OVERRIDE1 (WSA884X_ANA_IVSENSE_BASE + 0x07)
83 #define WSA884X_OVERRIDE2 (WSA884X_ANA_IVSENSE_BASE + 0x08)
84 #define WSA884X_ISENSE1 (WSA884X_ANA_IVSENSE_BASE + 0x09)
85 #define WSA884X_ISENSE_CAL (WSA884X_ANA_IVSENSE_BASE + 0x0a)
86 #define WSA884X_MISC (WSA884X_ANA_IVSENSE_BASE + 0x0b)
87 #define WSA884X_ADC_0 (WSA884X_ANA_IVSENSE_BASE + 0x0c)
88 #define WSA884X_ADC_1 (WSA884X_ANA_IVSENSE_BASE + 0x0d)
89 #define WSA884X_ADC_2 (WSA884X_ANA_IVSENSE_BASE + 0x0e)
90 #define WSA884X_ADC_3 (WSA884X_ANA_IVSENSE_BASE + 0x0f)
91 #define WSA884X_ADC_4 (WSA884X_ANA_IVSENSE_BASE + 0x10)
92 #define WSA884X_ADC_5 (WSA884X_ANA_IVSENSE_BASE + 0x11)
93 #define WSA884X_ADC_6 (WSA884X_ANA_IVSENSE_BASE + 0x12)
94 #define WSA884X_ADC_7 (WSA884X_ANA_IVSENSE_BASE + 0x13)
95 #define WSA884X_STATUS (WSA884X_ANA_IVSENSE_BASE + 0x14)
96 #define WSA884X_IVSENSE_SPARE_TUNE_1 (WSA884X_ANA_IVSENSE_BASE + 0x15)
97 #define WSA884X_SPARE_TUNE_2 (WSA884X_ANA_IVSENSE_BASE + 0x16)
98 #define WSA884X_SPARE_TUNE_3 (WSA884X_ANA_IVSENSE_BASE + 0x17)
99 #define WSA884X_SPARE_TUNE_4 (WSA884X_ANA_IVSENSE_BASE + 0x18)
100
101 #define WSA884X_ANA_SPK_TOP_BASE (WSA884X_BASE + 0x0040)
102 #define WSA884X_TOP_CTRL1 (WSA884X_ANA_SPK_TOP_BASE + 0x00)
103 #define WSA884X_TOP_CTRL1_OCP_LOWVBAT_ITH_EN_MASK 0x01
104 #define WSA884X_CLIP_DET_CTRL1 (WSA884X_ANA_SPK_TOP_BASE + 0x01)
105 #define WSA884X_CLIP_DET_CTRL2 (WSA884X_ANA_SPK_TOP_BASE + 0x02)
106 #define WSA884X_DAC_CTRL1 (WSA884X_ANA_SPK_TOP_BASE + 0x03)
107 #define WSA884X_DAC_VCM_CTRL_REG1 (WSA884X_ANA_SPK_TOP_BASE + 0x04)
108 #define WSA884X_DAC_VCM_CTRL_REG2 (WSA884X_ANA_SPK_TOP_BASE + 0x05)
109 #define WSA884X_DAC_VCM_CTRL_REG3 (WSA884X_ANA_SPK_TOP_BASE + 0x06)
110 #define WSA884X_DAC_VCM_CTRL_REG4 (WSA884X_ANA_SPK_TOP_BASE + 0x07)
111 #define WSA884X_DAC_VCM_CTRL_REG5 (WSA884X_ANA_SPK_TOP_BASE + 0x08)
112 #define WSA884X_DAC_VCM_CTRL_REG6 (WSA884X_ANA_SPK_TOP_BASE + 0x09)
113 #define WSA884X_PWM_CLK_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x0a)
114 #define WSA884X_PWM_CLK_CTL_VCMO_INT1_IDLE_MODE_OVRT_MASK 0x80
115 #define WSA884X_PWM_CLK_CTL_VCMO_INT1_IDLE_MODE_OVRT_SHIFT 7
116 #define WSA884X_PWM_CLK_CTL_REG_MCLK_DIV_RATIO_MASK 0x40
117 #define WSA884X_PWM_CLK_CTL_REG_MCLK_DIV_RATIO_SHIFT 6
118 #define WSA884X_PWM_CLK_CTL_PWM_DEGLITCH_CLK_DELAY_CTRL_MASK 0x30
119 #define WSA884X_PWM_CLK_CTL_PWM_DEGLITCH_CLK_DELAY_CTRL_SHIFT 4
120 #define WSA884X_PWM_CLK_CTL_PWM_CLK_FREQ_SEL_MASK 0x08
121 #define WSA884X_PWM_CLK_CTL_PWM_CLK_FREQ_SEL_SHIFT 3
122 #define WSA884X_PWM_CLK_CTL_PWM_CLK_DIV_RATIO_MASK 0x06
123 #define WSA884X_PWM_CLK_CTL_PWM_CLK_DIV_RATIO_SHIFT 1
124 #define WSA884X_PWM_CLK_CTL_PWM_CLK_DIV_BYPASS_MASK 0x01
125 #define WSA884X_PWM_CLK_CTL_PWM_CLK_DIV_BYPASS_SHIFT 0
126 #define WSA884X_DRV_LF_LDO_SEL (WSA884X_ANA_SPK_TOP_BASE + 0x0b)
127 #define WSA884X_OCP_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x0c)
128 #define WSA884X_PDRV_HS_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x0d)
129 #define WSA884X_PDRV_LS_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x0e)
130 #define WSA884X_SPK_TOP_SPARE_CTL_1 (WSA884X_ANA_SPK_TOP_BASE + 0x0f)
131 #define WSA884X_SPK_TOP_SPARE_CTL_2 (WSA884X_ANA_SPK_TOP_BASE + 0x10)
132 #define WSA884X_SPK_TOP_SPARE_CTL_3 (WSA884X_ANA_SPK_TOP_BASE + 0x11)
133 #define WSA884X_SPK_TOP_SPARE_CTL_4 (WSA884X_ANA_SPK_TOP_BASE + 0x12)
134 #define WSA884X_SPARE_CTL_5 (WSA884X_ANA_SPK_TOP_BASE + 0x13)
135 #define WSA884X_DAC_EN_DEBUG_REG (WSA884X_ANA_SPK_TOP_BASE + 0x14)
136 #define WSA884X_DAC_OPAMP_BIAS1_REG (WSA884X_ANA_SPK_TOP_BASE + 0x15)
137 #define WSA884X_DAC_OPAMP_BIAS2_REG (WSA884X_ANA_SPK_TOP_BASE + 0x16)
138 #define WSA884X_DAC_TUNE1 (WSA884X_ANA_SPK_TOP_BASE + 0x17)
139 #define WSA884X_DAC_VOLTAGE_CTRL_REG (WSA884X_ANA_SPK_TOP_BASE + 0x18)
140 #define WSA884X_ATEST1_REG (WSA884X_ANA_SPK_TOP_BASE + 0x19)
141 #define WSA884X_ATEST2_REG (WSA884X_ANA_SPK_TOP_BASE + 0x1a)
142 #define WSA884X_TOP_BIAS_REG1 (WSA884X_ANA_SPK_TOP_BASE + 0x1b)
143 #define WSA884X_TOP_BIAS_REG2 (WSA884X_ANA_SPK_TOP_BASE + 0x1c)
144 #define WSA884X_TOP_BIAS_REG3 (WSA884X_ANA_SPK_TOP_BASE + 0x1d)
145 #define WSA884X_TOP_BIAS_REG4 (WSA884X_ANA_SPK_TOP_BASE + 0x1e)
146 #define WSA884X_PWRSTG_DBG2 (WSA884X_ANA_SPK_TOP_BASE + 0x1f)
147 #define WSA884X_DRV_LF_BLK_EN (WSA884X_ANA_SPK_TOP_BASE + 0x20)
148 #define WSA884X_DRV_LF_EN (WSA884X_ANA_SPK_TOP_BASE + 0x21)
149 #define WSA884X_DRV_LF_MASK_DCC_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x22)
150 #define WSA884X_DRV_LF_MISC_CTL1 (WSA884X_ANA_SPK_TOP_BASE + 0x23)
151 #define WSA884X_DRV_LF_REG_GAIN (WSA884X_ANA_SPK_TOP_BASE + 0x24)
152 #define WSA884X_DRV_OS_CAL_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x25)
153 #define WSA884X_DRV_OS_CAL_CTL1 (WSA884X_ANA_SPK_TOP_BASE + 0x26)
154 #define WSA884X_PWRSTG_DBG (WSA884X_ANA_SPK_TOP_BASE + 0x27)
155 #define WSA884X_BBM_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x28)
156 #define WSA884X_TOP_MISC1 (WSA884X_ANA_SPK_TOP_BASE + 0x29)
157 #define WSA884X_DAC_VCM_CTRL_REG7 (WSA884X_ANA_SPK_TOP_BASE + 0x2a)
158 #define WSA884X_TOP_BIAS_REG5 (WSA884X_ANA_SPK_TOP_BASE + 0x2b)
159 #define WSA884X_DRV_LF_MISC_CTL2 (WSA884X_ANA_SPK_TOP_BASE + 0x2c)
160 #define WSA884X_SPK_TOP_SPARE_TUNE_2 (WSA884X_ANA_SPK_TOP_BASE + 0x2d)
161 #define WSA884X_SPK_TOP_SPARE_TUNE_3 (WSA884X_ANA_SPK_TOP_BASE + 0x2e)
162 #define WSA884X_SPK_TOP_SPARE_TUNE_4 (WSA884X_ANA_SPK_TOP_BASE + 0x2f)
163 #define WSA884X_SPARE_TUNE_5 (WSA884X_ANA_SPK_TOP_BASE + 0x30)
164 #define WSA884X_SPARE_TUNE_6 (WSA884X_ANA_SPK_TOP_BASE + 0x31)
165 #define WSA884X_SPARE_TUNE_7 (WSA884X_ANA_SPK_TOP_BASE + 0x32)
166 #define WSA884X_SPARE_TUNE_8 (WSA884X_ANA_SPK_TOP_BASE + 0x33)
167 #define WSA884X_SPARE_TUNE_9 (WSA884X_ANA_SPK_TOP_BASE + 0x34)
168 #define WSA884X_SPARE_TUNE_10 (WSA884X_ANA_SPK_TOP_BASE + 0x35)
169 #define WSA884X_PA_STATUS0 (WSA884X_ANA_SPK_TOP_BASE + 0x36)
170 #define WSA884X_PA_STATUS1 (WSA884X_ANA_SPK_TOP_BASE + 0x37)
171 #define WSA884X_PA_STATUS2 (WSA884X_ANA_SPK_TOP_BASE + 0x38)
172 #define WSA884X_PA_STATUS3 (WSA884X_ANA_SPK_TOP_BASE + 0x39)
173 #define WSA884X_PA_STATUS4 (WSA884X_ANA_SPK_TOP_BASE + 0x3a)
174 #define WSA884X_PA_STATUS5 (WSA884X_ANA_SPK_TOP_BASE + 0x3b)
175 #define WSA884X_SPARE_RO_1 (WSA884X_ANA_SPK_TOP_BASE + 0x3c)
176 #define WSA884X_SPARE_RO_2 (WSA884X_ANA_SPK_TOP_BASE + 0x3d)
177 #define WSA884X_SPARE_RO_3 (WSA884X_ANA_SPK_TOP_BASE + 0x3e)
178
179 #define WSA884X_ANA_BOOST_BASE (WSA884X_BASE + 0x0090)
180 #define WSA884X_STB_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x00)
181 #define WSA884X_STB_CTRL1_SLOPE_COMP_CURRENT_MASK 0xf8
182 #define WSA884X_STB_CTRL1_SLOPE_COMP_CURRENT_SHIFT 3
183 #define WSA884X_STB_CTRL1_VOUT_FS_MASK 0x07
184 #define WSA884X_STB_CTRL1_VOUT_FS_SHIFT 0
185 #define WSA884X_CURRENT_LIMIT (WSA884X_ANA_BOOST_BASE + 0x01)
186 #define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_OVRD_EN_MASK 0x80
187 #define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_OVRD_EN_SHIFT 7
188 #define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_MASK 0x7c
189 #define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_SHIFT 2
190 #define WSA884X_CURRENT_LIMIT_CLK_PHASE_SHIFT 0
191 #define WSA884X_BYP_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x02)
192 #define WSA884X_SPARE_CTL_0 (WSA884X_ANA_BOOST_BASE + 0x03)
193 #define WSA884X_BOOST_SPARE_CTL_1 (WSA884X_ANA_BOOST_BASE + 0x04)
194 #define WSA884X_SPARE_RO_0 (WSA884X_ANA_BOOST_BASE + 0x05)
195 #define WSA884X_BOOST_SPARE_RO_1 (WSA884X_ANA_BOOST_BASE + 0x06)
196 #define WSA884X_IBIAS1 (WSA884X_ANA_BOOST_BASE + 0x07)
197 #define WSA884X_IBIAS2 (WSA884X_ANA_BOOST_BASE + 0x08)
198 #define WSA884X_IBIAS3 (WSA884X_ANA_BOOST_BASE + 0x09)
199 #define WSA884X_EN_CTRL (WSA884X_ANA_BOOST_BASE + 0x0a)
200 #define WSA884X_STB_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x0b)
201 #define WSA884X_STB_CTRL3 (WSA884X_ANA_BOOST_BASE + 0x0c)
202 #define WSA884X_STB_CTRL4 (WSA884X_ANA_BOOST_BASE + 0x0d)
203 #define WSA884X_BYP_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x0e)
204 #define WSA884X_BYP_CTRL3 (WSA884X_ANA_BOOST_BASE + 0x0f)
205 #define WSA884X_ZX_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x10)
206 #define WSA884X_ZX_CTRL1_ZX_DET_EN_MASK 0x80
207 #define WSA884X_ZX_CTRL1_ZX_DET_EN_SHIFT 7
208 #define WSA884X_ZX_CTRL1_ZX_DET_SW_EN_MASK 0x40
209 #define WSA884X_ZX_CTRL1_ZX_DET_SW_EN_SHIFT 6
210 #define WSA884X_ZX_CTRL1_ZX_DET_STAGE_DEFAULT_MASK 0x20
211 #define WSA884X_ZX_CTRL1_ZX_DET_STAGE_DEFAULT_SHIFT 5
212 #define WSA884X_ZX_CTRL1_ZX_DET_SW_SEL_MASK 0x18
213 #define WSA884X_ZX_CTRL1_ZX_DET_SW_SEL_SHIFT 3
214 #define WSA884X_ZX_CTRL1_ZX_BYP_MASK_IGNORE_MASK 0x04
215 #define WSA884X_ZX_CTRL1_ZX_BYP_MASK_IGNORE_SHIFT 2
216 #define WSA884X_ZX_CTRL1_ZX_BYP_MASK_DEL_MASK 0x02
217 #define WSA884X_ZX_CTRL1_ZX_BYP_MASK_DEL_SHIFT 1
218 #define WSA884X_ZX_CTRL1_BOOTCAP_REFRESH_DIS_MASK 0x01
219 #define WSA884X_ZX_CTRL1_BOOTCAP_REFRESH_DIS_SHIFT 0
220 #define WSA884X_ZX_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x11)
221 #define WSA884X_BLEEDER_CTRL (WSA884X_ANA_BOOST_BASE + 0x12)
222 #define WSA884X_BOOST_MISC (WSA884X_ANA_BOOST_BASE + 0x13)
223 #define WSA884X_PWRSTAGE_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x14)
224 #define WSA884X_PWRSTAGE_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x15)
225 #define WSA884X_PWRSTAGE_CTRL3 (WSA884X_ANA_BOOST_BASE + 0x16)
226 #define WSA884X_PWRSTAGE_CTRL4 (WSA884X_ANA_BOOST_BASE + 0x17)
227 #define WSA884X_MAXD_REG1 (WSA884X_ANA_BOOST_BASE + 0x18)
228 #define WSA884X_MAXD_REG2 (WSA884X_ANA_BOOST_BASE + 0x19)
229 #define WSA884X_ILIM_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x1a)
230 #define WSA884X_ILIM_CTRL1_EN_AUTO_MAXD_SEL_MASK 0x80
231 #define WSA884X_ILIM_CTRL1_EN_AUTO_MAXD_SEL_SHIFT 0x07
232 #define WSA884X_ILIM_CTRL1_EN_ILIM_SW_CLH_MASK 0x40
233 #define WSA884X_ILIM_CTRL1_EN_ILIM_SW_CLH_SHIFT 0x06
234 #define WSA884X_ILIM_CTRL1_ILIM_OFFSET_CLH_MASK 0x38
235 #define WSA884X_ILIM_CTRL1_ILIM_OFFSET_CLH_SHIFT 0x03
236 #define WSA884X_ILIM_CTRL1_ILIM_OFFSET_PB_MASK 0x07
237 #define WSA884X_ILIM_CTRL1_ILIM_OFFSET_PB_SHIFT 0x00
238 #define WSA884X_ILIM_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x1b)
239 #define WSA884X_TEST_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x1c)
240 #define WSA884X_TEST_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x1d)
241 #define WSA884X_SPARE1 (WSA884X_ANA_BOOST_BASE + 0x1e)
242 #define WSA884X_BOOT_CAP_CHECK (WSA884X_ANA_BOOST_BASE + 0x1f)
243
244 #define WSA884X_ANA_PON_LDOL_BASE (WSA884X_BASE + 0x00b0)
245 #define WSA884X_PON_CTL_0 (WSA884X_ANA_PON_LDOL_BASE + 0x00)
246 #define WSA884X_PWRSAV_CTL (WSA884X_ANA_PON_LDOL_BASE + 0x01)
247 #define WSA884X_PON_LDOL_SPARE_CTL_0 (WSA884X_ANA_PON_LDOL_BASE + 0x02)
248 #define WSA884X_PON_LDOL_SPARE_CTL_1 (WSA884X_ANA_PON_LDOL_BASE + 0x03)
249 #define WSA884X_PON_LDOL_SPARE_CTL_2 (WSA884X_ANA_PON_LDOL_BASE + 0x04)
250 #define WSA884X_PON_LDOL_SPARE_CTL_3 (WSA884X_ANA_PON_LDOL_BASE + 0x05)
251 #define WSA884X_PON_CLT_1 (WSA884X_ANA_PON_LDOL_BASE + 0x06)
252 #define WSA884X_PON_CTL_2 (WSA884X_ANA_PON_LDOL_BASE + 0x07)
253 #define WSA884X_PON_CTL_3 (WSA884X_ANA_PON_LDOL_BASE + 0x08)
254 #define WSA884X_CKWD_CTL_0 (WSA884X_ANA_PON_LDOL_BASE + 0x09)
255 #define WSA884X_CKWD_CTL_1 (WSA884X_ANA_PON_LDOL_BASE + 0x0a)
256 #define WSA884X_CKWD_CTL_1_VPP_SW_CTL_MASK 0x20
257 #define WSA884X_CKWD_CTL_1_VPP_SW_CTL_SHIFT 5
258 #define WSA884X_CKWD_CTL_1_CKWD_VCOMP_VREF_SEL_MASK 0x1f
259 #define WSA884X_CKWD_CTL_1_CKWD_VCOMP_VREF_SEL_SHIFT 0
260 #define WSA884X_CKWD_CTL_2 (WSA884X_ANA_PON_LDOL_BASE + 0x0b)
261 #define WSA884X_CKSK_CTL_0 (WSA884X_ANA_PON_LDOL_BASE + 0x0c)
262 #define WSA884X_PADSW_CTL_0 (WSA884X_ANA_PON_LDOL_BASE + 0x0d)
263 #define WSA884X_TEST_0 (WSA884X_ANA_PON_LDOL_BASE + 0x0e)
264 #define WSA884X_TEST_1 (WSA884X_ANA_PON_LDOL_BASE + 0x0f)
265 #define WSA884X_STATUS_0 (WSA884X_ANA_PON_LDOL_BASE + 0x10)
266 #define WSA884X_STATUS_1 (WSA884X_ANA_PON_LDOL_BASE + 0x11)
267 #define WSA884X_PON_LDOL_SPARE_TUNE_0 (WSA884X_ANA_PON_LDOL_BASE + 0x12)
268 #define WSA884X_PON_LDOL_SPARE_TUNE_1 (WSA884X_ANA_PON_LDOL_BASE + 0x13)
269 #define WSA884X_PON_LDOL_SPARE_TUNE_2 (WSA884X_ANA_PON_LDOL_BASE + 0x14)
270 #define WSA884X_PON_LDOL_SPARE_TUNE_3 (WSA884X_ANA_PON_LDOL_BASE + 0x15)
271 #define WSA884X_PON_LDOL_SPARE_TUNE_4 (WSA884X_ANA_PON_LDOL_BASE + 0x16)
272
273 #define WSA884X_DIG_CTRL0_BASE (WSA884X_BASE + 0x0400)
274 #define WSA884X_DIG_CTRL0_PAGE (WSA884X_DIG_CTRL0_BASE + 0x00)
275 #define WSA884X_CHIP_ID0 (WSA884X_DIG_CTRL0_BASE + 0x01)
276 #define WSA884X_CHIP_ID1 (WSA884X_DIG_CTRL0_BASE + 0x02)
277 #define WSA884X_CHIP_ID2 (WSA884X_DIG_CTRL0_BASE + 0x03)
278 #define WSA884X_CHIP_ID3 (WSA884X_DIG_CTRL0_BASE + 0x04)
279 #define WSA884X_BUS_ID (WSA884X_DIG_CTRL0_BASE + 0x05)
280 #define WSA884X_CDC_RST_CTL (WSA884X_DIG_CTRL0_BASE + 0x10)
281 #define WSA884X_SWR_RESET_EN (WSA884X_DIG_CTRL0_BASE + 0x14)
282 #define WSA884X_TOP_CLK_CFG (WSA884X_DIG_CTRL0_BASE + 0x18)
283 #define WSA884X_SWR_CLK_RATE (WSA884X_DIG_CTRL0_BASE + 0x19)
284 #define WSA884X_CDC_PATH_MODE (WSA884X_DIG_CTRL0_BASE + 0x1a)
285 #define WSA884X_CDC_PATH_MODE_RXD_MODE_MASK 0x02
286 #define WSA884X_CDC_PATH_MODE_RXD_MODE_SHIFT 0
287 #define WSA884X_CDC_PATH_MODE_TXD_MODE_MASK 0x01
288 #define WSA884X_CDC_PATH_MODE_TXD_MODE_SHIFT 0
289 #define WSA884X_CDC_CLK_CTL (WSA884X_DIG_CTRL0_BASE + 0x1c)
290 #define WSA884X_PA_FSM_EN (WSA884X_DIG_CTRL0_BASE + 0x30)
291 #define WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK 0x01
292 #define WSA884X_PA_FSM_EN_GLOBAL_PA_EN_SHIFT 0
293 #define WSA884X_PA_FSM_CTL0 (WSA884X_DIG_CTRL0_BASE + 0x31)
294 #define WSA884X_PA_FSM_CTL1 (WSA884X_DIG_CTRL0_BASE + 0x32)
295 #define WSA884X_PA_FSM_CTL1_NOISE_GATE_BLOCK_MASK 0x38
296 #define WSA884X_PA_FSM_TIMER0 (WSA884X_DIG_CTRL0_BASE + 0x33)
297 #define WSA884X_PA_FSM_TIMER1 (WSA884X_DIG_CTRL0_BASE + 0x34)
298 #define WSA884X_PA_FSM_STA0 (WSA884X_DIG_CTRL0_BASE + 0x35)
299 #define WSA884X_PA_FSM_STA1 (WSA884X_DIG_CTRL0_BASE + 0x36)
300 #define WSA884X_PA_FSM_ERR_CTL (WSA884X_DIG_CTRL0_BASE + 0x37)
301 #define WSA884X_PA_FSM_ERR_COND0 (WSA884X_DIG_CTRL0_BASE + 0x38)
302 #define WSA884X_PA_FSM_ERR_COND1 (WSA884X_DIG_CTRL0_BASE + 0x39)
303 #define WSA884X_PA_FSM_MSK0 (WSA884X_DIG_CTRL0_BASE + 0x3a)
304 #define WSA884X_PA_FSM_MSK1 (WSA884X_DIG_CTRL0_BASE + 0x3b)
305 #define WSA884X_PA_FSM_BYP_CTL (WSA884X_DIG_CTRL0_BASE + 0x3c)
306 #define WSA884X_PA_FSM_BYP0 (WSA884X_DIG_CTRL0_BASE + 0x3d)
307 #define WSA884X_PA_FSM_BYP0_DC_CAL_EN_MASK 0x01
308 #define WSA884X_PA_FSM_BYP0_DC_CAL_EN_SHIFT 0
309 #define WSA884X_PA_FSM_BYP0_CLK_WD_EN_MASK 0x02
310 #define WSA884X_PA_FSM_BYP0_CLK_WD_EN_SHIFT 1
311 #define WSA884X_PA_FSM_BYP0_BG_EN_MASK 0x04
312 #define WSA884X_PA_FSM_BYP0_BG_EN_SHIFT 2
313 #define WSA884X_PA_FSM_BYP0_BOOST_EN_MASK 0x08
314 #define WSA884X_PA_FSM_BYP0_BOOST_EN_SHIFT 3
315 #define WSA884X_PA_FSM_BYP0_PA_EN_MASK 0x10
316 #define WSA884X_PA_FSM_BYP0_PA_EN_SHIFT 4
317 #define WSA884X_PA_FSM_BYP0_D_UNMUTE_MASK 0x20
318 #define WSA884X_PA_FSM_BYP0_D_UNMUTE_SHIFT 5
319 #define WSA884X_PA_FSM_BYP0_SPKR_PROT_EN_MASK 0x40
320 #define WSA884X_PA_FSM_BYP0_SPKR_PROT_EN_SHIFT 6
321 #define WSA884X_PA_FSM_BYP0_TSADC_EN_MASK 0x80
322 #define WSA884X_PA_FSM_BYP0_TSADC_EN_SHIFT 7
323 #define WSA884X_PA_FSM_BYP1 (WSA884X_DIG_CTRL0_BASE + 0x3e)
324 #define WSA884X_TADC_VALUE_CTL (WSA884X_DIG_CTRL0_BASE + 0x50)
325 #define WSA884X_TADC_VALUE_CTL_TEMP_VALUE_RD_EN_MASK 0x01
326 #define WSA884X_TADC_VALUE_CTL_TEMP_VALUE_RD_EN_SHIFT 0
327 #define WSA884X_TADC_VALUE_CTL_VBAT_VALUE_RD_EN_MASK 0x02
328 #define WSA884X_TADC_VALUE_CTL_VBAT_VALUE_RD_EN_SHIFT 1
329 #define WSA884X_TEMP_DETECT_CTL (WSA884X_DIG_CTRL0_BASE + 0x51)
330 #define WSA884X_TEMP_DIN_MSB (WSA884X_DIG_CTRL0_BASE + 0x52)
331 #define WSA884X_TEMP_DIN_LSB (WSA884X_DIG_CTRL0_BASE + 0x53)
332 #define WSA884X_TEMP_DOUT_MSB (WSA884X_DIG_CTRL0_BASE + 0x54)
333 #define WSA884X_TEMP_DOUT_LSB (WSA884X_DIG_CTRL0_BASE + 0x55)
334 #define WSA884X_TEMP_CONFIG0 (WSA884X_DIG_CTRL0_BASE + 0x56)
335 #define WSA884X_TEMP_CONFIG1 (WSA884X_DIG_CTRL0_BASE + 0x57)
336 #define WSA884X_VBAT_THRM_FLT_CTL (WSA884X_DIG_CTRL0_BASE + 0x58)
337 #define WSA884X_VBAT_THRM_FLT_CTL_THRM_COEF_SEL_MASK 0xe0
338 #define WSA884X_VBAT_THRM_FLT_CTL_THRM_COEF_SEL_SHIFT 5
339 #define WSA884X_VBAT_THRM_FLT_CTL_THRM_FLT_EN_SHIFT 4
340 #define WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_MASK 0x0e
341 #define WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_SHIFT 1
342 #define WSA884X_VBAT_THRM_FLT_CTL_VBAT_FLT_EN_SHIFT 0
343 #define WSA884X_VBAT_CAL_CTL (WSA884X_DIG_CTRL0_BASE + 0x59)
344 #define WSA884X_VBAT_CAL_CTL_RESERVE_MASK 0x0e
345 #define WSA884X_VBAT_CAL_CTL_VBAT_CAL_EN_MASK 0x01
346 #define WSA884X_VBAT_DIN_MSB (WSA884X_DIG_CTRL0_BASE + 0x5a)
347 #define WSA884X_VBAT_DIN_LSB (WSA884X_DIG_CTRL0_BASE + 0x5b)
348 #define WSA884X_VBAT_DOUT_MSB (WSA884X_DIG_CTRL0_BASE + 0x5c)
349 #define WSA884X_VBAT_DOUT_LSB (WSA884X_DIG_CTRL0_BASE + 0x5d)
350 #define WSA884X_VBAT_CAL_MSB (WSA884X_DIG_CTRL0_BASE + 0x5e)
351 #define WSA884X_VBAT_CAL_LSB (WSA884X_DIG_CTRL0_BASE + 0x5f)
352 #define WSA884X_UVLO_DEGLITCH_CTL (WSA884X_DIG_CTRL0_BASE + 0x60)
353 #define WSA884X_BOP_DEGLITCH_CTL (WSA884X_DIG_CTRL0_BASE + 0x61)
354 #define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_SETTING_MASK 0x1e
355 #define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_SETTING_SHIFT 1
356 #define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_EN_MASK 0x1
357 #define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_EN_SHIFT 0
358 #define WSA884X_VBAT_ZONE_DETC_CTL (WSA884X_DIG_CTRL0_BASE + 0x64)
359 #define WSA884X_CPS_CTL (WSA884X_DIG_CTRL0_BASE + 0x68)
360 #define WSA884X_CDC_RX_CTL (WSA884X_DIG_CTRL0_BASE + 0x70)
361 #define WSA884X_CDC_SPK_DSM_A1_0 (WSA884X_DIG_CTRL0_BASE + 0x71)
362 #define WSA884X_CDC_SPK_DSM_A1_1 (WSA884X_DIG_CTRL0_BASE + 0x72)
363 #define WSA884X_CDC_SPK_DSM_A2_0 (WSA884X_DIG_CTRL0_BASE + 0x73)
364 #define WSA884X_CDC_SPK_DSM_A2_1 (WSA884X_DIG_CTRL0_BASE + 0x74)
365 #define WSA884X_CDC_SPK_DSM_A3_0 (WSA884X_DIG_CTRL0_BASE + 0x75)
366 #define WSA884X_CDC_SPK_DSM_A3_1 (WSA884X_DIG_CTRL0_BASE + 0x76)
367 #define WSA884X_CDC_SPK_DSM_A4_0 (WSA884X_DIG_CTRL0_BASE + 0x77)
368 #define WSA884X_CDC_SPK_DSM_A4_1 (WSA884X_DIG_CTRL0_BASE + 0x78)
369 #define WSA884X_CDC_SPK_DSM_A5_0 (WSA884X_DIG_CTRL0_BASE + 0x79)
370 #define WSA884X_CDC_SPK_DSM_A5_1 (WSA884X_DIG_CTRL0_BASE + 0x7a)
371 #define WSA884X_CDC_SPK_DSM_A6_0 (WSA884X_DIG_CTRL0_BASE + 0x7b)
372 #define WSA884X_CDC_SPK_DSM_A7_0 (WSA884X_DIG_CTRL0_BASE + 0x7c)
373 #define WSA884X_CDC_SPK_DSM_C_0 (WSA884X_DIG_CTRL0_BASE + 0x7d)
374 #define WSA884X_CDC_SPK_DSM_C_0_COEF_C3_MASK 0xf0
375 #define WSA884X_CDC_SPK_DSM_C_0_COEF_C3_SHIFT 4
376 #define WSA884X_CDC_SPK_DSM_C_0_COEF_C2_MASK 0x0f
377 #define WSA884X_CDC_SPK_DSM_C_0_COEF_C2_SHIFT 0
378 #define WSA884X_CDC_SPK_DSM_C_1 (WSA884X_DIG_CTRL0_BASE + 0x7e)
379 #define WSA884X_CDC_SPK_DSM_C_2 (WSA884X_DIG_CTRL0_BASE + 0x7f)
380 #define WSA884X_CDC_SPK_DSM_C_2_COEF_C7_MASK 0xf0
381 #define WSA884X_CDC_SPK_DSM_C_2_COEF_C7_SHIFT 4
382 #define WSA884X_CDC_SPK_DSM_C_2_COEF_C6_MASK 0x0f
383 #define WSA884X_CDC_SPK_DSM_C_2_COEF_C6_SHIFT 0
384 #define WSA884X_CDC_SPK_DSM_C_3 (WSA884X_DIG_CTRL0_BASE + 0x80)
385 #define WSA884X_CDC_SPK_DSM_C_3_COEF_C7_MASK 0x3f
386 #define WSA884X_CDC_SPK_DSM_C_3_COEF_C7_SHIFT 0
387 #define WSA884X_CDC_SPK_DSM_R1 (WSA884X_DIG_CTRL0_BASE + 0x81)
388 #define WSA884X_CDC_SPK_DSM_R2 (WSA884X_DIG_CTRL0_BASE + 0x82)
389 #define WSA884X_CDC_SPK_DSM_R3 (WSA884X_DIG_CTRL0_BASE + 0x83)
390 #define WSA884X_CDC_SPK_DSM_R4 (WSA884X_DIG_CTRL0_BASE + 0x84)
391 #define WSA884X_CDC_SPK_DSM_R5 (WSA884X_DIG_CTRL0_BASE + 0x85)
392 #define WSA884X_CDC_SPK_DSM_R6 (WSA884X_DIG_CTRL0_BASE + 0x86)
393 #define WSA884X_CDC_SPK_DSM_R7 (WSA884X_DIG_CTRL0_BASE + 0x87)
394 #define WSA884X_CDC_SPK_GAIN_PDM_0 (WSA884X_DIG_CTRL0_BASE + 0x88)
395 #define WSA884X_CDC_SPK_GAIN_PDM_1 (WSA884X_DIG_CTRL0_BASE + 0x89)
396 #define WSA884X_CDC_SPK_GAIN_PDM_2 (WSA884X_DIG_CTRL0_BASE + 0x8a)
397 #define WSA884X_PDM_WD_CTL (WSA884X_DIG_CTRL0_BASE + 0x8b)
398 #define WSA884X_PDM_WD_CTL_HOLD_OFF_MASK 0x04
399 #define WSA884X_PDM_WD_CTL_HOLD_OFF_SHIFT 2
400 #define WSA884X_PDM_WD_CTL_TIME_OUT_SEL_MASK 0x02
401 #define WSA884X_PDM_WD_CTL_TIME_OUT_SEL_SHIFT 1
402 #define WSA884X_PDM_WD_CTL_PDM_WD_EN_MASK 0x01
403 #define WSA884X_PDM_WD_CTL_PDM_WD_EN_SHIFT 0
404 #define WSA884X_DEM_BYPASS_DATA0 (WSA884X_DIG_CTRL0_BASE + 0x90)
405 #define WSA884X_DEM_BYPASS_DATA1 (WSA884X_DIG_CTRL0_BASE + 0x91)
406 #define WSA884X_DEM_BYPASS_DATA2 (WSA884X_DIG_CTRL0_BASE + 0x92)
407 #define WSA884X_DEM_BYPASS_DATA3 (WSA884X_DIG_CTRL0_BASE + 0x93)
408 #define WSA884X_DRE_CTL_0 (WSA884X_DIG_CTRL0_BASE + 0xb0)
409 #define WSA884X_DRE_CTL_0_PROG_DELAY_MASK 0xf0
410 #define WSA884X_DRE_CTL_0_PROG_DELAY_SHIFT 4
411 #define WSA884X_DRE_CTL_0_OFFSET_MASK 0x07
412 #define WSA884X_DRE_CTL_0_OFFSET_SHIFT 0
413 #define WSA884X_DRE_CTL_1 (WSA884X_DIG_CTRL0_BASE + 0xb1)
414 #define WSA884X_DRE_CTL_1_CSR_GAIN_MASK 0x3e
415 #define WSA884X_DRE_CTL_1_CSR_GAIN_SHIFT 1
416 #define WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK 0x01
417 #define WSA884X_DRE_CTL_1_CSR_GAIN_EN_SHIFT 0
418 #define WSA884X_DRE_IDLE_DET_CTL (WSA884X_DIG_CTRL0_BASE + 0xb2)
419 #define WSA884X_GAIN_RAMPING_CTL (WSA884X_DIG_CTRL0_BASE + 0xb8)
420 #define WSA884X_GAIN_RAMPING_MIN (WSA884X_DIG_CTRL0_BASE + 0xb9)
421 #define WSA884X_GAIN_RAMPING_MIN_MIN_GAIN_MASK 0x1f
422 #define WSA884X_GAIN_RAMPING_MIN_MIN_GAIN_SHIFT 0
423 #define WSA884X_TAGC_CTL (WSA884X_DIG_CTRL0_BASE + 0xc0)
424 #define WSA884X_TAGC_TIME (WSA884X_DIG_CTRL0_BASE + 0xc1)
425 #define WSA884X_TAGC_FORCE_VAL (WSA884X_DIG_CTRL0_BASE + 0xc2)
426 #define WSA884X_VAGC_CTL (WSA884X_DIG_CTRL0_BASE + 0xc8)
427 #define WSA884X_VAGC_TIME (WSA884X_DIG_CTRL0_BASE + 0xc9)
428 #define WSA884X_VAGC_ATTN_LVL_1 (WSA884X_DIG_CTRL0_BASE + 0xca)
429 #define WSA884X_VAGC_ATTN_LVL_2 (WSA884X_DIG_CTRL0_BASE + 0xcb)
430 #define WSA884X_VAGC_ATTN_LVL_3 (WSA884X_DIG_CTRL0_BASE + 0xcc)
431 #define WSA884X_CLSH_CTL_0 (WSA884X_DIG_CTRL0_BASE + 0xd0)
432 #define WSA884X_CLSH_CTL_0_CSR_GAIN_EN_SHIFT 7
433 #define WSA884X_CLSH_CTL_0_DLY_CODE_MASK 0x70
434 #define WSA884X_CLSH_CTL_0_DLY_CODE_SHIFT 4
435 #define WSA884X_CLSH_CTL_0_DLY_RST_SHIFT 3
436 #define WSA884X_CLSH_CTL_0_DLY_EN_SHIFT 2
437 #define WSA884X_CLSH_CTL_0_INPUT_EN_SHIFT 1
438 #define WSA884X_CLSH_CTL_0_CLSH_EN_SHIFT 0
439 #define WSA884X_CLSH_CTL_1 (WSA884X_DIG_CTRL0_BASE + 0xd1)
440 #define WSA884X_CLSH_V_HD_PA (WSA884X_DIG_CTRL0_BASE + 0xd2)
441 #define WSA884X_CLSH_V_PA_MIN (WSA884X_DIG_CTRL0_BASE + 0xd3)
442 #define WSA884X_CLSH_OVRD_VAL (WSA884X_DIG_CTRL0_BASE + 0xd4)
443 #define WSA884X_CLSH_HARD_MAX (WSA884X_DIG_CTRL0_BASE + 0xd5)
444 #define WSA884X_CLSH_SOFT_MAX (WSA884X_DIG_CTRL0_BASE + 0xd6)
445 #define WSA884X_CLSH_SIG_DP (WSA884X_DIG_CTRL0_BASE + 0xd7)
446 #define WSA884X_PBR_DELAY_CTL (WSA884X_DIG_CTRL0_BASE + 0xd8)
447 #define WSA884X_CLSH_SRL_MAX_PBR (WSA884X_DIG_CTRL0_BASE + 0xe0)
448 #define WSA884X_PBR_MAX_VOLTAGE 20
449 #define WSA884X_PBR_MAX_CODE 255
450 #define WSA884X_VTH_TO_REG(vth) \
451 ((vth) != 0 ? (((vth) - 150) * WSA884X_PBR_MAX_CODE / (WSA884X_PBR_MAX_VOLTAGE * 100) + 1) : 0)
452 #define WSA884X_CLSH_VTH1 (WSA884X_DIG_CTRL0_BASE + 0xe1)
453 #define WSA884X_CLSH_VTH2 (WSA884X_DIG_CTRL0_BASE + 0xe2)
454 #define WSA884X_CLSH_VTH3 (WSA884X_DIG_CTRL0_BASE + 0xe3)
455 #define WSA884X_CLSH_VTH4 (WSA884X_DIG_CTRL0_BASE + 0xe4)
456 #define WSA884X_CLSH_VTH5 (WSA884X_DIG_CTRL0_BASE + 0xe5)
457 #define WSA884X_CLSH_VTH6 (WSA884X_DIG_CTRL0_BASE + 0xe6)
458 #define WSA884X_CLSH_VTH7 (WSA884X_DIG_CTRL0_BASE + 0xe7)
459 #define WSA884X_CLSH_VTH8 (WSA884X_DIG_CTRL0_BASE + 0xe8)
460 #define WSA884X_CLSH_VTH9 (WSA884X_DIG_CTRL0_BASE + 0xe9)
461 #define WSA884X_CLSH_VTH10 (WSA884X_DIG_CTRL0_BASE + 0xea)
462 #define WSA884X_CLSH_VTH11 (WSA884X_DIG_CTRL0_BASE + 0xeb)
463 #define WSA884X_CLSH_VTH12 (WSA884X_DIG_CTRL0_BASE + 0xec)
464 #define WSA884X_CLSH_VTH13 (WSA884X_DIG_CTRL0_BASE + 0xed)
465 #define WSA884X_CLSH_VTH14 (WSA884X_DIG_CTRL0_BASE + 0xee)
466 #define WSA884X_CLSH_VTH15 (WSA884X_DIG_CTRL0_BASE + 0xef)
467
468 #define WSA884X_DIG_CTRL1_BASE (WSA884X_BASE + 0x0500)
469 #define WSA884X_DIG_CTRL1_PAGE (WSA884X_DIG_CTRL1_BASE + 0x00)
470 #define WSA884X_VPHX_SYS_EN_STATUS (WSA884X_DIG_CTRL1_BASE + 0x01)
471 #define WSA884X_ANA_WO_CTL_0 (WSA884X_DIG_CTRL1_BASE + 0x04)
472 #define WSA884X_ANA_WO_CTL_0_MODE_SHIFT 0
473 #define WSA884X_ANA_WO_CTL_0_VPHX_SYS_EN_MASK 0xc0
474 #define WSA884X_ANA_WO_CTL_0_PA_AUX_DISABLE 0x0
475 #define WSA884X_ANA_WO_CTL_0_PA_AUX_18_DB 0xa
476 #define WSA884X_ANA_WO_CTL_0_PA_AUX_0_DB 0x7
477 #define WSA884X_ANA_WO_CTL_0_PA_AUX_GAIN_MASK 0x3c
478 #define WSA884X_ANA_WO_CTL_0_PA_MIN_GAIN_BYP_MASK 0x02
479 #define WSA884X_ANA_WO_CTL_0_DAC_CM_CLAMP_EN_MODE_SPEAKER 0x1
480 #define WSA884X_ANA_WO_CTL_0_DAC_CM_CLAMP_EN_MASK 0x01
481 #define WSA884X_ANA_WO_CTL_1 (WSA884X_DIG_CTRL1_BASE + 0x05)
482 #define WSA884X_PIN_CTL (WSA884X_DIG_CTRL1_BASE + 0x10)
483 #define WSA884X_PIN_CTL_OE (WSA884X_DIG_CTRL1_BASE + 0x11)
484 #define WSA884X_PIN_WDATA_IOPAD (WSA884X_DIG_CTRL1_BASE + 0x12)
485 #define WSA884X_PIN_STATUS (WSA884X_DIG_CTRL1_BASE + 0x13)
486 #define WSA884X_I2C_SLAVE_CTL (WSA884X_DIG_CTRL1_BASE + 0x14)
487 #define WSA884X_SPMI_PAD_CTL0 (WSA884X_DIG_CTRL1_BASE + 0x15)
488 #define WSA884X_SPMI_PAD_CTL1 (WSA884X_DIG_CTRL1_BASE + 0x16)
489 #define WSA884X_SPMI_PAD_CTL2 (WSA884X_DIG_CTRL1_BASE + 0x17)
490 #define WSA884X_MEM_CTL (WSA884X_DIG_CTRL1_BASE + 0x18)
491 #define WSA884X_SWR_HM_TEST0 (WSA884X_DIG_CTRL1_BASE + 0x19)
492 #define WSA884X_SWR_HM_TEST1 (WSA884X_DIG_CTRL1_BASE + 0x1a)
493 #define WSA884X_OTP_CTRL0 (WSA884X_DIG_CTRL1_BASE + 0x30)
494 #define WSA884X_OTP_CTRL1 (WSA884X_DIG_CTRL1_BASE + 0x31)
495 #define WSA884X_OTP_CTRL2 (WSA884X_DIG_CTRL1_BASE + 0x32)
496 #define WSA884X_OTP_STAT (WSA884X_DIG_CTRL1_BASE + 0x33)
497 #define WSA884X_OTP_PRG_TCSP0 (WSA884X_DIG_CTRL1_BASE + 0x34)
498 #define WSA884X_OTP_PRG_TCSP1 (WSA884X_DIG_CTRL1_BASE + 0x35)
499 #define WSA884X_OTP_PRG_TPPS (WSA884X_DIG_CTRL1_BASE + 0x36)
500 #define WSA884X_OTP_PRG_TVPS (WSA884X_DIG_CTRL1_BASE + 0x37)
501 #define WSA884X_OTP_PRG_TVPH (WSA884X_DIG_CTRL1_BASE + 0x38)
502 #define WSA884X_OTP_PRG_TPPR0 (WSA884X_DIG_CTRL1_BASE + 0x39)
503 #define WSA884X_OTP_PRG_TPPR1 (WSA884X_DIG_CTRL1_BASE + 0x3a)
504 #define WSA884X_OTP_PRG_TPPH (WSA884X_DIG_CTRL1_BASE + 0x3b)
505 #define WSA884X_OTP_PRG_END (WSA884X_DIG_CTRL1_BASE + 0x3c)
506 #define WSA884X_WAVG_PLAY (WSA884X_DIG_CTRL1_BASE + 0x40)
507 #define WSA884X_WAVG_CTL (WSA884X_DIG_CTRL1_BASE + 0x41)
508 #define WSA884X_WAVG_LRA_PER_0 (WSA884X_DIG_CTRL1_BASE + 0x43)
509 #define WSA884X_WAVG_LRA_PER_1 (WSA884X_DIG_CTRL1_BASE + 0x44)
510 #define WSA884X_WAVG_DELTA_THETA_0 (WSA884X_DIG_CTRL1_BASE + 0x45)
511 #define WSA884X_WAVG_DELTA_THETA_1 (WSA884X_DIG_CTRL1_BASE + 0x46)
512 #define WSA884X_WAVG_DIRECT_AMP_0 (WSA884X_DIG_CTRL1_BASE + 0x47)
513 #define WSA884X_WAVG_DIRECT_AMP_1 (WSA884X_DIG_CTRL1_BASE + 0x48)
514 #define WSA884X_WAVG_PTRN_AMP0_0 (WSA884X_DIG_CTRL1_BASE + 0x49)
515 #define WSA884X_WAVG_PTRN_AMP0_1 (WSA884X_DIG_CTRL1_BASE + 0x4a)
516 #define WSA884X_WAVG_PTRN_AMP1_0 (WSA884X_DIG_CTRL1_BASE + 0x4b)
517 #define WSA884X_WAVG_PTRN_AMP1_1 (WSA884X_DIG_CTRL1_BASE + 0x4c)
518 #define WSA884X_WAVG_PTRN_AMP2_0 (WSA884X_DIG_CTRL1_BASE + 0x4d)
519 #define WSA884X_WAVG_PTRN_AMP2_1 (WSA884X_DIG_CTRL1_BASE + 0x4e)
520 #define WSA884X_WAVG_PTRN_AMP3_0 (WSA884X_DIG_CTRL1_BASE + 0x4f)
521 #define WSA884X_WAVG_PTRN_AMP3_1 (WSA884X_DIG_CTRL1_BASE + 0x50)
522 #define WSA884X_WAVG_PTRN_AMP4_0 (WSA884X_DIG_CTRL1_BASE + 0x51)
523 #define WSA884X_WAVG_PTRN_AMP4_1 (WSA884X_DIG_CTRL1_BASE + 0x52)
524 #define WSA884X_WAVG_PTRN_AMP5_0 (WSA884X_DIG_CTRL1_BASE + 0x53)
525 #define WSA884X_WAVG_PTRN_AMP5_1 (WSA884X_DIG_CTRL1_BASE + 0x54)
526 #define WSA884X_WAVG_PTRN_AMP6_0 (WSA884X_DIG_CTRL1_BASE + 0x55)
527 #define WSA884X_WAVG_PTRN_AMP6_1 (WSA884X_DIG_CTRL1_BASE + 0x56)
528 #define WSA884X_WAVG_PTRN_AMP7_0 (WSA884X_DIG_CTRL1_BASE + 0x57)
529 #define WSA884X_WAVG_PTRN_AMP7_1 (WSA884X_DIG_CTRL1_BASE + 0x58)
530 #define WSA884X_WAVG_PER_0_1 (WSA884X_DIG_CTRL1_BASE + 0x59)
531 #define WSA884X_WAVG_PER_2_3 (WSA884X_DIG_CTRL1_BASE + 0x5a)
532 #define WSA884X_WAVG_PER_4_5 (WSA884X_DIG_CTRL1_BASE + 0x5b)
533 #define WSA884X_WAVG_PER_6_7 (WSA884X_DIG_CTRL1_BASE + 0x5c)
534 #define WSA884X_WAVG_STA (WSA884X_DIG_CTRL1_BASE + 0x5d)
535 #define WSA884X_INTR_MODE (WSA884X_DIG_CTRL1_BASE + 0x80)
536 #define WSA884X_INTR_MASK0 (WSA884X_DIG_CTRL1_BASE + 0x81)
537 #define WSA884X_INTR_MASK1 (WSA884X_DIG_CTRL1_BASE + 0x82)
538 #define WSA884X_INTR_STATUS0 (WSA884X_DIG_CTRL1_BASE + 0x83)
539 #define WSA884X_INTR_STATUS1 (WSA884X_DIG_CTRL1_BASE + 0x84)
540 #define WSA884X_INTR_CLEAR0 (WSA884X_DIG_CTRL1_BASE + 0x85)
541 #define WSA884X_INTR_CLEAR1 (WSA884X_DIG_CTRL1_BASE + 0x86)
542 #define WSA884X_INTR_LEVEL0 (WSA884X_DIG_CTRL1_BASE + 0x87)
543 #define WSA884X_INTR_LEVEL1 (WSA884X_DIG_CTRL1_BASE + 0x88)
544 #define WSA884X_INTR_SET0 (WSA884X_DIG_CTRL1_BASE + 0x89)
545 #define WSA884X_INTR_SET1 (WSA884X_DIG_CTRL1_BASE + 0x8a)
546 #define WSA884X_INTR_TEST0 (WSA884X_DIG_CTRL1_BASE + 0x8b)
547 #define WSA884X_INTR_TEST1 (WSA884X_DIG_CTRL1_BASE + 0x8c)
548 #define WSA884X_PDM_TEST_MODE (WSA884X_DIG_CTRL1_BASE + 0xc0)
549 #define WSA884X_ATE_TEST_MODE (WSA884X_DIG_CTRL1_BASE + 0xc1)
550 #define WSA884X_PA_FSM_DBG (WSA884X_DIG_CTRL1_BASE + 0xc2)
551 #define WSA884X_DIG_DEBUG_MODE (WSA884X_DIG_CTRL1_BASE + 0xc3)
552 #define WSA884X_DIG_DEBUG_SEL (WSA884X_DIG_CTRL1_BASE + 0xc4)
553 #define WSA884X_DIG_DEBUG_EN (WSA884X_DIG_CTRL1_BASE + 0xc5)
554 #define WSA884X_TADC_DETECT_DBG_CTL (WSA884X_DIG_CTRL1_BASE + 0xc9)
555 #define WSA884X_TADC_DEBUG_MSB (WSA884X_DIG_CTRL1_BASE + 0xca)
556 #define WSA884X_TADC_DEBUG_LSB (WSA884X_DIG_CTRL1_BASE + 0xcb)
557 #define WSA884X_SAMPLE_EDGE_SEL (WSA884X_DIG_CTRL1_BASE + 0xcc)
558 #define WSA884X_SWR_EDGE_SEL (WSA884X_DIG_CTRL1_BASE + 0xcd)
559 #define WSA884X_TEST_MODE_CTL (WSA884X_DIG_CTRL1_BASE + 0xce)
560 #define WSA884X_IOPAD_CTL (WSA884X_DIG_CTRL1_BASE + 0xcf)
561 #define WSA884X_ANA_CSR_DBG_ADD (WSA884X_DIG_CTRL1_BASE + 0xd0)
562 #define WSA884X_ANA_CSR_DBG_CTL (WSA884X_DIG_CTRL1_BASE + 0xd1)
563 #define WSA884X_CLK_DBG_CTL (WSA884X_DIG_CTRL1_BASE + 0xd2)
564 #define WSA884X_SPARE_R (WSA884X_DIG_CTRL1_BASE + 0xf0)
565 #define WSA884X_SPARE_0 (WSA884X_DIG_CTRL1_BASE + 0xf1)
566 #define WSA884X_SPARE_1 (WSA884X_DIG_CTRL1_BASE + 0xf2)
567 #define WSA884X_SPARE_2 (WSA884X_DIG_CTRL1_BASE + 0xf3)
568 #define WSA884X_SCODE (WSA884X_DIG_CTRL1_BASE + 0xff)
569
570 #define WSA884X_DIG_TRIM_BASE (WSA884X_BASE + 0x0800)
571 #define WSA884X_DIG_TRIM_PAGE (WSA884X_DIG_TRIM_BASE + 0x00)
572 #define WSA884X_OTP_REG_0 (WSA884X_DIG_TRIM_BASE + 0x80)
573 #define WSA884X_OTP_ID_WSA8840 0x0
574 #define WSA884X_OTP_ID_WSA8845 0x5
575 #define WSA884X_OTP_ID_WSA8845H 0xc
576 #define WSA884X_OTP_REG_0_ID_MASK 0x0f
577 #define WSA884X_OTP_REG_1 (WSA884X_DIG_TRIM_BASE + 0x81)
578 #define WSA884X_OTP_REG_2 (WSA884X_DIG_TRIM_BASE + 0x82)
579 #define WSA884X_OTP_REG_3 (WSA884X_DIG_TRIM_BASE + 0x83)
580 #define WSA884X_OTP_REG_4 (WSA884X_DIG_TRIM_BASE + 0x84)
581 #define WSA884X_OTP_REG_5 (WSA884X_DIG_TRIM_BASE + 0x85)
582 #define WSA884X_OTP_REG_6 (WSA884X_DIG_TRIM_BASE + 0x86)
583 #define WSA884X_OTP_REG_7 (WSA884X_DIG_TRIM_BASE + 0x87)
584 #define WSA884X_OTP_REG_8 (WSA884X_DIG_TRIM_BASE + 0x88)
585 #define WSA884X_OTP_REG_9 (WSA884X_DIG_TRIM_BASE + 0x89)
586 #define WSA884X_OTP_REG_10 (WSA884X_DIG_TRIM_BASE + 0x8a)
587 #define WSA884X_OTP_REG_11 (WSA884X_DIG_TRIM_BASE + 0x8b)
588 #define WSA884X_OTP_REG_12 (WSA884X_DIG_TRIM_BASE + 0x8c)
589 #define WSA884X_OTP_REG_13 (WSA884X_DIG_TRIM_BASE + 0x8d)
590 #define WSA884X_OTP_REG_14 (WSA884X_DIG_TRIM_BASE + 0x8e)
591 #define WSA884X_OTP_REG_15 (WSA884X_DIG_TRIM_BASE + 0x8f)
592 #define WSA884X_OTP_REG_16 (WSA884X_DIG_TRIM_BASE + 0x90)
593 #define WSA884X_OTP_REG_17 (WSA884X_DIG_TRIM_BASE + 0x91)
594 #define WSA884X_OTP_REG_18 (WSA884X_DIG_TRIM_BASE + 0x92)
595 #define WSA884X_OTP_REG_19 (WSA884X_DIG_TRIM_BASE + 0x93)
596 #define WSA884X_OTP_REG_20 (WSA884X_DIG_TRIM_BASE + 0x94)
597 #define WSA884X_OTP_REG_21 (WSA884X_DIG_TRIM_BASE + 0x95)
598 #define WSA884X_OTP_REG_22 (WSA884X_DIG_TRIM_BASE + 0x96)
599 #define WSA884X_OTP_REG_23 (WSA884X_DIG_TRIM_BASE + 0x97)
600 #define WSA884X_OTP_REG_24 (WSA884X_DIG_TRIM_BASE + 0x98)
601 #define WSA884X_OTP_REG_25 (WSA884X_DIG_TRIM_BASE + 0x99)
602 #define WSA884X_OTP_REG_26 (WSA884X_DIG_TRIM_BASE + 0x9a)
603 #define WSA884X_OTP_REG_27 (WSA884X_DIG_TRIM_BASE + 0x9b)
604 #define WSA884X_OTP_REG_28 (WSA884X_DIG_TRIM_BASE + 0x9c)
605 #define WSA884X_OTP_REG_29 (WSA884X_DIG_TRIM_BASE + 0x9d)
606 #define WSA884X_OTP_REG_30 (WSA884X_DIG_TRIM_BASE + 0x9e)
607 #define WSA884X_OTP_REG_31 (WSA884X_DIG_TRIM_BASE + 0x9f)
608 #define WSA884X_OTP_REG_32 (WSA884X_DIG_TRIM_BASE + 0xa0)
609 #define WSA884X_OTP_REG_33 (WSA884X_DIG_TRIM_BASE + 0xa1)
610 #define WSA884X_OTP_REG_34 (WSA884X_DIG_TRIM_BASE + 0xa2)
611 #define WSA884X_OTP_REG_35 (WSA884X_DIG_TRIM_BASE + 0xa3)
612 #define WSA884X_OTP_REG_36 (WSA884X_DIG_TRIM_BASE + 0xa4)
613 #define WSA884X_OTP_REG_37 (WSA884X_DIG_TRIM_BASE + 0xa5)
614 #define WSA884X_OTP_REG_38 (WSA884X_DIG_TRIM_BASE + 0xa6)
615 #define WSA884X_OTP_REG_38_RESERVER_MASK 0xf0
616 #define WSA884X_OTP_REG_38_RESERVER_SHIFT 4
617 #define WSA884X_OTP_REG_38_BST_CFG_SEL_MASK 0x08
618 #define WSA884X_OTP_REG_38_BST_CFG_SEL_SHIFT 3
619 #define WSA884X_OTP_REG_38_BOOST_ILIM_TUNE_MASK 0x07
620 #define WSA884X_OTP_REG_38_BOOST_ILIM_TUNE_SHIFT 0
621 #define WSA884X_OTP_REG_39 (WSA884X_DIG_TRIM_BASE + 0xa7)
622 #define WSA884X_OTP_REG_40 (WSA884X_DIG_TRIM_BASE + 0xa8)
623 #define WSA884X_OTP_REG_40_SPARE_TYPE2_MASK 0xc0
624 #define WSA884X_OTP_REG_40_SPARE_TYPE2_SHIFT 6
625 #define WSA884X_OTP_REG_40_ISENSE_RESCAL_MASK 0x3c
626 #define WSA884X_OTP_REG_40_ISENSE_RESCAL_SHIFT 2
627 #define WSA884X_OTP_REG_40_ATE_BOOST_RDSON_TEST_MASK 0x2
628 #define WSA884X_OTP_REG_40_ATE_BOOST_RDSON_TEST_SHIFT 1
629 #define WSA884X_OTP_REG_40_ATE_CLASSD_RDSON_TEST_MASK 0x1
630 #define WSA884X_OTP_REG_40_ATE_CLASSD_RDSON_TEST_SHIFT 0
631 #define WSA884X_OTP_REG_41 (WSA884X_DIG_TRIM_BASE + 0xa9)
632 #define WSA884X_OTP_REG_63 (WSA884X_DIG_TRIM_BASE + 0xbf)
633
634 #define WSA884X_DIG_EMEM_BASE (WSA884X_BASE + 0x08C0)
635 #define WSA884X_EMEM_0 (WSA884X_DIG_EMEM_BASE + 0x00)
636 #define WSA884X_EMEM_1 (WSA884X_DIG_EMEM_BASE + 0x01)
637 #define WSA884X_EMEM_2 (WSA884X_DIG_EMEM_BASE + 0x02)
638 #define WSA884X_EMEM_3 (WSA884X_DIG_EMEM_BASE + 0x03)
639 #define WSA884X_EMEM_4 (WSA884X_DIG_EMEM_BASE + 0x04)
640 #define WSA884X_EMEM_5 (WSA884X_DIG_EMEM_BASE + 0x05)
641 #define WSA884X_EMEM_6 (WSA884X_DIG_EMEM_BASE + 0x06)
642 #define WSA884X_EMEM_7 (WSA884X_DIG_EMEM_BASE + 0x07)
643 #define WSA884X_EMEM_8 (WSA884X_DIG_EMEM_BASE + 0x08)
644 #define WSA884X_EMEM_9 (WSA884X_DIG_EMEM_BASE + 0x09)
645 #define WSA884X_EMEM_10 (WSA884X_DIG_EMEM_BASE + 0x0a)
646 #define WSA884X_EMEM_11 (WSA884X_DIG_EMEM_BASE + 0x0b)
647 #define WSA884X_EMEM_12 (WSA884X_DIG_EMEM_BASE + 0x0c)
648 #define WSA884X_EMEM_13 (WSA884X_DIG_EMEM_BASE + 0x0d)
649 #define WSA884X_EMEM_14 (WSA884X_DIG_EMEM_BASE + 0x0e)
650 #define WSA884X_EMEM_15 (WSA884X_DIG_EMEM_BASE + 0x0f)
651 #define WSA884X_EMEM_16 (WSA884X_DIG_EMEM_BASE + 0x10)
652 #define WSA884X_EMEM_17 (WSA884X_DIG_EMEM_BASE + 0x11)
653 #define WSA884X_EMEM_18 (WSA884X_DIG_EMEM_BASE + 0x12)
654 #define WSA884X_EMEM_19 (WSA884X_DIG_EMEM_BASE + 0x13)
655 #define WSA884X_EMEM_20 (WSA884X_DIG_EMEM_BASE + 0x14)
656 #define WSA884X_EMEM_21 (WSA884X_DIG_EMEM_BASE + 0x15)
657 #define WSA884X_EMEM_22 (WSA884X_DIG_EMEM_BASE + 0x16)
658 #define WSA884X_EMEM_23 (WSA884X_DIG_EMEM_BASE + 0x17)
659 #define WSA884X_EMEM_24 (WSA884X_DIG_EMEM_BASE + 0x18)
660 #define WSA884X_EMEM_25 (WSA884X_DIG_EMEM_BASE + 0x19)
661 #define WSA884X_EMEM_26 (WSA884X_DIG_EMEM_BASE + 0x1a)
662 #define WSA884X_EMEM_27 (WSA884X_DIG_EMEM_BASE + 0x1b)
663 #define WSA884X_EMEM_28 (WSA884X_DIG_EMEM_BASE + 0x1c)
664 #define WSA884X_EMEM_29 (WSA884X_DIG_EMEM_BASE + 0x1d)
665 #define WSA884X_EMEM_30 (WSA884X_DIG_EMEM_BASE + 0x1e)
666 #define WSA884X_EMEM_31 (WSA884X_DIG_EMEM_BASE + 0x1f)
667 #define WSA884X_EMEM_32 (WSA884X_DIG_EMEM_BASE + 0x20)
668 #define WSA884X_EMEM_33 (WSA884X_DIG_EMEM_BASE + 0x21)
669 #define WSA884X_EMEM_34 (WSA884X_DIG_EMEM_BASE + 0x22)
670 #define WSA884X_EMEM_35 (WSA884X_DIG_EMEM_BASE + 0x23)
671 #define WSA884X_EMEM_36 (WSA884X_DIG_EMEM_BASE + 0x24)
672 #define WSA884X_EMEM_37 (WSA884X_DIG_EMEM_BASE + 0x25)
673 #define WSA884X_EMEM_38 (WSA884X_DIG_EMEM_BASE + 0x26)
674 #define WSA884X_EMEM_39 (WSA884X_DIG_EMEM_BASE + 0x27)
675 #define WSA884X_EMEM_40 (WSA884X_DIG_EMEM_BASE + 0x28)
676 #define WSA884X_EMEM_41 (WSA884X_DIG_EMEM_BASE + 0x29)
677 #define WSA884X_EMEM_42 (WSA884X_DIG_EMEM_BASE + 0x2a)
678 #define WSA884X_EMEM_43 (WSA884X_DIG_EMEM_BASE + 0x2b)
679 #define WSA884X_EMEM_44 (WSA884X_DIG_EMEM_BASE + 0x2c)
680 #define WSA884X_EMEM_45 (WSA884X_DIG_EMEM_BASE + 0x2d)
681 #define WSA884X_EMEM_46 (WSA884X_DIG_EMEM_BASE + 0x2e)
682 #define WSA884X_EMEM_47 (WSA884X_DIG_EMEM_BASE + 0x2f)
683 #define WSA884X_EMEM_48 (WSA884X_DIG_EMEM_BASE + 0x30)
684 #define WSA884X_EMEM_49 (WSA884X_DIG_EMEM_BASE + 0x31)
685 #define WSA884X_EMEM_50 (WSA884X_DIG_EMEM_BASE + 0x32)
686 #define WSA884X_EMEM_51 (WSA884X_DIG_EMEM_BASE + 0x33)
687 #define WSA884X_EMEM_52 (WSA884X_DIG_EMEM_BASE + 0x34)
688 #define WSA884X_EMEM_53 (WSA884X_DIG_EMEM_BASE + 0x35)
689 #define WSA884X_EMEM_54 (WSA884X_DIG_EMEM_BASE + 0x36)
690 #define WSA884X_EMEM_55 (WSA884X_DIG_EMEM_BASE + 0x37)
691 #define WSA884X_EMEM_56 (WSA884X_DIG_EMEM_BASE + 0x38)
692 #define WSA884X_EMEM_57 (WSA884X_DIG_EMEM_BASE + 0x39)
693 #define WSA884X_EMEM_58 (WSA884X_DIG_EMEM_BASE + 0x3a)
694 #define WSA884X_EMEM_59 (WSA884X_DIG_EMEM_BASE + 0x3b)
695 #define WSA884X_EMEM_60 (WSA884X_DIG_EMEM_BASE + 0x3c)
696 #define WSA884X_EMEM_61 (WSA884X_DIG_EMEM_BASE + 0x3d)
697 #define WSA884X_EMEM_62 (WSA884X_DIG_EMEM_BASE + 0x3e)
698 #define WSA884X_EMEM_63 (WSA884X_DIG_EMEM_BASE + 0x3f)
699
700 #define WSA884X_NUM_REGISTERS (WSA884X_EMEM_63 + 1)
701 #define WSA884X_MAX_REGISTER (WSA884X_NUM_REGISTERS - 1)
702
703 #define WSA884X_SUPPLIES_NUM 2
704 #define WSA884X_MAX_SWR_PORTS 6
705 #define WSA884X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
706 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
707 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
708 SNDRV_PCM_RATE_384000)
709 /* Fractional Rates */
710 #define WSA884X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
711 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
712
713 #define WSA884X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
714 SNDRV_PCM_FMTBIT_S24_LE |\
715 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
716
717 /* Two-point trimming for temperature calibration */
718 #define WSA884X_T1_TEMP -10L
719 #define WSA884X_T2_TEMP 150L
720
721 /*
722 * Device will report senseless data in many cases, so discard any measurements
723 * outside of valid range.
724 */
725 #define WSA884X_LOW_TEMP_THRESHOLD 5
726 #define WSA884X_HIGH_TEMP_THRESHOLD 45
727
728 struct wsa884x_priv {
729 struct regmap *regmap;
730 struct device *dev;
731 struct regulator_bulk_data supplies[WSA884X_SUPPLIES_NUM];
732 struct sdw_slave *slave;
733 struct sdw_stream_config sconfig;
734 struct sdw_stream_runtime *sruntime;
735 struct sdw_port_config port_config[WSA884X_MAX_SWR_PORTS];
736 struct gpio_desc *sd_n;
737 struct reset_control *sd_reset;
738 bool port_prepared[WSA884X_MAX_SWR_PORTS];
739 bool port_enable[WSA884X_MAX_SWR_PORTS];
740 int active_ports;
741 int dev_mode;
742 bool hw_init;
743 /*
744 * Protects temperature reading code (related to speaker protection) and
745 * fields: temperature and pa_on.
746 */
747 struct mutex sp_lock;
748 unsigned int temperature;
749 bool pa_on;
750 };
751
752 enum {
753 COMP_OFFSET0,
754 COMP_OFFSET1,
755 COMP_OFFSET2,
756 COMP_OFFSET3,
757 COMP_OFFSET4,
758 };
759
760 enum wsa884x_gain {
761 G_21_DB = 0,
762 G_19P5_DB,
763 G_18_DB,
764 G_16P5_DB,
765 G_15_DB,
766 G_13P5_DB,
767 G_12_DB,
768 G_10P5_DB,
769 G_9_DB,
770 G_7P5_DB,
771 G_6_DB,
772 G_4P5_DB,
773 G_3_DB,
774 G_1P5_DB,
775 G_0_DB,
776 G_M1P5_DB,
777 G_M3_DB,
778 G_M4P5_DB,
779 G_M6_DB,
780 G_MAX_DB,
781 };
782
783 enum wsa884x_isense {
784 ISENSE_6_DB = 0,
785 ISENSE_12_DB,
786 ISENSE_15_DB,
787 ISENSE_18_DB,
788 };
789
790 enum wsa884x_vsense {
791 VSENSE_M12_DB = 0,
792 VSENSE_M15_DB,
793 VSENSE_M18_DB,
794 VSENSE_M21_DB,
795 VSENSE_M24_DB,
796 };
797
798 enum wsa884x_port_ids {
799 WSA884X_PORT_DAC,
800 WSA884X_PORT_COMP,
801 WSA884X_PORT_BOOST,
802 WSA884X_PORT_PBR,
803 WSA884X_PORT_VISENSE,
804 WSA884X_PORT_CPS,
805 };
806
807 static const char * const wsa884x_supply_name[] = {
808 "vdd-io",
809 "vdd-1p8",
810 };
811
812 static const char * const wsa884x_dev_mode_text[] = {
813 "Speaker", "Receiver"
814 };
815
816 enum wsa884x_mode {
817 WSA884X_SPEAKER,
818 WSA884X_RECEIVER,
819 };
820
821 static const struct soc_enum wsa884x_dev_mode_enum =
822 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa884x_dev_mode_text), wsa884x_dev_mode_text);
823
824 static struct sdw_dpn_prop wsa884x_sink_dpn_prop[WSA884X_MAX_SWR_PORTS] = {
825 [WSA884X_PORT_DAC] = {
826 .num = WSA884X_PORT_DAC + 1,
827 .type = SDW_DPN_SIMPLE,
828 .min_ch = 1,
829 .max_ch = 1,
830 .simple_ch_prep_sm = true,
831 .read_only_wordlength = true,
832 },
833 [WSA884X_PORT_COMP] = {
834 .num = WSA884X_PORT_COMP + 1,
835 .type = SDW_DPN_SIMPLE,
836 .min_ch = 1,
837 .max_ch = 1,
838 .simple_ch_prep_sm = true,
839 .read_only_wordlength = true,
840 },
841 [WSA884X_PORT_BOOST] = {
842 .num = WSA884X_PORT_BOOST + 1,
843 .type = SDW_DPN_SIMPLE,
844 .min_ch = 1,
845 .max_ch = 1,
846 .simple_ch_prep_sm = true,
847 .read_only_wordlength = true,
848 },
849 [WSA884X_PORT_PBR] = {
850 .num = WSA884X_PORT_PBR + 1,
851 .type = SDW_DPN_SIMPLE,
852 .min_ch = 1,
853 .max_ch = 1,
854 .simple_ch_prep_sm = true,
855 .read_only_wordlength = true,
856 },
857 [WSA884X_PORT_VISENSE] = {
858 .num = WSA884X_PORT_VISENSE + 1,
859 .type = SDW_DPN_SIMPLE,
860 .min_ch = 1,
861 .max_ch = 1,
862 .simple_ch_prep_sm = true,
863 .read_only_wordlength = true,
864 },
865 [WSA884X_PORT_CPS] = {
866 .num = WSA884X_PORT_CPS + 1,
867 .type = SDW_DPN_SIMPLE,
868 .min_ch = 1,
869 .max_ch = 1,
870 .simple_ch_prep_sm = true,
871 .read_only_wordlength = true,
872 }
873 };
874
875 static const struct sdw_port_config wsa884x_pconfig[WSA884X_MAX_SWR_PORTS] = {
876 [WSA884X_PORT_DAC] = {
877 .num = WSA884X_PORT_DAC + 1,
878 .ch_mask = 0x1,
879 },
880 [WSA884X_PORT_COMP] = {
881 .num = WSA884X_PORT_COMP + 1,
882 .ch_mask = 0xf,
883 },
884 [WSA884X_PORT_BOOST] = {
885 .num = WSA884X_PORT_BOOST + 1,
886 .ch_mask = 0x3,
887 },
888 [WSA884X_PORT_PBR] = {
889 .num = WSA884X_PORT_PBR + 1,
890 .ch_mask = 0x1,
891 },
892 [WSA884X_PORT_VISENSE] = {
893 .num = WSA884X_PORT_VISENSE + 1,
894 .ch_mask = 0x3,
895 },
896 [WSA884X_PORT_CPS] = {
897 .num = WSA884X_PORT_CPS + 1,
898 .ch_mask = 0x3,
899 },
900 };
901
902 static struct reg_default wsa884x_defaults[] = {
903 { WSA884X_BG_CTRL, 0xa5 },
904 { WSA884X_ADC_CTRL, 0x00 },
905 { WSA884X_BOP1_PROG, 0x22 },
906 { WSA884X_BOP2_PROG, 0x44 },
907 { WSA884X_UVLO_PROG, 0x99 },
908 { WSA884X_UVLO_PROG1, 0x70 },
909 { WSA884X_SPARE_CTRL_0, 0x00 },
910 { WSA884X_SPARE_CTRL_1, 0x00 },
911 { WSA884X_SPARE_CTRL_2, 0x00 },
912 { WSA884X_SPARE_CTRL_3, 0x00 },
913 { WSA884X_REF_CTRL, 0xd2 },
914 { WSA884X_BG_TEST_CTL, 0x06 },
915 { WSA884X_BG_BIAS, 0xd7 },
916 { WSA884X_ADC_PROG, 0x08 },
917 { WSA884X_ADC_IREF_CTL, 0x57 },
918 { WSA884X_ADC_ISENS_CTL, 0x47 },
919 { WSA884X_ADC_CLK_CTL, 0x87 },
920 { WSA884X_ADC_TEST_CTL, 0x00 },
921 { WSA884X_ADC_BIAS, 0x51 },
922 { WSA884X_VBAT_SNS, 0xa0 },
923 { WSA884X_BOP_ATEST_SEL, 0x00 },
924 { WSA884X_MISC0, 0x04 },
925 { WSA884X_MISC1, 0x75 },
926 { WSA884X_MISC2, 0x00 },
927 { WSA884X_MISC3, 0x10 },
928 { WSA884X_SPARE_TSBG_0, 0x00 },
929 { WSA884X_SPARE_TUNE_0, 0x00 },
930 { WSA884X_SPARE_TUNE_1, 0x00 },
931 { WSA884X_VSENSE1, 0xe7 },
932 { WSA884X_ISENSE2, 0x27 },
933 { WSA884X_SPARE_CTL_1, 0x00 },
934 { WSA884X_SPARE_CTL_2, 0x00 },
935 { WSA884X_SPARE_CTL_3, 0x00 },
936 { WSA884X_SPARE_CTL_4, 0x00 },
937 { WSA884X_EN, 0x10 },
938 { WSA884X_OVERRIDE1, 0x00 },
939 { WSA884X_OVERRIDE2, 0x08 },
940 { WSA884X_ISENSE1, 0xd4 },
941 { WSA884X_ISENSE_CAL, 0x00 },
942 { WSA884X_MISC, 0x00 },
943 { WSA884X_ADC_0, 0x00 },
944 { WSA884X_ADC_1, 0x00 },
945 { WSA884X_ADC_2, 0x40 },
946 { WSA884X_ADC_3, 0x80 },
947 { WSA884X_ADC_4, 0x25 },
948 { WSA884X_ADC_5, 0x24 },
949 { WSA884X_ADC_6, 0x0a },
950 { WSA884X_ADC_7, 0x81 },
951 { WSA884X_IVSENSE_SPARE_TUNE_1, 0x00 },
952 { WSA884X_SPARE_TUNE_2, 0x00 },
953 { WSA884X_SPARE_TUNE_3, 0x00 },
954 { WSA884X_SPARE_TUNE_4, 0x00 },
955 { WSA884X_TOP_CTRL1, 0xd3 },
956 { WSA884X_CLIP_DET_CTRL1, 0x7e },
957 { WSA884X_CLIP_DET_CTRL2, 0x4c },
958 { WSA884X_DAC_CTRL1, 0xa4 },
959 { WSA884X_DAC_VCM_CTRL_REG1, 0x02 },
960 { WSA884X_DAC_VCM_CTRL_REG2, 0x00 },
961 { WSA884X_DAC_VCM_CTRL_REG3, 0x00 },
962 { WSA884X_DAC_VCM_CTRL_REG4, 0x00 },
963 { WSA884X_DAC_VCM_CTRL_REG5, 0x00 },
964 { WSA884X_DAC_VCM_CTRL_REG6, 0x00 },
965 { WSA884X_PWM_CLK_CTL, 0x20 },
966 { WSA884X_DRV_LF_LDO_SEL, 0xaa },
967 { WSA884X_OCP_CTL, 0xc6 },
968 { WSA884X_PDRV_HS_CTL, 0x52 },
969 { WSA884X_PDRV_LS_CTL, 0x4a },
970 { WSA884X_SPK_TOP_SPARE_CTL_1, 0x00 },
971 { WSA884X_SPK_TOP_SPARE_CTL_2, 0x00 },
972 { WSA884X_SPK_TOP_SPARE_CTL_3, 0x00 },
973 { WSA884X_SPK_TOP_SPARE_CTL_4, 0x00 },
974 { WSA884X_SPARE_CTL_5, 0x00 },
975 { WSA884X_DAC_EN_DEBUG_REG, 0x00 },
976 { WSA884X_DAC_OPAMP_BIAS1_REG, 0x48 },
977 { WSA884X_DAC_OPAMP_BIAS2_REG, 0x48 },
978 { WSA884X_DAC_TUNE1, 0x02 },
979 { WSA884X_DAC_VOLTAGE_CTRL_REG, 0x05 },
980 { WSA884X_ATEST1_REG, 0x00 },
981 { WSA884X_ATEST2_REG, 0x00 },
982 { WSA884X_TOP_BIAS_REG1, 0x6a },
983 { WSA884X_TOP_BIAS_REG2, 0x65 },
984 { WSA884X_TOP_BIAS_REG3, 0x55 },
985 { WSA884X_TOP_BIAS_REG4, 0xa9 },
986 { WSA884X_PWRSTG_DBG2, 0x21 },
987 { WSA884X_DRV_LF_BLK_EN, 0x0f },
988 { WSA884X_DRV_LF_EN, 0x0a },
989 { WSA884X_DRV_LF_MASK_DCC_CTL, 0x08 },
990 { WSA884X_DRV_LF_MISC_CTL1, 0x30 },
991 { WSA884X_DRV_LF_REG_GAIN, 0x00 },
992 { WSA884X_DRV_OS_CAL_CTL, 0x00 },
993 { WSA884X_DRV_OS_CAL_CTL1, 0x90 },
994 { WSA884X_PWRSTG_DBG, 0x08 },
995 { WSA884X_BBM_CTL, 0x92 },
996 { WSA884X_TOP_MISC1, 0x00 },
997 { WSA884X_DAC_VCM_CTRL_REG7, 0x00 },
998 { WSA884X_TOP_BIAS_REG5, 0x15 },
999 { WSA884X_DRV_LF_MISC_CTL2, 0x00 },
1000 { WSA884X_STB_CTRL1, 0x42 },
1001 { WSA884X_CURRENT_LIMIT, 0x54 },
1002 { WSA884X_BYP_CTRL1, 0x01 },
1003 { WSA884X_SPARE_CTL_0, 0x00 },
1004 { WSA884X_BOOST_SPARE_CTL_1, 0x00 },
1005 { WSA884X_IBIAS1, 0x00 },
1006 { WSA884X_IBIAS2, 0x00 },
1007 { WSA884X_IBIAS3, 0x00 },
1008 { WSA884X_EN_CTRL, 0x42 },
1009 { WSA884X_STB_CTRL2, 0x03 },
1010 { WSA884X_STB_CTRL3, 0x3c },
1011 { WSA884X_STB_CTRL4, 0x30 },
1012 { WSA884X_BYP_CTRL2, 0x97 },
1013 { WSA884X_BYP_CTRL3, 0x11 },
1014 { WSA884X_ZX_CTRL1, 0xf0 },
1015 { WSA884X_ZX_CTRL2, 0x04 },
1016 { WSA884X_BLEEDER_CTRL, 0x04 },
1017 { WSA884X_BOOST_MISC, 0x62 },
1018 { WSA884X_PWRSTAGE_CTRL1, 0x00 },
1019 { WSA884X_PWRSTAGE_CTRL2, 0x31 },
1020 { WSA884X_PWRSTAGE_CTRL3, 0x81 },
1021 { WSA884X_PWRSTAGE_CTRL4, 0x5f },
1022 { WSA884X_MAXD_REG1, 0x00 },
1023 { WSA884X_MAXD_REG2, 0x5b },
1024 { WSA884X_ILIM_CTRL1, 0xe2 },
1025 { WSA884X_ILIM_CTRL2, 0x90 },
1026 { WSA884X_TEST_CTRL1, 0x00 },
1027 { WSA884X_TEST_CTRL2, 0x00 },
1028 { WSA884X_SPARE1, 0x00 },
1029 { WSA884X_BOOT_CAP_CHECK, 0x01 },
1030 { WSA884X_PON_CTL_0, 0x12 },
1031 { WSA884X_PWRSAV_CTL, 0xaa },
1032 { WSA884X_PON_LDOL_SPARE_CTL_0, 0x00 },
1033 { WSA884X_PON_LDOL_SPARE_CTL_1, 0x00 },
1034 { WSA884X_PON_LDOL_SPARE_CTL_2, 0x00 },
1035 { WSA884X_PON_LDOL_SPARE_CTL_3, 0x00 },
1036 { WSA884X_PON_CLT_1, 0xe1 },
1037 { WSA884X_PON_CTL_2, 0x00 },
1038 { WSA884X_PON_CTL_3, 0x70 },
1039 { WSA884X_CKWD_CTL_0, 0x14 },
1040 { WSA884X_CKWD_CTL_1, 0x3b },
1041 { WSA884X_CKWD_CTL_2, 0x00 },
1042 { WSA884X_CKSK_CTL_0, 0x00 },
1043 { WSA884X_PADSW_CTL_0, 0x00 },
1044 { WSA884X_TEST_0, 0x00 },
1045 { WSA884X_TEST_1, 0x00 },
1046 { WSA884X_PON_LDOL_SPARE_TUNE_0, 0x00 },
1047 { WSA884X_PON_LDOL_SPARE_TUNE_1, 0x00 },
1048 { WSA884X_PON_LDOL_SPARE_TUNE_2, 0x00 },
1049 { WSA884X_PON_LDOL_SPARE_TUNE_3, 0x00 },
1050 { WSA884X_PON_LDOL_SPARE_TUNE_4, 0x00 },
1051 { WSA884X_DIG_CTRL0_PAGE, 0x00 },
1052 { WSA884X_CDC_RST_CTL, 0x01 },
1053 { WSA884X_SWR_RESET_EN, 0x00 },
1054 { WSA884X_TOP_CLK_CFG, 0x00 },
1055 { WSA884X_SWR_CLK_RATE, 0x00 },
1056 { WSA884X_CDC_PATH_MODE, 0x00 },
1057 { WSA884X_CDC_CLK_CTL, 0x1f },
1058 { WSA884X_PA_FSM_EN, 0x00 },
1059 { WSA884X_PA_FSM_CTL0, 0x00 },
1060 { WSA884X_PA_FSM_CTL1, 0xfe },
1061 { WSA884X_PA_FSM_TIMER0, 0x80 },
1062 { WSA884X_PA_FSM_TIMER1, 0x80 },
1063 { WSA884X_PA_FSM_ERR_CTL, 0x00 },
1064 { WSA884X_PA_FSM_MSK0, 0x00 },
1065 { WSA884X_PA_FSM_MSK1, 0x00 },
1066 { WSA884X_PA_FSM_BYP_CTL, 0x00 },
1067 { WSA884X_PA_FSM_BYP0, 0x00 },
1068 { WSA884X_PA_FSM_BYP1, 0x00 },
1069 { WSA884X_TADC_VALUE_CTL, 0x03 },
1070 { WSA884X_TEMP_DETECT_CTL, 0x01 },
1071 { WSA884X_TEMP_CONFIG0, 0x00 },
1072 { WSA884X_TEMP_CONFIG1, 0x00 },
1073 { WSA884X_VBAT_THRM_FLT_CTL, 0x7f },
1074 { WSA884X_VBAT_CAL_CTL, 0x01 },
1075 { WSA884X_UVLO_DEGLITCH_CTL, 0x05 },
1076 { WSA884X_BOP_DEGLITCH_CTL, 0x05 },
1077 { WSA884X_VBAT_ZONE_DETC_CTL, 0x31 },
1078 { WSA884X_CPS_CTL, 0x00 },
1079 { WSA884X_CDC_RX_CTL, 0xfe },
1080 { WSA884X_CDC_SPK_DSM_A1_0, 0x00 },
1081 { WSA884X_CDC_SPK_DSM_A1_1, 0x01 },
1082 { WSA884X_CDC_SPK_DSM_A2_0, 0x96 },
1083 { WSA884X_CDC_SPK_DSM_A2_1, 0x09 },
1084 { WSA884X_CDC_SPK_DSM_A3_0, 0xab },
1085 { WSA884X_CDC_SPK_DSM_A3_1, 0x05 },
1086 { WSA884X_CDC_SPK_DSM_A4_0, 0x1c },
1087 { WSA884X_CDC_SPK_DSM_A4_1, 0x02 },
1088 { WSA884X_CDC_SPK_DSM_A5_0, 0x17 },
1089 { WSA884X_CDC_SPK_DSM_A5_1, 0x02 },
1090 { WSA884X_CDC_SPK_DSM_A6_0, 0xaa },
1091 { WSA884X_CDC_SPK_DSM_A7_0, 0xe3 },
1092 { WSA884X_CDC_SPK_DSM_C_0, 0x69 },
1093 { WSA884X_CDC_SPK_DSM_C_1, 0x54 },
1094 { WSA884X_CDC_SPK_DSM_C_2, 0x02 },
1095 { WSA884X_CDC_SPK_DSM_C_3, 0x15 },
1096 { WSA884X_CDC_SPK_DSM_R1, 0xa4 },
1097 { WSA884X_CDC_SPK_DSM_R2, 0xb5 },
1098 { WSA884X_CDC_SPK_DSM_R3, 0x86 },
1099 { WSA884X_CDC_SPK_DSM_R4, 0x85 },
1100 { WSA884X_CDC_SPK_DSM_R5, 0xaa },
1101 { WSA884X_CDC_SPK_DSM_R6, 0xe2 },
1102 { WSA884X_CDC_SPK_DSM_R7, 0x62 },
1103 { WSA884X_CDC_SPK_GAIN_PDM_0, 0x00 },
1104 { WSA884X_CDC_SPK_GAIN_PDM_1, 0xfc },
1105 { WSA884X_CDC_SPK_GAIN_PDM_2, 0x05 },
1106 { WSA884X_PDM_WD_CTL, 0x00 },
1107 { WSA884X_DEM_BYPASS_DATA0, 0x00 },
1108 { WSA884X_DEM_BYPASS_DATA1, 0x00 },
1109 { WSA884X_DEM_BYPASS_DATA2, 0x00 },
1110 { WSA884X_DEM_BYPASS_DATA3, 0x00 },
1111 { WSA884X_DRE_CTL_0, 0x70 },
1112 { WSA884X_DRE_CTL_1, 0x04 },
1113 { WSA884X_DRE_IDLE_DET_CTL, 0x2f },
1114 { WSA884X_GAIN_RAMPING_CTL, 0x50 },
1115 { WSA884X_GAIN_RAMPING_MIN, 0x12 },
1116 { WSA884X_TAGC_CTL, 0x15 },
1117 { WSA884X_TAGC_TIME, 0xbc },
1118 { WSA884X_TAGC_FORCE_VAL, 0x00 },
1119 { WSA884X_VAGC_CTL, 0x01 },
1120 { WSA884X_VAGC_TIME, 0x0f },
1121 { WSA884X_VAGC_ATTN_LVL_1, 0x03 },
1122 { WSA884X_VAGC_ATTN_LVL_2, 0x06 },
1123 { WSA884X_VAGC_ATTN_LVL_3, 0x09 },
1124 { WSA884X_CLSH_CTL_0, 0x37 },
1125 { WSA884X_CLSH_CTL_1, 0x81 },
1126 { WSA884X_CLSH_V_HD_PA, 0x0c },
1127 { WSA884X_CLSH_V_PA_MIN, 0x00 },
1128 { WSA884X_CLSH_OVRD_VAL, 0x00 },
1129 { WSA884X_CLSH_HARD_MAX, 0xff },
1130 { WSA884X_CLSH_SOFT_MAX, 0xf5 },
1131 { WSA884X_CLSH_SIG_DP, 0x00 },
1132 { WSA884X_PBR_DELAY_CTL, 0x07 },
1133 { WSA884X_CLSH_SRL_MAX_PBR, 0x02 },
1134 { WSA884X_CLSH_VTH1, 0x00 },
1135 { WSA884X_CLSH_VTH2, 0x00 },
1136 { WSA884X_CLSH_VTH3, 0x00 },
1137 { WSA884X_CLSH_VTH4, 0x00 },
1138 { WSA884X_CLSH_VTH5, 0x00 },
1139 { WSA884X_CLSH_VTH6, 0x00 },
1140 { WSA884X_CLSH_VTH7, 0x00 },
1141 { WSA884X_CLSH_VTH8, 0x00 },
1142 { WSA884X_CLSH_VTH9, 0x00 },
1143 { WSA884X_CLSH_VTH10, 0x00 },
1144 { WSA884X_CLSH_VTH11, 0x00 },
1145 { WSA884X_CLSH_VTH12, 0x00 },
1146 { WSA884X_CLSH_VTH13, 0x00 },
1147 { WSA884X_CLSH_VTH14, 0x00 },
1148 { WSA884X_CLSH_VTH15, 0x00 },
1149 { WSA884X_DIG_CTRL1_PAGE, 0x00 },
1150 { WSA884X_PIN_CTL, 0x04 },
1151 { WSA884X_PIN_CTL_OE, 0x00 },
1152 { WSA884X_PIN_WDATA_IOPAD, 0x00 },
1153 { WSA884X_I2C_SLAVE_CTL, 0x00 },
1154 { WSA884X_SPMI_PAD_CTL0, 0x2f },
1155 { WSA884X_SPMI_PAD_CTL1, 0x2f },
1156 { WSA884X_SPMI_PAD_CTL2, 0x2f },
1157 { WSA884X_MEM_CTL, 0x00 },
1158 { WSA884X_SWR_HM_TEST0, 0x08 },
1159 { WSA884X_OTP_CTRL0, 0x00 },
1160 { WSA884X_OTP_CTRL2, 0x00 },
1161 { WSA884X_OTP_PRG_TCSP0, 0x77 },
1162 { WSA884X_OTP_PRG_TCSP1, 0x00 },
1163 { WSA884X_OTP_PRG_TPPS, 0x47 },
1164 { WSA884X_OTP_PRG_TVPS, 0x3b },
1165 { WSA884X_OTP_PRG_TVPH, 0x47 },
1166 { WSA884X_OTP_PRG_TPPR0, 0x47 },
1167 { WSA884X_OTP_PRG_TPPR1, 0x00 },
1168 { WSA884X_OTP_PRG_TPPH, 0x47 },
1169 { WSA884X_OTP_PRG_END, 0x47 },
1170 { WSA884X_WAVG_PLAY, 0x00 },
1171 { WSA884X_WAVG_CTL, 0x06 },
1172 { WSA884X_WAVG_LRA_PER_0, 0xd1 },
1173 { WSA884X_WAVG_LRA_PER_1, 0x00 },
1174 { WSA884X_WAVG_DELTA_THETA_0, 0xe6 },
1175 { WSA884X_WAVG_DELTA_THETA_1, 0x04 },
1176 { WSA884X_WAVG_DIRECT_AMP_0, 0x50 },
1177 { WSA884X_WAVG_DIRECT_AMP_1, 0x00 },
1178 { WSA884X_WAVG_PTRN_AMP0_0, 0x50 },
1179 { WSA884X_WAVG_PTRN_AMP0_1, 0x00 },
1180 { WSA884X_WAVG_PTRN_AMP1_0, 0x50 },
1181 { WSA884X_WAVG_PTRN_AMP1_1, 0x00 },
1182 { WSA884X_WAVG_PTRN_AMP2_0, 0x50 },
1183 { WSA884X_WAVG_PTRN_AMP2_1, 0x00 },
1184 { WSA884X_WAVG_PTRN_AMP3_0, 0x50 },
1185 { WSA884X_WAVG_PTRN_AMP3_1, 0x00 },
1186 { WSA884X_WAVG_PTRN_AMP4_0, 0x50 },
1187 { WSA884X_WAVG_PTRN_AMP4_1, 0x00 },
1188 { WSA884X_WAVG_PTRN_AMP5_0, 0x50 },
1189 { WSA884X_WAVG_PTRN_AMP5_1, 0x00 },
1190 { WSA884X_WAVG_PTRN_AMP6_0, 0x50 },
1191 { WSA884X_WAVG_PTRN_AMP6_1, 0x00 },
1192 { WSA884X_WAVG_PTRN_AMP7_0, 0x50 },
1193 { WSA884X_WAVG_PTRN_AMP7_1, 0x00 },
1194 { WSA884X_WAVG_PER_0_1, 0x88 },
1195 { WSA884X_WAVG_PER_2_3, 0x88 },
1196 { WSA884X_WAVG_PER_4_5, 0x88 },
1197 { WSA884X_WAVG_PER_6_7, 0x88 },
1198 { WSA884X_INTR_MODE, 0x00 },
1199 { WSA884X_INTR_MASK0, 0x90 },
1200 { WSA884X_INTR_MASK1, 0x00 },
1201 { WSA884X_INTR_CLEAR0, 0x00 },
1202 { WSA884X_INTR_CLEAR1, 0x00 },
1203 { WSA884X_INTR_LEVEL0, 0x04 },
1204 { WSA884X_INTR_LEVEL1, 0x00 },
1205 { WSA884X_INTR_SET0, 0x00 },
1206 { WSA884X_INTR_SET1, 0x00 },
1207 { WSA884X_INTR_TEST0, 0x00 },
1208 { WSA884X_INTR_TEST1, 0x00 },
1209 { WSA884X_PDM_TEST_MODE, 0x00 },
1210 { WSA884X_PA_FSM_DBG, 0x00 },
1211 { WSA884X_DIG_DEBUG_MODE, 0x00 },
1212 { WSA884X_DIG_DEBUG_SEL, 0x00 },
1213 { WSA884X_DIG_DEBUG_EN, 0x00 },
1214 { WSA884X_TADC_DETECT_DBG_CTL, 0x00 },
1215 { WSA884X_TADC_DEBUG_MSB, 0x00 },
1216 { WSA884X_TADC_DEBUG_LSB, 0x00 },
1217 { WSA884X_SAMPLE_EDGE_SEL, 0x7f },
1218 { WSA884X_SWR_EDGE_SEL, 0x00 },
1219 { WSA884X_TEST_MODE_CTL, 0x05 },
1220 { WSA884X_IOPAD_CTL, 0x00 },
1221 { WSA884X_ANA_CSR_DBG_ADD, 0x00 },
1222 { WSA884X_ANA_CSR_DBG_CTL, 0x12 },
1223 { WSA884X_CLK_DBG_CTL, 0x00 },
1224 { WSA884X_SPARE_0, 0x00 },
1225 { WSA884X_SPARE_1, 0x00 },
1226 { WSA884X_SPARE_2, 0x00 },
1227 { WSA884X_SCODE, 0x00 },
1228 { WSA884X_DIG_TRIM_PAGE, 0x00 },
1229 { WSA884X_EMEM_0, 0x00 },
1230 { WSA884X_EMEM_1, 0x00 },
1231 { WSA884X_EMEM_2, 0x00 },
1232 { WSA884X_EMEM_3, 0x00 },
1233 { WSA884X_EMEM_4, 0x00 },
1234 { WSA884X_EMEM_5, 0x00 },
1235 { WSA884X_EMEM_6, 0x00 },
1236 { WSA884X_EMEM_7, 0x00 },
1237 { WSA884X_EMEM_8, 0x00 },
1238 { WSA884X_EMEM_9, 0x00 },
1239 { WSA884X_EMEM_10, 0x00 },
1240 { WSA884X_EMEM_11, 0x00 },
1241 { WSA884X_EMEM_12, 0x00 },
1242 { WSA884X_EMEM_13, 0x00 },
1243 { WSA884X_EMEM_14, 0x00 },
1244 { WSA884X_EMEM_15, 0x00 },
1245 { WSA884X_EMEM_16, 0x00 },
1246 { WSA884X_EMEM_17, 0x00 },
1247 { WSA884X_EMEM_18, 0x00 },
1248 { WSA884X_EMEM_19, 0x00 },
1249 { WSA884X_EMEM_20, 0x00 },
1250 { WSA884X_EMEM_21, 0x00 },
1251 { WSA884X_EMEM_22, 0x00 },
1252 { WSA884X_EMEM_23, 0x00 },
1253 { WSA884X_EMEM_24, 0x00 },
1254 { WSA884X_EMEM_25, 0x00 },
1255 { WSA884X_EMEM_26, 0x00 },
1256 { WSA884X_EMEM_27, 0x00 },
1257 { WSA884X_EMEM_28, 0x00 },
1258 { WSA884X_EMEM_29, 0x00 },
1259 { WSA884X_EMEM_30, 0x00 },
1260 { WSA884X_EMEM_31, 0x00 },
1261 { WSA884X_EMEM_32, 0x00 },
1262 { WSA884X_EMEM_33, 0x00 },
1263 { WSA884X_EMEM_34, 0x00 },
1264 { WSA884X_EMEM_35, 0x00 },
1265 { WSA884X_EMEM_36, 0x00 },
1266 { WSA884X_EMEM_37, 0x00 },
1267 { WSA884X_EMEM_38, 0x00 },
1268 { WSA884X_EMEM_39, 0x00 },
1269 { WSA884X_EMEM_40, 0x00 },
1270 { WSA884X_EMEM_41, 0x00 },
1271 { WSA884X_EMEM_42, 0x00 },
1272 { WSA884X_EMEM_43, 0x00 },
1273 { WSA884X_EMEM_44, 0x00 },
1274 { WSA884X_EMEM_45, 0x00 },
1275 { WSA884X_EMEM_46, 0x00 },
1276 { WSA884X_EMEM_47, 0x00 },
1277 { WSA884X_EMEM_48, 0x00 },
1278 { WSA884X_EMEM_49, 0x00 },
1279 { WSA884X_EMEM_50, 0x00 },
1280 { WSA884X_EMEM_51, 0x00 },
1281 { WSA884X_EMEM_52, 0x00 },
1282 { WSA884X_EMEM_53, 0x00 },
1283 { WSA884X_EMEM_54, 0x00 },
1284 { WSA884X_EMEM_55, 0x00 },
1285 { WSA884X_EMEM_56, 0x00 },
1286 { WSA884X_EMEM_57, 0x00 },
1287 { WSA884X_EMEM_58, 0x00 },
1288 { WSA884X_EMEM_59, 0x00 },
1289 { WSA884X_EMEM_60, 0x00 },
1290 { WSA884X_EMEM_61, 0x00 },
1291 { WSA884X_EMEM_62, 0x00 },
1292 { WSA884X_EMEM_63, 0x00 },
1293 };
1294
1295 static bool wsa884x_readonly_register(struct device *dev, unsigned int reg)
1296 {
1297 switch (reg) {
1298 case WSA884X_DOUT_MSB:
1299 case WSA884X_DOUT_LSB:
1300 case WSA884X_STATUS:
1301 case WSA884X_SPK_TOP_SPARE_TUNE_2:
1302 case WSA884X_SPK_TOP_SPARE_TUNE_3:
1303 case WSA884X_SPK_TOP_SPARE_TUNE_4:
1304 case WSA884X_SPARE_TUNE_5:
1305 case WSA884X_SPARE_TUNE_6:
1306 case WSA884X_SPARE_TUNE_7:
1307 case WSA884X_SPARE_TUNE_8:
1308 case WSA884X_SPARE_TUNE_9:
1309 case WSA884X_SPARE_TUNE_10:
1310 case WSA884X_PA_STATUS0:
1311 case WSA884X_PA_STATUS1:
1312 case WSA884X_PA_STATUS2:
1313 case WSA884X_PA_STATUS3:
1314 case WSA884X_PA_STATUS4:
1315 case WSA884X_PA_STATUS5:
1316 case WSA884X_SPARE_RO_1:
1317 case WSA884X_SPARE_RO_2:
1318 case WSA884X_SPARE_RO_3:
1319 case WSA884X_SPARE_RO_0:
1320 case WSA884X_BOOST_SPARE_RO_1:
1321 case WSA884X_STATUS_0:
1322 case WSA884X_STATUS_1:
1323 case WSA884X_CHIP_ID0:
1324 case WSA884X_CHIP_ID1:
1325 case WSA884X_CHIP_ID2:
1326 case WSA884X_CHIP_ID3:
1327 case WSA884X_BUS_ID:
1328 case WSA884X_PA_FSM_STA0:
1329 case WSA884X_PA_FSM_STA1:
1330 case WSA884X_PA_FSM_ERR_COND0:
1331 case WSA884X_PA_FSM_ERR_COND1:
1332 case WSA884X_TEMP_DIN_MSB:
1333 case WSA884X_TEMP_DIN_LSB:
1334 case WSA884X_TEMP_DOUT_MSB:
1335 case WSA884X_TEMP_DOUT_LSB:
1336 case WSA884X_VBAT_DIN_MSB:
1337 case WSA884X_VBAT_DIN_LSB:
1338 case WSA884X_VBAT_DOUT_MSB:
1339 case WSA884X_VBAT_DOUT_LSB:
1340 case WSA884X_VBAT_CAL_MSB:
1341 case WSA884X_VBAT_CAL_LSB:
1342 case WSA884X_VPHX_SYS_EN_STATUS:
1343 case WSA884X_PIN_STATUS:
1344 case WSA884X_SWR_HM_TEST1:
1345 case WSA884X_OTP_CTRL1:
1346 case WSA884X_OTP_STAT:
1347 case WSA884X_WAVG_STA:
1348 case WSA884X_INTR_STATUS0:
1349 case WSA884X_INTR_STATUS1:
1350 case WSA884X_ATE_TEST_MODE:
1351 case WSA884X_SPARE_R:
1352 return true;
1353 }
1354 return false;
1355 }
1356
1357 static bool wsa884x_writeable_register(struct device *dev, unsigned int reg)
1358 {
1359 return !wsa884x_readonly_register(dev, reg);
1360 }
1361
1362 static bool wsa884x_volatile_register(struct device *dev, unsigned int reg)
1363 {
1364 switch (reg) {
1365 case WSA884X_ANA_WO_CTL_0:
1366 case WSA884X_ANA_WO_CTL_1:
1367 return true;
1368 }
1369 return wsa884x_readonly_register(dev, reg);
1370 }
1371
1372 static const struct regmap_config wsa884x_regmap_config = {
1373 .reg_bits = 32,
1374 .val_bits = 8,
1375 .cache_type = REGCACHE_MAPLE,
1376 .reg_defaults = wsa884x_defaults,
1377 .max_register = WSA884X_MAX_REGISTER,
1378 .num_reg_defaults = ARRAY_SIZE(wsa884x_defaults),
1379 .volatile_reg = wsa884x_volatile_register,
1380 .writeable_reg = wsa884x_writeable_register,
1381 .reg_format_endian = REGMAP_ENDIAN_NATIVE,
1382 .val_format_endian = REGMAP_ENDIAN_NATIVE,
1383 .use_single_read = true,
1384 };
1385
1386 static const struct reg_sequence wsa884x_reg_init[] = {
1387 { WSA884X_BOP2_PROG, FIELD_PREP_CONST(WSA884X_BOP2_PROG_BOP2_VTH_MASK, 0x6) |
1388 FIELD_PREP_CONST(WSA884X_BOP2_PROG_BOP2_HYST_MASK, 0x6) },
1389 { WSA884X_REF_CTRL, (0xd2 & ~WSA884X_REF_CTRL_BG_RDY_SEL_MASK) |
1390 FIELD_PREP_CONST(WSA884X_REF_CTRL_BG_RDY_SEL_MASK, 0x1) },
1391 /*
1392 * Downstream suggests for batteries different than 1-Stacked (1S):
1393 * { WSA884X_TOP_CTRL1, 0xd3 & ~WSA884X_TOP_CTRL1_OCP_LOWVBAT_ITH_EN_MASK },
1394 */
1395 { WSA884X_STB_CTRL1, (0x42 & ~WSA884X_STB_CTRL1_SLOPE_COMP_CURRENT_MASK) |
1396 FIELD_PREP_CONST(WSA884X_STB_CTRL1_SLOPE_COMP_CURRENT_MASK, 0xd) },
1397 { WSA884X_CURRENT_LIMIT, (0x54 & ~WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_MASK) |
1398 FIELD_PREP_CONST(WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_MASK, 0x9) },
1399 { WSA884X_ZX_CTRL1, (0xf0 & ~WSA884X_ZX_CTRL1_ZX_DET_SW_SEL_MASK) |
1400 FIELD_PREP_CONST(WSA884X_ZX_CTRL1_ZX_DET_SW_SEL_MASK, 0x3) },
1401 { WSA884X_ILIM_CTRL1, (0xe2 & ~WSA884X_ILIM_CTRL1_ILIM_OFFSET_PB_MASK) |
1402 FIELD_PREP_CONST(WSA884X_ILIM_CTRL1_ILIM_OFFSET_PB_MASK, 0x3) },
1403 { WSA884X_CKWD_CTL_1, FIELD_PREP_CONST(WSA884X_CKWD_CTL_1_VPP_SW_CTL_MASK, 0x0) |
1404 FIELD_PREP_CONST(WSA884X_CKWD_CTL_1_CKWD_VCOMP_VREF_SEL_MASK, 0x13) },
1405 { WSA884X_PA_FSM_CTL1, (0xfe & ~WSA884X_PA_FSM_CTL1_NOISE_GATE_BLOCK_MASK) |
1406 FIELD_PREP_CONST(WSA884X_PA_FSM_CTL1_NOISE_GATE_BLOCK_MASK, 0x4) }, /* == 0xfe */
1407 { WSA884X_VBAT_THRM_FLT_CTL, (0x7f & ~WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_MASK) |
1408 FIELD_PREP_CONST(WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_MASK, 0x4) },
1409 { WSA884X_VBAT_CAL_CTL, FIELD_PREP_CONST(WSA884X_VBAT_CAL_CTL_RESERVE_MASK, 0x2) |
1410 FIELD_PREP_CONST(WSA884X_VBAT_CAL_CTL_VBAT_CAL_EN_MASK, 0x1) },
1411 { WSA884X_BOP_DEGLITCH_CTL, FIELD_PREP_CONST(WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_SETTING_MASK, 0x8) |
1412 FIELD_PREP_CONST(WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_EN_MASK, 0x1) },
1413 { WSA884X_CDC_SPK_DSM_A2_0, 0x0a },
1414 { WSA884X_CDC_SPK_DSM_A2_1, 0x08 },
1415 { WSA884X_CDC_SPK_DSM_A3_0, 0xf3 },
1416 { WSA884X_CDC_SPK_DSM_A3_1, 0x07 },
1417 { WSA884X_CDC_SPK_DSM_A4_0, 0x79 },
1418 { WSA884X_CDC_SPK_DSM_A5_0, 0x0b },
1419 { WSA884X_CDC_SPK_DSM_A6_0, 0x8a },
1420 { WSA884X_CDC_SPK_DSM_A7_0, 0x9b },
1421 { WSA884X_CDC_SPK_DSM_C_0, FIELD_PREP_CONST(WSA884X_CDC_SPK_DSM_C_0_COEF_C3_MASK, 0x6) |
1422 FIELD_PREP_CONST(WSA884X_CDC_SPK_DSM_C_0_COEF_C2_MASK, 0x8) },
1423 { WSA884X_CDC_SPK_DSM_C_2, FIELD_PREP_CONST(WSA884X_CDC_SPK_DSM_C_2_COEF_C7_MASK, 0xf) },
1424 { WSA884X_CDC_SPK_DSM_C_3, FIELD_PREP_CONST(WSA884X_CDC_SPK_DSM_C_3_COEF_C7_MASK, 0x20) },
1425 { WSA884X_CDC_SPK_DSM_R1, 0x83 },
1426 { WSA884X_CDC_SPK_DSM_R2, 0x7f },
1427 { WSA884X_CDC_SPK_DSM_R3, 0x9d },
1428 { WSA884X_CDC_SPK_DSM_R4, 0x82 },
1429 { WSA884X_CDC_SPK_DSM_R5, 0x8b },
1430 { WSA884X_CDC_SPK_DSM_R6, 0x9b },
1431 { WSA884X_CDC_SPK_DSM_R7, 0x3f },
1432 /* Speaker mode by default */
1433 { WSA884X_DRE_CTL_0, FIELD_PREP_CONST(WSA884X_DRE_CTL_0_PROG_DELAY_MASK, 0x7) },
1434 { WSA884X_CLSH_CTL_0, (0x37 & ~WSA884X_CLSH_CTL_0_DLY_CODE_MASK) |
1435 FIELD_PREP_CONST(WSA884X_CLSH_CTL_0_DLY_CODE_MASK, 0x6) },
1436 /*
1437 * WSA884X_CLSH_VTH values for speaker mode with G_21_DB system gain,
1438 * battery 1S and rload 8 Ohms.
1439 */
1440 { WSA884X_CLSH_VTH1, WSA884X_VTH_TO_REG(863), },
1441 { WSA884X_CLSH_VTH2, WSA884X_VTH_TO_REG(918), },
1442 { WSA884X_CLSH_VTH3, WSA884X_VTH_TO_REG(980), },
1443 { WSA884X_CLSH_VTH4, WSA884X_VTH_TO_REG(1043), },
1444 { WSA884X_CLSH_VTH5, WSA884X_VTH_TO_REG(1098), },
1445 { WSA884X_CLSH_VTH6, WSA884X_VTH_TO_REG(1137), },
1446 { WSA884X_CLSH_VTH7, WSA884X_VTH_TO_REG(1184), },
1447 { WSA884X_CLSH_VTH8, WSA884X_VTH_TO_REG(1239), },
1448 { WSA884X_CLSH_VTH9, WSA884X_VTH_TO_REG(1278), },
1449 { WSA884X_CLSH_VTH10, WSA884X_VTH_TO_REG(1380), },
1450 { WSA884X_CLSH_VTH11, WSA884X_VTH_TO_REG(1482), },
1451 { WSA884X_CLSH_VTH12, WSA884X_VTH_TO_REG(1584), },
1452 { WSA884X_CLSH_VTH13, WSA884X_VTH_TO_REG(1663), },
1453 { WSA884X_CLSH_VTH14, WSA884X_VTH_TO_REG(1780), },
1454 { WSA884X_CLSH_VTH15, WSA884X_VTH_TO_REG(2000), },
1455 { WSA884X_ANA_WO_CTL_1, 0x00 },
1456 { WSA884X_OTP_REG_38, 0x00 },
1457 { WSA884X_OTP_REG_40, FIELD_PREP_CONST(WSA884X_OTP_REG_40_ISENSE_RESCAL_MASK, 0x8) },
1458 };
1459
1460 static void wsa884x_set_gain_parameters(struct wsa884x_priv *wsa884x)
1461 {
1462 struct regmap *regmap = wsa884x->regmap;
1463 unsigned int min_gain, igain, vgain, comp_offset;
1464
1465 /*
1466 * Downstream sets gain parameters customized per boards per use-case.
1467 * Choose here some sane values matching knowon users, like QRD8550
1468 * board:.
1469 *
1470 * Values match here downstream:
1471 * For WSA884X_RECEIVER - G_7P5_DB system gain
1472 * For WSA884X_SPEAKER - G_21_DB system gain
1473 */
1474 if (wsa884x->dev_mode == WSA884X_RECEIVER) {
1475 comp_offset = COMP_OFFSET4;
1476 min_gain = G_M6_DB;
1477 igain = ISENSE_18_DB;
1478 vgain = VSENSE_M12_DB;
1479 } else {
1480 /* WSA884X_SPEAKER */
1481 comp_offset = COMP_OFFSET0;
1482 min_gain = G_0_DB;
1483 igain = ISENSE_12_DB;
1484 vgain = VSENSE_M24_DB;
1485 }
1486
1487 regmap_update_bits(regmap, WSA884X_ISENSE2,
1488 WSA884X_ISENSE2_ISENSE_GAIN_CTL_MASK,
1489 FIELD_PREP(WSA884X_ISENSE2_ISENSE_GAIN_CTL_MASK, igain));
1490 regmap_update_bits(regmap, WSA884X_VSENSE1,
1491 WSA884X_VSENSE1_GAIN_VSENSE_FE_MASK,
1492 FIELD_PREP(WSA884X_VSENSE1_GAIN_VSENSE_FE_MASK, vgain));
1493 regmap_update_bits(regmap, WSA884X_GAIN_RAMPING_MIN,
1494 WSA884X_GAIN_RAMPING_MIN_MIN_GAIN_MASK,
1495 FIELD_PREP(WSA884X_GAIN_RAMPING_MIN_MIN_GAIN_MASK, min_gain));
1496
1497 if (wsa884x->port_enable[WSA884X_PORT_COMP]) {
1498 regmap_update_bits(regmap, WSA884X_DRE_CTL_0,
1499 WSA884X_DRE_CTL_0_OFFSET_MASK,
1500 FIELD_PREP(WSA884X_DRE_CTL_0_OFFSET_MASK, comp_offset));
1501
1502 regmap_update_bits(regmap, WSA884X_DRE_CTL_1,
1503 WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK,
1504 FIELD_PREP(WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK, 0x0));
1505 } else {
1506 regmap_update_bits(regmap, WSA884X_DRE_CTL_1,
1507 WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK,
1508 FIELD_PREP(WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK, 0x1));
1509 }
1510 }
1511
1512 static void wsa884x_init(struct wsa884x_priv *wsa884x)
1513 {
1514 unsigned int wo_ctl_0;
1515 unsigned int variant = 0;
1516
1517 if (!regmap_read(wsa884x->regmap, WSA884X_OTP_REG_0, &variant))
1518 variant = variant & WSA884X_OTP_REG_0_ID_MASK;
1519
1520 regmap_multi_reg_write(wsa884x->regmap, wsa884x_reg_init,
1521 ARRAY_SIZE(wsa884x_reg_init));
1522
1523 wo_ctl_0 = 0xc;
1524 wo_ctl_0 |= FIELD_PREP(WSA884X_ANA_WO_CTL_0_DAC_CM_CLAMP_EN_MASK,
1525 WSA884X_ANA_WO_CTL_0_DAC_CM_CLAMP_EN_MODE_SPEAKER);
1526 /* Assume that compander is enabled by default unless it is haptics sku */
1527 if (variant == WSA884X_OTP_ID_WSA8845H)
1528 wo_ctl_0 |= FIELD_PREP(WSA884X_ANA_WO_CTL_0_PA_AUX_GAIN_MASK,
1529 WSA884X_ANA_WO_CTL_0_PA_AUX_18_DB);
1530 else
1531 wo_ctl_0 |= FIELD_PREP(WSA884X_ANA_WO_CTL_0_PA_AUX_GAIN_MASK,
1532 WSA884X_ANA_WO_CTL_0_PA_AUX_0_DB);
1533 regmap_write(wsa884x->regmap, WSA884X_ANA_WO_CTL_0, wo_ctl_0);
1534
1535 wsa884x_set_gain_parameters(wsa884x);
1536
1537 wsa884x->hw_init = false;
1538 }
1539
1540 static int wsa884x_update_status(struct sdw_slave *slave,
1541 enum sdw_slave_status status)
1542 {
1543 struct wsa884x_priv *wsa884x = dev_get_drvdata(&slave->dev);
1544 int ret;
1545
1546 if (status == SDW_SLAVE_UNATTACHED) {
1547 wsa884x->hw_init = false;
1548 regcache_cache_only(wsa884x->regmap, true);
1549 regcache_mark_dirty(wsa884x->regmap);
1550 return 0;
1551 }
1552
1553 if (wsa884x->hw_init || status != SDW_SLAVE_ATTACHED)
1554 return 0;
1555
1556 regcache_cache_only(wsa884x->regmap, false);
1557 ret = regcache_sync(wsa884x->regmap);
1558 if (ret < 0) {
1559 dev_err(&slave->dev, "Cannot sync regmap cache\n");
1560 return ret;
1561 }
1562
1563 wsa884x_init(wsa884x);
1564
1565 return 0;
1566 }
1567
1568 static int wsa884x_port_prep(struct sdw_slave *slave,
1569 struct sdw_prepare_ch *prepare_ch,
1570 enum sdw_port_prep_ops state)
1571 {
1572 struct wsa884x_priv *wsa884x = dev_get_drvdata(&slave->dev);
1573
1574 if (state == SDW_OPS_PORT_POST_PREP)
1575 wsa884x->port_prepared[prepare_ch->num - 1] = true;
1576 else
1577 wsa884x->port_prepared[prepare_ch->num - 1] = false;
1578
1579 return 0;
1580 }
1581
1582 static const struct sdw_slave_ops wsa884x_slave_ops = {
1583 .update_status = wsa884x_update_status,
1584 .port_prep = wsa884x_port_prep,
1585 };
1586
1587 static int wsa884x_dev_mode_get(struct snd_kcontrol *kcontrol,
1588 struct snd_ctl_elem_value *ucontrol)
1589 {
1590 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1591 struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
1592
1593 ucontrol->value.enumerated.item[0] = wsa884x->dev_mode;
1594
1595 return 0;
1596 }
1597
1598 static int wsa884x_dev_mode_put(struct snd_kcontrol *kcontrol,
1599 struct snd_ctl_elem_value *ucontrol)
1600 {
1601 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1602 struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
1603
1604 if (wsa884x->dev_mode == ucontrol->value.enumerated.item[0])
1605 return 0;
1606
1607 wsa884x->dev_mode = ucontrol->value.enumerated.item[0];
1608
1609 return 1;
1610 }
1611
1612 static int wsa884x_get_swr_port(struct snd_kcontrol *kcontrol,
1613 struct snd_ctl_elem_value *ucontrol)
1614 {
1615 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
1616 struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(comp);
1617 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1618 int portidx = mixer->reg;
1619
1620 ucontrol->value.integer.value[0] = wsa884x->port_enable[portidx];
1621
1622 return 0;
1623 }
1624
1625 static int wsa884x_set_swr_port(struct snd_kcontrol *kcontrol,
1626 struct snd_ctl_elem_value *ucontrol)
1627 {
1628 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
1629 struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(comp);
1630 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1631 int portidx = mixer->reg;
1632
1633 if (ucontrol->value.integer.value[0]) {
1634 if (wsa884x->port_enable[portidx])
1635 return 0;
1636
1637 wsa884x->port_enable[portidx] = true;
1638 } else {
1639 if (!wsa884x->port_enable[portidx])
1640 return 0;
1641
1642 wsa884x->port_enable[portidx] = false;
1643 }
1644
1645 return 1;
1646 }
1647
1648 static int wsa884x_codec_probe(struct snd_soc_component *comp)
1649 {
1650 struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(comp);
1651
1652 snd_soc_component_init_regmap(comp, wsa884x->regmap);
1653
1654 return 0;
1655 }
1656
1657 static void wsa884x_spkr_post_pmu(struct snd_soc_component *component,
1658 struct wsa884x_priv *wsa884x)
1659 {
1660 unsigned int curr_limit, curr_ovrd_en;
1661
1662 wsa884x_set_gain_parameters(wsa884x);
1663 if (wsa884x->dev_mode == WSA884X_RECEIVER) {
1664 snd_soc_component_write_field(component, WSA884X_DRE_CTL_0,
1665 WSA884X_DRE_CTL_0_PROG_DELAY_MASK, 0x3);
1666 snd_soc_component_write_field(component, WSA884X_CDC_PATH_MODE,
1667 WSA884X_CDC_PATH_MODE_RXD_MODE_MASK,
1668 0x1);
1669 snd_soc_component_write_field(component, WSA884X_PWM_CLK_CTL,
1670 WSA884X_PWM_CLK_CTL_PWM_CLK_FREQ_SEL_MASK,
1671 0x1);
1672 } else {
1673 /* WSA884X_SPEAKER */
1674 snd_soc_component_write_field(component, WSA884X_DRE_CTL_0,
1675 WSA884X_DRE_CTL_0_PROG_DELAY_MASK, 0xf);
1676 }
1677
1678 if (wsa884x->port_enable[WSA884X_PORT_PBR]) {
1679 curr_ovrd_en = 0x0;
1680 curr_limit = 0x15;
1681 } else {
1682 curr_ovrd_en = 0x1;
1683 if (wsa884x->dev_mode == WSA884X_RECEIVER)
1684 curr_limit = 0x9;
1685 else
1686 curr_limit = 0x15;
1687 }
1688 snd_soc_component_write_field(component, WSA884X_CURRENT_LIMIT,
1689 WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_OVRD_EN_MASK,
1690 curr_ovrd_en);
1691 snd_soc_component_write_field(component, WSA884X_CURRENT_LIMIT,
1692 WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_MASK,
1693 curr_limit);
1694 }
1695
1696 static int wsa884x_spkr_event(struct snd_soc_dapm_widget *w,
1697 struct snd_kcontrol *kcontrol, int event)
1698 {
1699 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1700 struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
1701
1702 switch (event) {
1703 case SND_SOC_DAPM_POST_PMU:
1704 mutex_lock(&wsa884x->sp_lock);
1705 wsa884x->pa_on = true;
1706 mutex_unlock(&wsa884x->sp_lock);
1707
1708 wsa884x_spkr_post_pmu(component, wsa884x);
1709
1710 snd_soc_component_write_field(component, WSA884X_PDM_WD_CTL,
1711 WSA884X_PDM_WD_CTL_PDM_WD_EN_MASK,
1712 0x1);
1713
1714 break;
1715 case SND_SOC_DAPM_PRE_PMD:
1716 snd_soc_component_write_field(component, WSA884X_PDM_WD_CTL,
1717 WSA884X_PDM_WD_CTL_PDM_WD_EN_MASK,
1718 0x0);
1719
1720 mutex_lock(&wsa884x->sp_lock);
1721 wsa884x->pa_on = false;
1722 mutex_unlock(&wsa884x->sp_lock);
1723 break;
1724 }
1725
1726 return 0;
1727 }
1728
1729 static const struct snd_soc_dapm_widget wsa884x_dapm_widgets[] = {
1730 SND_SOC_DAPM_INPUT("IN"),
1731 SND_SOC_DAPM_SPK("SPKR", wsa884x_spkr_event),
1732 };
1733
1734 static const DECLARE_TLV_DB_SCALE(pa_gain, -900, 150, -900);
1735
1736 static const struct snd_kcontrol_new wsa884x_snd_controls[] = {
1737 SOC_SINGLE_RANGE_TLV("PA Volume", WSA884X_DRE_CTL_1,
1738 WSA884X_DRE_CTL_1_CSR_GAIN_SHIFT,
1739 0x0, 0x1f, 1, pa_gain),
1740 SOC_ENUM_EXT("WSA MODE", wsa884x_dev_mode_enum,
1741 wsa884x_dev_mode_get, wsa884x_dev_mode_put),
1742 SOC_SINGLE_EXT("DAC Switch", WSA884X_PORT_DAC, 0, 1, 0,
1743 wsa884x_get_swr_port, wsa884x_set_swr_port),
1744 SOC_SINGLE_EXT("COMP Switch", WSA884X_PORT_COMP, 0, 1, 0,
1745 wsa884x_get_swr_port, wsa884x_set_swr_port),
1746 SOC_SINGLE_EXT("BOOST Switch", WSA884X_PORT_BOOST, 0, 1, 0,
1747 wsa884x_get_swr_port, wsa884x_set_swr_port),
1748 SOC_SINGLE_EXT("PBR Switch", WSA884X_PORT_PBR, 0, 1, 0,
1749 wsa884x_get_swr_port, wsa884x_set_swr_port),
1750 SOC_SINGLE_EXT("VISENSE Switch", WSA884X_PORT_VISENSE, 0, 1, 0,
1751 wsa884x_get_swr_port, wsa884x_set_swr_port),
1752 SOC_SINGLE_EXT("CPS Switch", WSA884X_PORT_CPS, 0, 1, 0,
1753 wsa884x_get_swr_port, wsa884x_set_swr_port),
1754 };
1755
1756 static const struct snd_soc_dapm_route wsa884x_audio_map[] = {
1757 {"SPKR", NULL, "IN"},
1758 };
1759
1760 static const struct snd_soc_component_driver wsa884x_component_drv = {
1761 .name = "WSA884x",
1762 .probe = wsa884x_codec_probe,
1763 .controls = wsa884x_snd_controls,
1764 .num_controls = ARRAY_SIZE(wsa884x_snd_controls),
1765 .dapm_widgets = wsa884x_dapm_widgets,
1766 .num_dapm_widgets = ARRAY_SIZE(wsa884x_dapm_widgets),
1767 .dapm_routes = wsa884x_audio_map,
1768 .num_dapm_routes = ARRAY_SIZE(wsa884x_audio_map),
1769 };
1770
1771 static int wsa884x_hw_params(struct snd_pcm_substream *substream,
1772 struct snd_pcm_hw_params *params,
1773 struct snd_soc_dai *dai)
1774 {
1775 struct wsa884x_priv *wsa884x = dev_get_drvdata(dai->dev);
1776 int i;
1777
1778 wsa884x->active_ports = 0;
1779 for (i = 0; i < WSA884X_MAX_SWR_PORTS; i++) {
1780 if (!wsa884x->port_enable[i])
1781 continue;
1782
1783 wsa884x->port_config[wsa884x->active_ports] = wsa884x_pconfig[i];
1784 wsa884x->active_ports++;
1785 }
1786
1787 wsa884x->sconfig.frame_rate = params_rate(params);
1788
1789 return sdw_stream_add_slave(wsa884x->slave, &wsa884x->sconfig,
1790 wsa884x->port_config, wsa884x->active_ports,
1791 wsa884x->sruntime);
1792 }
1793
1794 static int wsa884x_hw_free(struct snd_pcm_substream *substream,
1795 struct snd_soc_dai *dai)
1796 {
1797 struct wsa884x_priv *wsa884x = dev_get_drvdata(dai->dev);
1798
1799 sdw_stream_remove_slave(wsa884x->slave, wsa884x->sruntime);
1800
1801 return 0;
1802 }
1803
1804 static int wsa884x_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
1805 {
1806 struct snd_soc_component *component = dai->component;
1807
1808 if (mute) {
1809 snd_soc_component_write_field(component, WSA884X_DRE_CTL_1,
1810 WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK,
1811 0x0);
1812 snd_soc_component_write_field(component, WSA884X_PA_FSM_EN,
1813 WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK,
1814 0x0);
1815
1816 } else {
1817 snd_soc_component_write_field(component, WSA884X_DRE_CTL_1,
1818 WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK,
1819 0x1);
1820 snd_soc_component_write_field(component, WSA884X_PA_FSM_EN,
1821 WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK,
1822 0x1);
1823 }
1824
1825 return 0;
1826 }
1827
1828 static int wsa884x_set_stream(struct snd_soc_dai *dai,
1829 void *stream, int direction)
1830 {
1831 struct wsa884x_priv *wsa884x = dev_get_drvdata(dai->dev);
1832
1833 wsa884x->sruntime = stream;
1834
1835 return 0;
1836 }
1837
1838 static const struct snd_soc_dai_ops wsa884x_dai_ops = {
1839 .hw_params = wsa884x_hw_params,
1840 .hw_free = wsa884x_hw_free,
1841 .mute_stream = wsa884x_mute_stream,
1842 .set_stream = wsa884x_set_stream,
1843 .mute_unmute_on_trigger = true,
1844 };
1845
1846 static struct snd_soc_dai_driver wsa884x_dais[] = {
1847 {
1848 .name = "SPKR",
1849 .playback = {
1850 .stream_name = "SPKR Playback",
1851 .rates = WSA884X_RATES | WSA884X_FRAC_RATES,
1852 .formats = WSA884X_FORMATS,
1853 .rate_min = 8000,
1854 .rate_max = 384000,
1855 .channels_min = 1,
1856 .channels_max = 1,
1857 },
1858 .ops = &wsa884x_dai_ops,
1859 },
1860 };
1861
1862 static int wsa884x_get_temp(struct wsa884x_priv *wsa884x, long *temp)
1863 {
1864 unsigned int d1_msb = 0, d1_lsb = 0, d2_msb = 0, d2_lsb = 0;
1865 unsigned int dmeas_msb = 0, dmeas_lsb = 0;
1866 int d1, d2, dmeas;
1867 unsigned int mask;
1868 long val;
1869 int ret;
1870
1871 guard(mutex)(&wsa884x->sp_lock);
1872
1873 if (wsa884x->pa_on) {
1874 /*
1875 * Reading temperature is possible only when Power Amplifier is
1876 * off. Report last cached data.
1877 */
1878 *temp = wsa884x->temperature;
1879 return 0;
1880 }
1881
1882 ret = pm_runtime_resume_and_get(wsa884x->dev);
1883 if (ret < 0)
1884 return ret;
1885
1886 mask = WSA884X_PA_FSM_BYP0_DC_CAL_EN_MASK |
1887 WSA884X_PA_FSM_BYP0_CLK_WD_EN_MASK |
1888 WSA884X_PA_FSM_BYP0_BG_EN_MASK |
1889 WSA884X_PA_FSM_BYP0_D_UNMUTE_MASK |
1890 WSA884X_PA_FSM_BYP0_SPKR_PROT_EN_MASK |
1891 WSA884X_PA_FSM_BYP0_TSADC_EN_MASK;
1892 /*
1893 * Here and further do not care about read or update failures.
1894 * For example, before turning on Power Amplifier for the first
1895 * time, reading WSA884X_TEMP_DIN_MSB will always return 0.
1896 * Instead, check if returned value is within reasonable
1897 * thresholds.
1898 */
1899 regmap_update_bits(wsa884x->regmap, WSA884X_PA_FSM_BYP0, mask, mask);
1900
1901 regmap_update_bits(wsa884x->regmap, WSA884X_TADC_VALUE_CTL,
1902 WSA884X_TADC_VALUE_CTL_TEMP_VALUE_RD_EN_MASK,
1903 FIELD_PREP(WSA884X_TADC_VALUE_CTL_TEMP_VALUE_RD_EN_MASK, 0x0));
1904
1905 regmap_read(wsa884x->regmap, WSA884X_TEMP_DIN_MSB, &dmeas_msb);
1906 regmap_read(wsa884x->regmap, WSA884X_TEMP_DIN_LSB, &dmeas_lsb);
1907
1908 regmap_update_bits(wsa884x->regmap, WSA884X_TADC_VALUE_CTL,
1909 WSA884X_TADC_VALUE_CTL_TEMP_VALUE_RD_EN_MASK,
1910 FIELD_PREP(WSA884X_TADC_VALUE_CTL_TEMP_VALUE_RD_EN_MASK, 0x1));
1911
1912 regmap_read(wsa884x->regmap, WSA884X_OTP_REG_1, &d1_msb);
1913 regmap_read(wsa884x->regmap, WSA884X_OTP_REG_2, &d1_lsb);
1914 regmap_read(wsa884x->regmap, WSA884X_OTP_REG_3, &d2_msb);
1915 regmap_read(wsa884x->regmap, WSA884X_OTP_REG_4, &d2_lsb);
1916
1917 regmap_update_bits(wsa884x->regmap, WSA884X_PA_FSM_BYP0, mask, 0x0);
1918
1919 dmeas = (((dmeas_msb & 0xff) << 0x8) | (dmeas_lsb & 0xff)) >> 0x6;
1920 d1 = (((d1_msb & 0xff) << 0x8) | (d1_lsb & 0xff)) >> 0x6;
1921 d2 = (((d2_msb & 0xff) << 0x8) | (d2_lsb & 0xff)) >> 0x6;
1922
1923 if (d1 == d2) {
1924 /* Incorrect data in OTP? */
1925 ret = -EINVAL;
1926 goto out;
1927 }
1928
1929 val = WSA884X_T1_TEMP + (((dmeas - d1) * (WSA884X_T2_TEMP - WSA884X_T1_TEMP))/(d2 - d1));
1930
1931 dev_dbg(wsa884x->dev, "Measured temp %ld (dmeas=%d, d1=%d, d2=%d)\n",
1932 val, dmeas, d1, d2);
1933
1934 if ((val > WSA884X_LOW_TEMP_THRESHOLD) &&
1935 (val < WSA884X_HIGH_TEMP_THRESHOLD)) {
1936 wsa884x->temperature = val;
1937 *temp = val;
1938 ret = 0;
1939 } else {
1940 ret = -EAGAIN;
1941 }
1942
1943 out:
1944 pm_runtime_mark_last_busy(wsa884x->dev);
1945 pm_runtime_put_autosuspend(wsa884x->dev);
1946
1947 return ret;
1948 }
1949
1950 static umode_t wsa884x_hwmon_is_visible(const void *data,
1951 enum hwmon_sensor_types type, u32 attr,
1952 int channel)
1953 {
1954 if (type != hwmon_temp)
1955 return 0;
1956
1957 switch (attr) {
1958 case hwmon_temp_input:
1959 return 0444;
1960 default:
1961 break;
1962 }
1963
1964 return 0;
1965 }
1966
1967 static int wsa884x_hwmon_read(struct device *dev,
1968 enum hwmon_sensor_types type,
1969 u32 attr, int channel, long *temp)
1970 {
1971 int ret;
1972
1973 switch (attr) {
1974 case hwmon_temp_input:
1975 ret = wsa884x_get_temp(dev_get_drvdata(dev), temp);
1976 break;
1977 default:
1978 ret = -EOPNOTSUPP;
1979 break;
1980 }
1981
1982 return ret;
1983 }
1984
1985 static const struct hwmon_channel_info *const wsa884x_hwmon_info[] = {
1986 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT),
1987 NULL
1988 };
1989
1990 static const struct hwmon_ops wsa884x_hwmon_ops = {
1991 .is_visible = wsa884x_hwmon_is_visible,
1992 .read = wsa884x_hwmon_read,
1993 };
1994
1995 static const struct hwmon_chip_info wsa884x_hwmon_chip_info = {
1996 .ops = &wsa884x_hwmon_ops,
1997 .info = wsa884x_hwmon_info,
1998 };
1999
2000 static void wsa884x_reset_powerdown(void *data)
2001 {
2002 struct wsa884x_priv *wsa884x = data;
2003
2004 if (wsa884x->sd_reset)
2005 reset_control_assert(wsa884x->sd_reset);
2006 else
2007 gpiod_direction_output(wsa884x->sd_n, 1);
2008 }
2009
2010 static void wsa884x_reset_deassert(struct wsa884x_priv *wsa884x)
2011 {
2012 if (wsa884x->sd_reset)
2013 reset_control_deassert(wsa884x->sd_reset);
2014 else
2015 gpiod_direction_output(wsa884x->sd_n, 0);
2016 }
2017
2018 static void wsa884x_regulator_disable(void *data)
2019 {
2020 regulator_bulk_disable(WSA884X_SUPPLIES_NUM, data);
2021 }
2022
2023 static int wsa884x_get_reset(struct device *dev, struct wsa884x_priv *wsa884x)
2024 {
2025 wsa884x->sd_reset = devm_reset_control_get_optional_shared(dev, NULL);
2026 if (IS_ERR(wsa884x->sd_reset))
2027 return dev_err_probe(dev, PTR_ERR(wsa884x->sd_reset),
2028 "Failed to get reset\n");
2029 else if (wsa884x->sd_reset)
2030 return 0;
2031 /*
2032 * else: NULL, so use the backwards compatible way for powerdown-gpios,
2033 * which does not handle sharing GPIO properly.
2034 */
2035 wsa884x->sd_n = devm_gpiod_get_optional(dev, "powerdown",
2036 GPIOD_OUT_HIGH);
2037 if (IS_ERR(wsa884x->sd_n))
2038 return dev_err_probe(dev, PTR_ERR(wsa884x->sd_n),
2039 "Shutdown Control GPIO not found\n");
2040
2041 return 0;
2042 }
2043
2044 static int wsa884x_probe(struct sdw_slave *pdev,
2045 const struct sdw_device_id *id)
2046 {
2047 struct device *dev = &pdev->dev;
2048 struct wsa884x_priv *wsa884x;
2049 unsigned int i;
2050 int ret;
2051
2052 wsa884x = devm_kzalloc(dev, sizeof(*wsa884x), GFP_KERNEL);
2053 if (!wsa884x)
2054 return -ENOMEM;
2055
2056 mutex_init(&wsa884x->sp_lock);
2057
2058 for (i = 0; i < WSA884X_SUPPLIES_NUM; i++)
2059 wsa884x->supplies[i].supply = wsa884x_supply_name[i];
2060
2061 ret = devm_regulator_bulk_get(dev, WSA884X_SUPPLIES_NUM,
2062 wsa884x->supplies);
2063 if (ret)
2064 return dev_err_probe(dev, ret, "Failed to get regulators\n");
2065
2066 ret = regulator_bulk_enable(WSA884X_SUPPLIES_NUM, wsa884x->supplies);
2067 if (ret)
2068 return dev_err_probe(dev, ret, "Failed to enable regulators\n");
2069
2070 ret = devm_add_action_or_reset(dev, wsa884x_regulator_disable,
2071 wsa884x->supplies);
2072 if (ret)
2073 return ret;
2074
2075 ret = wsa884x_get_reset(dev, wsa884x);
2076 if (ret)
2077 return ret;
2078
2079 dev_set_drvdata(dev, wsa884x);
2080 wsa884x->slave = pdev;
2081 wsa884x->dev = dev;
2082 wsa884x->dev_mode = WSA884X_SPEAKER;
2083 wsa884x->sconfig.ch_count = 1;
2084 wsa884x->sconfig.bps = 1;
2085 wsa884x->sconfig.direction = SDW_DATA_DIR_RX;
2086 wsa884x->sconfig.type = SDW_STREAM_PDM;
2087
2088 /**
2089 * Port map index starts with 0, however the data port for this codec
2090 * are from index 1
2091 */
2092 if (of_property_read_u32_array(dev->of_node, "qcom,port-mapping", &pdev->m_port_map[1],
2093 WSA884X_MAX_SWR_PORTS))
2094 dev_dbg(dev, "Static Port mapping not specified\n");
2095
2096 pdev->prop.sink_ports = GENMASK(WSA884X_MAX_SWR_PORTS - 1, 0);
2097 pdev->prop.simple_clk_stop_capable = true;
2098 pdev->prop.sink_dpn_prop = wsa884x_sink_dpn_prop;
2099 pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
2100
2101 wsa884x_reset_deassert(wsa884x);
2102 ret = devm_add_action_or_reset(dev, wsa884x_reset_powerdown, wsa884x);
2103 if (ret)
2104 return ret;
2105
2106 wsa884x->regmap = devm_regmap_init_sdw(pdev, &wsa884x_regmap_config);
2107 if (IS_ERR(wsa884x->regmap))
2108 return dev_err_probe(dev, PTR_ERR(wsa884x->regmap),
2109 "regmap_init failed\n");
2110
2111 /* Start in cache-only until device is enumerated */
2112 regcache_cache_only(wsa884x->regmap, true);
2113 wsa884x->hw_init = true;
2114
2115 if (IS_REACHABLE(CONFIG_HWMON)) {
2116 struct device *hwmon;
2117
2118 hwmon = devm_hwmon_device_register_with_info(dev, "wsa884x",
2119 wsa884x,
2120 &wsa884x_hwmon_chip_info,
2121 NULL);
2122 if (IS_ERR(hwmon))
2123 return dev_err_probe(dev, PTR_ERR(hwmon),
2124 "Failed to register hwmon sensor\n");
2125 }
2126
2127 pm_runtime_set_autosuspend_delay(dev, 3000);
2128 pm_runtime_use_autosuspend(dev);
2129 pm_runtime_mark_last_busy(dev);
2130 pm_runtime_set_active(dev);
2131 pm_runtime_enable(dev);
2132
2133 return devm_snd_soc_register_component(dev,
2134 &wsa884x_component_drv,
2135 wsa884x_dais,
2136 ARRAY_SIZE(wsa884x_dais));
2137 }
2138
2139 static int __maybe_unused wsa884x_runtime_suspend(struct device *dev)
2140 {
2141 struct regmap *regmap = dev_get_regmap(dev, NULL);
2142
2143 regcache_cache_only(regmap, true);
2144 regcache_mark_dirty(regmap);
2145
2146 return 0;
2147 }
2148
2149 static int __maybe_unused wsa884x_runtime_resume(struct device *dev)
2150 {
2151 struct regmap *regmap = dev_get_regmap(dev, NULL);
2152
2153 regcache_cache_only(regmap, false);
2154 regcache_sync(regmap);
2155
2156 return 0;
2157 }
2158
2159 static const struct dev_pm_ops wsa884x_pm_ops = {
2160 SET_RUNTIME_PM_OPS(wsa884x_runtime_suspend, wsa884x_runtime_resume, NULL)
2161 };
2162
2163 static const struct sdw_device_id wsa884x_swr_id[] = {
2164 SDW_SLAVE_ENTRY(0x0217, 0x204, 0),
2165 {},
2166 };
2167 MODULE_DEVICE_TABLE(sdw, wsa884x_swr_id);
2168
2169 static struct sdw_driver wsa884x_codec_driver = {
2170 .driver = {
2171 .name = "wsa884x-codec",
2172 .pm = &wsa884x_pm_ops,
2173 },
2174 .probe = wsa884x_probe,
2175 .ops = &wsa884x_slave_ops,
2176 .id_table = wsa884x_swr_id,
2177 };
2178 module_sdw_driver(wsa884x_codec_driver);
2179
2180 MODULE_AUTHOR("Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>");
2181 MODULE_DESCRIPTION("WSA884x codec driver");
2182 MODULE_LICENSE("GPL");
Kernel DRM miscellaneous fixes and cross-tree changes