drm/ast: Only warn about unsupported TX chips on Gen4 and later
[drm/drm-misc.git] / tools / memory-model / litmus-tests / ISA2+pooncelock+pooncelock+pombonce.litmus
blob094d58df778969c836e97b945e92d3329e1c509f
1 C ISA2+pooncelock+pooncelock+pombonce
3 (*
4  * Result: Never
5  *
6  * This test shows that write-write ordering provided by locks
7  * (in P0() and P1()) is visible to external process P2().
8  *)
12 P0(int *x, int *y, spinlock_t *mylock)
14         spin_lock(mylock);
15         WRITE_ONCE(*x, 1);
16         WRITE_ONCE(*y, 1);
17         spin_unlock(mylock);
20 P1(int *y, int *z, spinlock_t *mylock)
22         int r0;
24         spin_lock(mylock);
25         r0 = READ_ONCE(*y);
26         WRITE_ONCE(*z, 1);
27         spin_unlock(mylock);
30 P2(int *x, int *z)
32         int r1;
33         int r2;
35         r2 = READ_ONCE(*z);
36         smp_mb();
37         r1 = READ_ONCE(*x);
40 exists (1:r0=1 /\ 2:r2=1 /\ 2:r1=0)