tools/perf/util/perf-regs-arch/perf_regs_riscv.c

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 #include "../perf_regs.h"
   4 #include "../../../arch/riscv/include/uapi/asm/perf_regs.h"
   5
   6 const char *__perf_reg_name_riscv(int id)
   7 {
   8         switch (id) {
   9         case PERF_REG_RISCV_PC:
  10                 return "pc";
  11         case PERF_REG_RISCV_RA:
  12                 return "ra";
  13         case PERF_REG_RISCV_SP:
  14                 return "sp";
  15         case PERF_REG_RISCV_GP:
  16                 return "gp";
  17         case PERF_REG_RISCV_TP:
  18                 return "tp";
  19         case PERF_REG_RISCV_T0:
  20                 return "t0";
  21         case PERF_REG_RISCV_T1:
  22                 return "t1";
  23         case PERF_REG_RISCV_T2:
  24                 return "t2";
  25         case PERF_REG_RISCV_S0:
  26                 return "s0";
  27         case PERF_REG_RISCV_S1:
  28                 return "s1";
  29         case PERF_REG_RISCV_A0:
  30                 return "a0";
  31         case PERF_REG_RISCV_A1:
  32                 return "a1";
  33         case PERF_REG_RISCV_A2:
  34                 return "a2";
  35         case PERF_REG_RISCV_A3:
  36                 return "a3";
  37         case PERF_REG_RISCV_A4:
  38                 return "a4";
  39         case PERF_REG_RISCV_A5:
  40                 return "a5";
  41         case PERF_REG_RISCV_A6:
  42                 return "a6";
  43         case PERF_REG_RISCV_A7:
  44                 return "a7";
  45         case PERF_REG_RISCV_S2:
  46                 return "s2";
  47         case PERF_REG_RISCV_S3:
  48                 return "s3";
  49         case PERF_REG_RISCV_S4:
  50                 return "s4";
  51         case PERF_REG_RISCV_S5:
  52                 return "s5";
  53         case PERF_REG_RISCV_S6:
  54                 return "s6";
  55         case PERF_REG_RISCV_S7:
  56                 return "s7";
  57         case PERF_REG_RISCV_S8:
  58                 return "s8";
  59         case PERF_REG_RISCV_S9:
  60                 return "s9";
  61         case PERF_REG_RISCV_S10:
  62                 return "s10";
  63         case PERF_REG_RISCV_S11:
  64                 return "s11";
  65         case PERF_REG_RISCV_T3:
  66                 return "t3";
  67         case PERF_REG_RISCV_T4:
  68                 return "t4";
  69         case PERF_REG_RISCV_T5:
  70                 return "t5";
  71         case PERF_REG_RISCV_T6:
  72                 return "t6";
  73         default:
  74                 return NULL;
  75         }
  76
  77         return NULL;
  78 }
  79
  80 uint64_t __perf_reg_ip_riscv(void)
  81 {
  82         return PERF_REG_RISCV_PC;
  83 }
  84
  85 uint64_t __perf_reg_sp_riscv(void)
  86 {
  87         return PERF_REG_RISCV_SP;
  88 }