tools/testing/selftests/powerpc/nx-gzip/include/crb.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 #ifndef __CRB_H
   3 #define __CRB_H
   4 #include <linux/types.h>
   5 #include "nx.h"
   6
   7 /* CCW 842 CI/FC masks
   8  * NX P8 workbook, section 4.3.1, figure 4-6
   9  * "CI/FC Boundary by NX CT type"
  10  */
  11 #define CCW_CI_842              (0x00003ff8)
  12 #define CCW_FC_842              (0x00000007)
  13
  14 /* Chapter 6.5.8 Coprocessor-Completion Block (CCB) */
  15
  16 #define CCB_VALUE               (0x3fffffffffffffff)
  17 #define CCB_ADDRESS             (0xfffffffffffffff8)
  18 #define CCB_CM                  (0x0000000000000007)
  19 #define CCB_CM0                 (0x0000000000000004)
  20 #define CCB_CM12                (0x0000000000000003)
  21
  22 #define CCB_CM0_ALL_COMPLETIONS (0x0)
  23 #define CCB_CM0_LAST_IN_CHAIN   (0x4)
  24 #define CCB_CM12_STORE          (0x0)
  25 #define CCB_CM12_INTERRUPT      (0x1)
  26
  27 #define CCB_SIZE                (0x10)
  28 #define CCB_ALIGN               CCB_SIZE
  29
  30 struct coprocessor_completion_block {
  31         __be64 value;
  32         __be64 address;
  33 } __aligned(CCB_ALIGN);
  34
  35
  36 /* Chapter 6.5.7 Coprocessor-Status Block (CSB) */
  37
  38 #define CSB_V                   (0x80)
  39 #define CSB_F                   (0x04)
  40 #define CSB_CH                  (0x03)
  41 #define CSB_CE_INCOMPLETE       (0x80)
  42 #define CSB_CE_TERMINATION      (0x40)
  43 #define CSB_CE_TPBC             (0x20)
  44
  45 #define CSB_CC_SUCCESS          (0)
  46 #define CSB_CC_INVALID_ALIGN    (1)
  47 #define CSB_CC_OPERAND_OVERLAP  (2)
  48 #define CSB_CC_DATA_LENGTH      (3)
  49 #define CSB_CC_TRANSLATION      (5)
  50 #define CSB_CC_PROTECTION       (6)
  51 #define CSB_CC_RD_EXTERNAL      (7)
  52 #define CSB_CC_INVALID_OPERAND  (8)
  53 #define CSB_CC_PRIVILEGE        (9)
  54 #define CSB_CC_INTERNAL         (10)
  55 #define CSB_CC_WR_EXTERNAL      (12)
  56 #define CSB_CC_NOSPC            (13)
  57 #define CSB_CC_EXCESSIVE_DDE    (14)
  58 #define CSB_CC_WR_TRANSLATION   (15)
  59 #define CSB_CC_WR_PROTECTION    (16)
  60 #define CSB_CC_UNKNOWN_CODE     (17)
  61 #define CSB_CC_ABORT            (18)
  62 #define CSB_CC_TRANSPORT        (20)
  63 #define CSB_CC_SEGMENTED_DDL    (31)
  64 #define CSB_CC_PROGRESS_POINT   (32)
  65 #define CSB_CC_DDE_OVERFLOW     (33)
  66 #define CSB_CC_SESSION          (34)
  67 #define CSB_CC_PROVISION        (36)
  68 #define CSB_CC_CHAIN            (37)
  69 #define CSB_CC_SEQUENCE         (38)
  70 #define CSB_CC_HW               (39)
  71
  72 #define CSB_SIZE                (0x10)
  73 #define CSB_ALIGN               CSB_SIZE
  74
  75 struct coprocessor_status_block {
  76         __u8 flags;
  77         __u8 cs;
  78         __u8 cc;
  79         __u8 ce;
  80         __be32 count;
  81         __be64 address;
  82 } __aligned(CSB_ALIGN);
  83
  84
  85 /* Chapter 6.5.10 Data-Descriptor List (DDL)
  86  * each list contains one or more Data-Descriptor Entries (DDE)
  87  */
  88
  89 #define DDE_P                   (0x8000)
  90
  91 #define DDE_SIZE                (0x10)
  92 #define DDE_ALIGN               DDE_SIZE
  93
  94 struct data_descriptor_entry {
  95         __be16 flags;
  96         __u8 count;
  97         __u8 index;
  98         __be32 length;
  99         __be64 address;
 100 } __aligned(DDE_ALIGN);
 101
 102
 103 /* Chapter 6.5.2 Coprocessor-Request Block (CRB) */
 104
 105 #define CRB_SIZE                (0x80)
 106 #define CRB_ALIGN               (0x100) /* Errata: requires 256 alignment */
 107
 108
 109 /* Coprocessor Status Block field
 110  *   ADDRESS    address of CSB
 111  *   C          CCB is valid
 112  *   AT         0 = addrs are virtual, 1 = addrs are phys
 113  *   M          enable perf monitor
 114  */
 115 #define CRB_CSB_ADDRESS         (0xfffffffffffffff0)
 116 #define CRB_CSB_C               (0x0000000000000008)
 117 #define CRB_CSB_AT              (0x0000000000000002)
 118 #define CRB_CSB_M               (0x0000000000000001)
 119
 120 struct coprocessor_request_block {
 121         __be32 ccw;
 122         __be32 flags;
 123         __be64 csb_addr;
 124
 125         struct data_descriptor_entry source;
 126         struct data_descriptor_entry target;
 127
 128         struct coprocessor_completion_block ccb;
 129
 130         __u8 reserved[48];
 131
 132         struct coprocessor_status_block csb;
 133 } __aligned(CRB_ALIGN);
 134
 135 #define crb_csb_addr(c)         __be64_to_cpu(c->csb_addr)
 136 #define crb_nx_fault_addr(c)    __be64_to_cpu(c->stamp.nx.fault_storage_addr)
 137 #define crb_nx_flags(c)         c->stamp.nx.flags
 138 #define crb_nx_fault_status(c)  c->stamp.nx.fault_status
 139 #define crb_nx_pswid(c)         c->stamp.nx.pswid
 140
 141
 142 /* RFC02167 Initiate Coprocessor Instructions document
 143  * Chapter 8.2.1.1.1 RS
 144  * Chapter 8.2.3 Coprocessor Directive
 145  * Chapter 8.2.4 Execution
 146  *
 147  * The CCW must be converted to BE before passing to icswx()
 148  */
 149
 150 #define CCW_PS                  (0xff000000)
 151 #define CCW_CT                  (0x00ff0000)
 152 #define CCW_CD                  (0x0000ffff)
 153 #define CCW_CL                  (0x0000c000)
 154
 155 #endif