1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright(c) 2016-20 Intel Corporation.
13 .fill 1, 8, 0 # STATE (set by CPU)
15 .quad encl_ssa_tcs1 # OSSA
16 .fill 1, 4, 0 # CSSA (set by CPU)
18 .quad encl_entry # OENTRY
19 .fill 1, 8, 0 # AEP (set by EENTER and ERESUME)
20 .fill 1, 8, 0 # OFSBASE
21 .fill 1, 8, 0 # OGSBASE
22 .fill 1, 4, 0xFFFFFFFF # FSLIMIT
23 .fill 1, 4, 0xFFFFFFFF # GSLIMIT
24 .fill 4024, 1, 0 # Reserved
27 .fill 1, 8, 0 # STATE (set by CPU)
29 .quad encl_ssa_tcs2 # OSSA
30 .fill 1, 4, 0 # CSSA (set by CPU)
32 .quad encl_entry # OENTRY
33 .fill 1, 8, 0 # AEP (set by EENTER and ERESUME)
34 .fill 1, 8, 0 # OFSBASE
35 .fill 1, 8, 0 # OGSBASE
36 .fill 1, 4, 0xFFFFFFFF # FSLIMIT
37 .fill 1, 4, 0xFFFFFFFF # GSLIMIT
38 .fill 4024, 1, 0 # Reserved
43 # RBX contains the base address for TCS, which is the first address
44 # inside the enclave for TCS #1 and one page into the enclave for
45 # TCS #2. First make it relative by substracting __encl_base and
46 # then add the address of encl_stack to get the address for the stack.
47 lea __encl_base(%rip), %rax
49 lea encl_stack(%rip), %rax
53 # Entry point for dynamically created TCS page expected to follow
60 push %rcx # push the address after EENTER
62 # NOTE: as the selftest enclave is *not* intended for production,
63 # simplify the code by not initializing ABI registers on entry or
64 # cleansing caller-save registers on exit.
67 # Prepare EEXIT target by popping the address of the instruction after
71 # Restore the caller stack.
79 .section ".data", "aw"