arch/x86/boot/cpuflags.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <linux/types.h>
   3 #include "bitops.h"
   4
   5 #include <asm/processor-flags.h>
   6 #include <asm/required-features.h>
   7 #include <asm/msr-index.h>
   8 #include "cpuflags.h"
   9
  10 struct cpu_features cpu;
  11 u32 cpu_vendor[3];
  12
  13 static bool loaded_flags;
  14
  15 static int has_fpu(void)
  16 {
  17         u16 fcw = -1, fsw = -1;
  18         unsigned long cr0;
  19
  20         asm volatile("mov %%cr0,%0" : "=r" (cr0));
  21         if (cr0 & (X86_CR0_EM|X86_CR0_TS)) {
  22                 cr0 &= ~(X86_CR0_EM|X86_CR0_TS);
  23                 asm volatile("mov %0,%%cr0" : : "r" (cr0));
  24         }
  25
  26         asm volatile("fninit ; fnstsw %0 ; fnstcw %1"
  27                      : "+m" (fsw), "+m" (fcw));
  28
  29         return fsw == 0 && (fcw & 0x103f) == 0x003f;
  30 }
  31
  32 /*
  33  * For building the 16-bit code we want to explicitly specify 32-bit
  34  * push/pop operations, rather than just saying 'pushf' or 'popf' and
  35  * letting the compiler choose. But this is also included from the
  36  * compressed/ directory where it may be 64-bit code, and thus needs
  37  * to be 'pushfq' or 'popfq' in that case.
  38  */
  39 #ifdef __x86_64__
  40 #define PUSHF "pushfq"
  41 #define POPF "popfq"
  42 #else
  43 #define PUSHF "pushfl"
  44 #define POPF "popfl"
  45 #endif
  46
  47 int has_eflag(unsigned long mask)
  48 {
  49         unsigned long f0, f1;
  50
  51         asm volatile(PUSHF "    \n\t"
  52                      PUSHF "    \n\t"
  53                      "pop %0    \n\t"
  54                      "mov %0,%1 \n\t"
  55                      "xor %2,%1 \n\t"
  56                      "push %1   \n\t"
  57                      POPF "     \n\t"
  58                      PUSHF "    \n\t"
  59                      "pop %1    \n\t"
  60                      POPF
  61                      : "=&r" (f0), "=&r" (f1)
  62                      : "ri" (mask));
  63
  64         return !!((f0^f1) & mask);
  65 }
  66
  67 void cpuid_count(u32 id, u32 count, u32 *a, u32 *b, u32 *c, u32 *d)
  68 {
  69         asm volatile("cpuid"
  70                      : "=a" (*a), "=b" (*b), "=c" (*c), "=d" (*d)
  71                      : "0" (id), "2" (count)
  72         );
  73 }
  74
  75 #define cpuid(id, a, b, c, d) cpuid_count(id, 0, a, b, c, d)
  76
  77 void get_cpuflags(void)
  78 {
  79         u32 max_intel_level, max_amd_level;
  80         u32 tfms;
  81         u32 ignored;
  82
  83         if (loaded_flags)
  84                 return;
  85         loaded_flags = true;
  86
  87         if (has_fpu())
  88                 set_bit(X86_FEATURE_FPU, cpu.flags);
  89
  90         if (has_eflag(X86_EFLAGS_ID)) {
  91                 cpuid(0x0, &max_intel_level, &cpu_vendor[0], &cpu_vendor[2],
  92                       &cpu_vendor[1]);
  93
  94                 if (max_intel_level >= 0x00000001 &&
  95                     max_intel_level <= 0x0000ffff) {
  96                         cpuid(0x1, &tfms, &ignored, &cpu.flags[4],
  97                               &cpu.flags[0]);
  98                         cpu.level = (tfms >> 8) & 15;
  99                         cpu.family = cpu.level;
 100                         cpu.model = (tfms >> 4) & 15;
 101                         if (cpu.level >= 6)
 102                                 cpu.model += ((tfms >> 16) & 0xf) << 4;
 103                 }
 104
 105                 if (max_intel_level >= 0x00000007) {
 106                         cpuid_count(0x00000007, 0, &ignored, &ignored,
 107                                         &cpu.flags[16], &ignored);
 108                 }
 109
 110                 cpuid(0x80000000, &max_amd_level, &ignored, &ignored,
 111                       &ignored);
 112
 113                 if (max_amd_level >= 0x80000001 &&
 114                     max_amd_level <= 0x8000ffff) {
 115                         cpuid(0x80000001, &ignored, &ignored, &cpu.flags[6],
 116                               &cpu.flags[1]);
 117                 }
 118         }
 119 }