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drm/tests: hdmi: Fix memory leaks in drm_display_mode_from_cea_vic()
[drm/drm-misc.git] / drivers / ata / sata_qstor.c
blob8a62861590441f0c7d01a3cfe0b3c19d223715e1
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * sata_qstor.c - Pacific Digital Corporation QStor SATA
4 *
5 * Maintained by: Mark Lord <mlord@pobox.com>
6 *
7 * Copyright 2005 Pacific Digital Corporation.
8 * (OSL/GPL code release authorized by Jalil Fadavi).
9 *
10 * libata documentation is available via 'make {ps|pdf}docs',
11 * as Documentation/driver-api/libata.rst
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/gfp.h>
17 #include <linux/pci.h>
18 #include <linux/blkdev.h>
19 #include <linux/delay.h>
20 #include <linux/interrupt.h>
21 #include <linux/device.h>
22 #include <scsi/scsi_host.h>
23 #include <linux/libata.h>
24
25 #define DRV_NAME "sata_qstor"
26 #define DRV_VERSION "0.09"
27
28 enum {
29 QS_MMIO_BAR = 4,
30
31 QS_PORTS = 4,
32 QS_MAX_PRD = LIBATA_MAX_PRD,
33 QS_CPB_ORDER = 6,
34 QS_CPB_BYTES = (1 << QS_CPB_ORDER),
35 QS_PRD_BYTES = QS_MAX_PRD * 16,
36 QS_PKT_BYTES = QS_CPB_BYTES + QS_PRD_BYTES,
37
38 /* global register offsets */
39 QS_HCF_CNFG3 = 0x0003, /* host configuration offset */
40 QS_HID_HPHY = 0x0004, /* host physical interface info */
41 QS_HCT_CTRL = 0x00e4, /* global interrupt mask offset */
42 QS_HST_SFF = 0x0100, /* host status fifo offset */
43 QS_HVS_SERD3 = 0x0393, /* PHY enable offset */
44
45 /* global control bits */
46 QS_HPHY_64BIT = (1 << 1), /* 64-bit bus detected */
47 QS_CNFG3_GSRST = 0x01, /* global chip reset */
48 QS_SERD3_PHY_ENA = 0xf0, /* PHY detection ENAble*/
49
50 /* per-channel register offsets */
51 QS_CCF_CPBA = 0x0710, /* chan CPB base address */
52 QS_CCF_CSEP = 0x0718, /* chan CPB separation factor */
53 QS_CFC_HUFT = 0x0800, /* host upstream fifo threshold */
54 QS_CFC_HDFT = 0x0804, /* host downstream fifo threshold */
55 QS_CFC_DUFT = 0x0808, /* dev upstream fifo threshold */
56 QS_CFC_DDFT = 0x080c, /* dev downstream fifo threshold */
57 QS_CCT_CTR0 = 0x0900, /* chan control-0 offset */
58 QS_CCT_CTR1 = 0x0901, /* chan control-1 offset */
59 QS_CCT_CFF = 0x0a00, /* chan command fifo offset */
60
61 /* channel control bits */
62 QS_CTR0_REG = (1 << 1), /* register mode (vs. pkt mode) */
63 QS_CTR0_CLER = (1 << 2), /* clear channel errors */
64 QS_CTR1_RDEV = (1 << 1), /* sata phy/comms reset */
65 QS_CTR1_RCHN = (1 << 4), /* reset channel logic */
66 QS_CCF_RUN_PKT = 0x107, /* RUN a new dma PKT */
67
68 /* pkt sub-field headers */
69 QS_HCB_HDR = 0x01, /* Host Control Block header */
70 QS_DCB_HDR = 0x02, /* Device Control Block header */
71
72 /* pkt HCB flag bits */
73 QS_HF_DIRO = (1 << 0), /* data DIRection Out */
74 QS_HF_DAT = (1 << 3), /* DATa pkt */
75 QS_HF_IEN = (1 << 4), /* Interrupt ENable */
76 QS_HF_VLD = (1 << 5), /* VaLiD pkt */
77
78 /* pkt DCB flag bits */
79 QS_DF_PORD = (1 << 2), /* Pio OR Dma */
80 QS_DF_ELBA = (1 << 3), /* Extended LBA (lba48) */
81
82 /* PCI device IDs */
83 board_2068_idx = 0, /* QStor 4-port SATA/RAID */
84 };
85
86 enum {
87 QS_DMA_BOUNDARY = ~0UL
88 };
89
90 typedef enum { qs_state_mmio, qs_state_pkt } qs_state_t;
91
92 struct qs_port_priv {
93 u8 *pkt;
94 dma_addr_t pkt_dma;
95 qs_state_t state;
96 };
97
98 static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
99 static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
100 static int qs_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
101 static int qs_port_start(struct ata_port *ap);
102 static void qs_host_stop(struct ata_host *host);
103 static enum ata_completion_errors qs_qc_prep(struct ata_queued_cmd *qc);
104 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc);
105 static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
106 static void qs_freeze(struct ata_port *ap);
107 static void qs_thaw(struct ata_port *ap);
108 static int qs_prereset(struct ata_link *link, unsigned long deadline);
109 static void qs_error_handler(struct ata_port *ap);
110
111 static const struct scsi_host_template qs_ata_sht = {
112 ATA_BASE_SHT(DRV_NAME),
113 .sg_tablesize = QS_MAX_PRD,
114 .dma_boundary = QS_DMA_BOUNDARY,
115 };
116
117 static struct ata_port_operations qs_ata_ops = {
118 .inherits = &ata_sff_port_ops,
119
120 .check_atapi_dma = qs_check_atapi_dma,
121 .qc_prep = qs_qc_prep,
122 .qc_issue = qs_qc_issue,
123
124 .freeze = qs_freeze,
125 .thaw = qs_thaw,
126 .prereset = qs_prereset,
127 .softreset = ATA_OP_NULL,
128 .error_handler = qs_error_handler,
129 .lost_interrupt = ATA_OP_NULL,
130
131 .scr_read = qs_scr_read,
132 .scr_write = qs_scr_write,
133
134 .port_start = qs_port_start,
135 .host_stop = qs_host_stop,
136 };
137
138 static const struct ata_port_info qs_port_info[] = {
139 /* board_2068_idx */
140 {
141 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_POLLING,
142 .pio_mask = ATA_PIO4_ONLY,
143 .udma_mask = ATA_UDMA6,
144 .port_ops = &qs_ata_ops,
145 },
146 };
147
148 static const struct pci_device_id qs_ata_pci_tbl[] = {
149 { PCI_VDEVICE(PDC, 0x2068), board_2068_idx },
150
151 { } /* terminate list */
152 };
153
154 static struct pci_driver qs_ata_pci_driver = {
155 .name = DRV_NAME,
156 .id_table = qs_ata_pci_tbl,
157 .probe = qs_ata_init_one,
158 .remove = ata_pci_remove_one,
159 };
160
161 static void __iomem *qs_mmio_base(struct ata_host *host)
162 {
163 return host->iomap[QS_MMIO_BAR];
164 }
165
166 static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
167 {
168 return 1; /* ATAPI DMA not supported */
169 }
170
171 static inline void qs_enter_reg_mode(struct ata_port *ap)
172 {
173 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
174 struct qs_port_priv *pp = ap->private_data;
175
176 pp->state = qs_state_mmio;
177 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
178 readb(chan + QS_CCT_CTR0); /* flush */
179 }
180
181 static inline void qs_reset_channel_logic(struct ata_port *ap)
182 {
183 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
184
185 writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1);
186 readb(chan + QS_CCT_CTR0); /* flush */
187 qs_enter_reg_mode(ap);
188 }
189
190 static void qs_freeze(struct ata_port *ap)
191 {
192 u8 __iomem *mmio_base = qs_mmio_base(ap->host);
193
194 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
195 qs_enter_reg_mode(ap);
196 }
197
198 static void qs_thaw(struct ata_port *ap)
199 {
200 u8 __iomem *mmio_base = qs_mmio_base(ap->host);
201
202 qs_enter_reg_mode(ap);
203 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
204 }
205
206 static int qs_prereset(struct ata_link *link, unsigned long deadline)
207 {
208 struct ata_port *ap = link->ap;
209
210 qs_reset_channel_logic(ap);
211 return ata_sff_prereset(link, deadline);
212 }
213
214 static int qs_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
215 {
216 if (sc_reg > SCR_CONTROL)
217 return -EINVAL;
218 *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 8));
219 return 0;
220 }
221
222 static void qs_error_handler(struct ata_port *ap)
223 {
224 qs_enter_reg_mode(ap);
225 ata_sff_error_handler(ap);
226 }
227
228 static int qs_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
229 {
230 if (sc_reg > SCR_CONTROL)
231 return -EINVAL;
232 writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 8));
233 return 0;
234 }
235
236 static unsigned int qs_fill_sg(struct ata_queued_cmd *qc)
237 {
238 struct scatterlist *sg;
239 struct ata_port *ap = qc->ap;
240 struct qs_port_priv *pp = ap->private_data;
241 u8 *prd = pp->pkt + QS_CPB_BYTES;
242 unsigned int si;
243
244 for_each_sg(qc->sg, sg, qc->n_elem, si) {
245 u64 addr;
246 u32 len;
247
248 addr = sg_dma_address(sg);
249 *(__le64 *)prd = cpu_to_le64(addr);
250 prd += sizeof(u64);
251
252 len = sg_dma_len(sg);
253 *(__le32 *)prd = cpu_to_le32(len);
254 prd += sizeof(u64);
255 }
256
257 return si;
258 }
259
260 static enum ata_completion_errors qs_qc_prep(struct ata_queued_cmd *qc)
261 {
262 struct qs_port_priv *pp = qc->ap->private_data;
263 u8 dflags = QS_DF_PORD, *buf = pp->pkt;
264 u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD;
265 u64 addr;
266 unsigned int nelem;
267
268 qs_enter_reg_mode(qc->ap);
269 if (qc->tf.protocol != ATA_PROT_DMA)
270 return AC_ERR_OK;
271
272 nelem = qs_fill_sg(qc);
273
274 if ((qc->tf.flags & ATA_TFLAG_WRITE))
275 hflags |= QS_HF_DIRO;
276 if ((qc->tf.flags & ATA_TFLAG_LBA48))
277 dflags |= QS_DF_ELBA;
278
279 /* host control block (HCB) */
280 buf[ 0] = QS_HCB_HDR;
281 buf[ 1] = hflags;
282 *(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nbytes);
283 *(__le32 *)(&buf[ 8]) = cpu_to_le32(nelem);
284 addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES;
285 *(__le64 *)(&buf[16]) = cpu_to_le64(addr);
286
287 /* device control block (DCB) */
288 buf[24] = QS_DCB_HDR;
289 buf[28] = dflags;
290
291 /* frame information structure (FIS) */
292 ata_tf_to_fis(&qc->tf, 0, 1, &buf[32]);
293
294 return AC_ERR_OK;
295 }
296
297 static inline void qs_packet_start(struct ata_queued_cmd *qc)
298 {
299 struct ata_port *ap = qc->ap;
300 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
301
302 writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0);
303 wmb(); /* flush PRDs and pkt to memory */
304 writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
305 readl(chan + QS_CCT_CFF); /* flush */
306 }
307
308 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc)
309 {
310 struct qs_port_priv *pp = qc->ap->private_data;
311
312 switch (qc->tf.protocol) {
313 case ATA_PROT_DMA:
314 pp->state = qs_state_pkt;
315 qs_packet_start(qc);
316 return 0;
317
318 case ATAPI_PROT_DMA:
319 BUG();
320 break;
321
322 default:
323 break;
324 }
325
326 pp->state = qs_state_mmio;
327 return ata_sff_qc_issue(qc);
328 }
329
330 static void qs_do_or_die(struct ata_queued_cmd *qc, u8 status)
331 {
332 qc->err_mask |= ac_err_mask(status);
333
334 if (!qc->err_mask) {
335 ata_qc_complete(qc);
336 } else {
337 struct ata_port *ap = qc->ap;
338 struct ata_eh_info *ehi = &ap->link.eh_info;
339
340 ata_ehi_clear_desc(ehi);
341 ata_ehi_push_desc(ehi, "status 0x%02X", status);
342
343 if (qc->err_mask == AC_ERR_DEV)
344 ata_port_abort(ap);
345 else
346 ata_port_freeze(ap);
347 }
348 }
349
350 static inline unsigned int qs_intr_pkt(struct ata_host *host)
351 {
352 unsigned int handled = 0;
353 u8 sFFE;
354 u8 __iomem *mmio_base = qs_mmio_base(host);
355
356 do {
357 u32 sff0 = readl(mmio_base + QS_HST_SFF);
358 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
359 u8 sEVLD = (sff1 >> 30) & 0x01; /* valid flag */
360 sFFE = sff1 >> 31; /* empty flag */
361
362 if (sEVLD) {
363 u8 sDST = sff0 >> 16; /* dev status */
364 u8 sHST = sff1 & 0x3f; /* host status */
365 unsigned int port_no = (sff1 >> 8) & 0x03;
366 struct ata_port *ap = host->ports[port_no];
367 struct qs_port_priv *pp = ap->private_data;
368 struct ata_queued_cmd *qc;
369
370 dev_dbg(host->dev, "SFF=%08x%08x: sHST=%d sDST=%02x\n",
371 sff1, sff0, sHST, sDST);
372 handled = 1;
373 if (!pp || pp->state != qs_state_pkt)
374 continue;
375 qc = ata_qc_from_tag(ap, ap->link.active_tag);
376 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
377 switch (sHST) {
378 case 0: /* successful CPB */
379 case 3: /* device error */
380 qs_enter_reg_mode(qc->ap);
381 qs_do_or_die(qc, sDST);
382 break;
383 default:
384 break;
385 }
386 }
387 }
388 } while (!sFFE);
389 return handled;
390 }
391
392 static inline unsigned int qs_intr_mmio(struct ata_host *host)
393 {
394 unsigned int handled = 0, port_no;
395
396 for (port_no = 0; port_no < host->n_ports; ++port_no) {
397 struct ata_port *ap = host->ports[port_no];
398 struct qs_port_priv *pp = ap->private_data;
399 struct ata_queued_cmd *qc;
400
401 qc = ata_qc_from_tag(ap, ap->link.active_tag);
402 if (!qc) {
403 /*
404 * The qstor hardware generates spurious
405 * interrupts from time to time when switching
406 * in and out of packet mode. There's no
407 * obvious way to know if we're here now due
408 * to that, so just ack the irq and pretend we
409 * knew it was ours.. (ugh). This does not
410 * affect packet mode.
411 */
412 ata_sff_check_status(ap);
413 handled = 1;
414 continue;
415 }
416
417 if (!pp || pp->state != qs_state_mmio)
418 continue;
419 if (!(qc->tf.flags & ATA_TFLAG_POLLING))
420 handled |= ata_sff_port_intr(ap, qc);
421 }
422 return handled;
423 }
424
425 static irqreturn_t qs_intr(int irq, void *dev_instance)
426 {
427 struct ata_host *host = dev_instance;
428 unsigned int handled = 0;
429 unsigned long flags;
430
431 spin_lock_irqsave(&host->lock, flags);
432 handled = qs_intr_pkt(host) | qs_intr_mmio(host);
433 spin_unlock_irqrestore(&host->lock, flags);
434
435 return IRQ_RETVAL(handled);
436 }
437
438 static void qs_ata_setup_port(struct ata_ioports *port, void __iomem *base)
439 {
440 port->cmd_addr =
441 port->data_addr = base + 0x400;
442 port->error_addr =
443 port->feature_addr = base + 0x408; /* hob_feature = 0x409 */
444 port->nsect_addr = base + 0x410; /* hob_nsect = 0x411 */
445 port->lbal_addr = base + 0x418; /* hob_lbal = 0x419 */
446 port->lbam_addr = base + 0x420; /* hob_lbam = 0x421 */
447 port->lbah_addr = base + 0x428; /* hob_lbah = 0x429 */
448 port->device_addr = base + 0x430;
449 port->status_addr =
450 port->command_addr = base + 0x438;
451 port->altstatus_addr =
452 port->ctl_addr = base + 0x440;
453 port->scr_addr = base + 0xc00;
454 }
455
456 static int qs_port_start(struct ata_port *ap)
457 {
458 struct device *dev = ap->host->dev;
459 struct qs_port_priv *pp;
460 void __iomem *mmio_base = qs_mmio_base(ap->host);
461 void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
462 u64 addr;
463
464 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
465 if (!pp)
466 return -ENOMEM;
467 pp->pkt = dmam_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma,
468 GFP_KERNEL);
469 if (!pp->pkt)
470 return -ENOMEM;
471 ap->private_data = pp;
472
473 qs_enter_reg_mode(ap);
474 addr = (u64)pp->pkt_dma;
475 writel((u32) addr, chan + QS_CCF_CPBA);
476 writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);
477 return 0;
478 }
479
480 static void qs_host_stop(struct ata_host *host)
481 {
482 void __iomem *mmio_base = qs_mmio_base(host);
483
484 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
485 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
486 }
487
488 static void qs_host_init(struct ata_host *host, unsigned int chip_id)
489 {
490 void __iomem *mmio_base = host->iomap[QS_MMIO_BAR];
491 unsigned int port_no;
492
493 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
494 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
495
496 /* reset each channel in turn */
497 for (port_no = 0; port_no < host->n_ports; ++port_no) {
498 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
499 writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1);
500 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
501 readb(chan + QS_CCT_CTR0); /* flush */
502 }
503 writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
504
505 for (port_no = 0; port_no < host->n_ports; ++port_no) {
506 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
507 /* set FIFO depths to same settings as Windows driver */
508 writew(32, chan + QS_CFC_HUFT);
509 writew(32, chan + QS_CFC_HDFT);
510 writew(10, chan + QS_CFC_DUFT);
511 writew( 8, chan + QS_CFC_DDFT);
512 /* set CPB size in bytes, as a power of two */
513 writeb(QS_CPB_ORDER, chan + QS_CCF_CSEP);
514 }
515 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
516 }
517
518 /*
519 * The QStor understands 64-bit buses, and uses 64-bit fields
520 * for DMA pointers regardless of bus width. We just have to
521 * make sure our DMA masks are set appropriately for whatever
522 * bridge lies between us and the QStor, and then the DMA mapping
523 * code will ensure we only ever "see" appropriate buffer addresses.
524 * If we're 32-bit limited somewhere, then our 64-bit fields will
525 * just end up with zeros in the upper 32-bits, without any special
526 * logic required outside of this routine (below).
527 */
528 static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
529 {
530 u32 bus_info = readl(mmio_base + QS_HID_HPHY);
531 int dma_bits = (bus_info & QS_HPHY_64BIT) ? 64 : 32;
532 int rc;
533
534 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
535 if (rc)
536 dev_err(&pdev->dev, "%d-bit DMA enable failed\n", dma_bits);
537 return rc;
538 }
539
540 static int qs_ata_init_one(struct pci_dev *pdev,
541 const struct pci_device_id *ent)
542 {
543 unsigned int board_idx = (unsigned int) ent->driver_data;
544 const struct ata_port_info *ppi[] = { &qs_port_info[board_idx], NULL };
545 struct ata_host *host;
546 int rc, port_no;
547
548 ata_print_version_once(&pdev->dev, DRV_VERSION);
549
550 /* alloc host */
551 host = ata_host_alloc_pinfo(&pdev->dev, ppi, QS_PORTS);
552 if (!host)
553 return -ENOMEM;
554
555 /* acquire resources and fill host */
556 rc = pcim_enable_device(pdev);
557 if (rc)
558 return rc;
559
560 if ((pci_resource_flags(pdev, QS_MMIO_BAR) & IORESOURCE_MEM) == 0)
561 return -ENODEV;
562
563 rc = pcim_iomap_regions(pdev, 1 << QS_MMIO_BAR, DRV_NAME);
564 if (rc)
565 return rc;
566 host->iomap = pcim_iomap_table(pdev);
567
568 rc = qs_set_dma_masks(pdev, host->iomap[QS_MMIO_BAR]);
569 if (rc)
570 return rc;
571
572 for (port_no = 0; port_no < host->n_ports; ++port_no) {
573 struct ata_port *ap = host->ports[port_no];
574 unsigned int offset = port_no * 0x4000;
575 void __iomem *chan = host->iomap[QS_MMIO_BAR] + offset;
576
577 qs_ata_setup_port(&ap->ioaddr, chan);
578
579 ata_port_pbar_desc(ap, QS_MMIO_BAR, -1, "mmio");
580 ata_port_pbar_desc(ap, QS_MMIO_BAR, offset, "port");
581 }
582
583 /* initialize adapter */
584 qs_host_init(host, board_idx);
585
586 pci_set_master(pdev);
587 return ata_host_activate(host, pdev->irq, qs_intr, IRQF_SHARED,
588 &qs_ata_sht);
589 }
590
591 module_pci_driver(qs_ata_pci_driver);
592
593 MODULE_AUTHOR("Mark Lord");
594 MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");
595 MODULE_LICENSE("GPL");
596 MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl);
597 MODULE_VERSION(DRV_VERSION);
Kernel DRM miscellaneous fixes and cross-tree changes