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drm/tests: hdmi: Fix memory leaks in drm_display_mode_from_cea_vic()
[drm/drm-misc.git] / drivers / clk / clk-en7523.c
blob22fbea61c3dcc05e63f8fa37e203c62b2a6fe79e
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <linux/delay.h>
4 #include <linux/clk-provider.h>
5 #include <linux/io.h>
6 #include <linux/platform_device.h>
7 #include <linux/property.h>
8 #include <linux/reset-controller.h>
9 #include <dt-bindings/clock/en7523-clk.h>
10 #include <dt-bindings/reset/airoha,en7581-reset.h>
11
12 #define RST_NR_PER_BANK 32
13
14 #define REG_PCI_CONTROL 0x88
15 #define REG_PCI_CONTROL_PERSTOUT BIT(29)
16 #define REG_PCI_CONTROL_PERSTOUT1 BIT(26)
17 #define REG_PCI_CONTROL_REFCLK_EN0 BIT(23)
18 #define REG_PCI_CONTROL_REFCLK_EN1 BIT(22)
19 #define REG_PCI_CONTROL_PERSTOUT2 BIT(16)
20 #define REG_GSW_CLK_DIV_SEL 0x1b4
21 #define REG_EMI_CLK_DIV_SEL 0x1b8
22 #define REG_BUS_CLK_DIV_SEL 0x1bc
23 #define REG_SPI_CLK_DIV_SEL 0x1c4
24 #define REG_SPI_CLK_FREQ_SEL 0x1c8
25 #define REG_NPU_CLK_DIV_SEL 0x1fc
26 #define REG_CRYPTO_CLKSRC 0x200
27 #define REG_RESET_CONTROL2 0x830
28 #define REG_RESET2_CONTROL_PCIE2 BIT(27)
29 #define REG_RESET_CONTROL1 0x834
30 #define REG_RESET_CONTROL_PCIEHB BIT(29)
31 #define REG_RESET_CONTROL_PCIE1 BIT(27)
32 #define REG_RESET_CONTROL_PCIE2 BIT(26)
33 /* EN7581 */
34 #define REG_PCIE0_MEM 0x00
35 #define REG_PCIE0_MEM_MASK 0x04
36 #define REG_PCIE1_MEM 0x08
37 #define REG_PCIE1_MEM_MASK 0x0c
38 #define REG_PCIE2_MEM 0x10
39 #define REG_PCIE2_MEM_MASK 0x14
40 #define REG_NP_SCU_PCIC 0x88
41 #define REG_NP_SCU_SSTR 0x9c
42 #define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13)
43 #define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11)
44
45 #define REG_RST_CTRL2 0x00
46 #define REG_RST_CTRL1 0x04
47
48 struct en_clk_desc {
49 int id;
50 const char *name;
51 u32 base_reg;
52 u8 base_bits;
53 u8 base_shift;
54 union {
55 const unsigned int *base_values;
56 unsigned int base_value;
57 };
58 size_t n_base_values;
59
60 u16 div_reg;
61 u8 div_bits;
62 u8 div_shift;
63 u16 div_val0;
64 u8 div_step;
65 u8 div_offset;
66 };
67
68 struct en_clk_gate {
69 void __iomem *base;
70 struct clk_hw hw;
71 };
72
73 struct en_rst_data {
74 const u16 *bank_ofs;
75 const u16 *idx_map;
76 void __iomem *base;
77 struct reset_controller_dev rcdev;
78 };
79
80 struct en_clk_soc_data {
81 const struct clk_ops pcie_ops;
82 struct {
83 const u16 *bank_ofs;
84 const u16 *idx_map;
85 u16 idx_map_nr;
86 } reset;
87 int (*hw_init)(struct platform_device *pdev, void __iomem *np_base);
88 };
89
90 static const u32 gsw_base[] = { 400000000, 500000000 };
91 static const u32 emi_base[] = { 333000000, 400000000 };
92 static const u32 bus_base[] = { 500000000, 540000000 };
93 static const u32 slic_base[] = { 100000000, 3125000 };
94 static const u32 npu_base[] = { 333000000, 400000000, 500000000 };
95
96 static const struct en_clk_desc en7523_base_clks[] = {
97 {
98 .id = EN7523_CLK_GSW,
99 .name = "gsw",
100
101 .base_reg = REG_GSW_CLK_DIV_SEL,
102 .base_bits = 1,
103 .base_shift = 8,
104 .base_values = gsw_base,
105 .n_base_values = ARRAY_SIZE(gsw_base),
106
107 .div_bits = 3,
108 .div_shift = 0,
109 .div_step = 1,
110 .div_offset = 1,
111 }, {
112 .id = EN7523_CLK_EMI,
113 .name = "emi",
114
115 .base_reg = REG_EMI_CLK_DIV_SEL,
116 .base_bits = 1,
117 .base_shift = 8,
118 .base_values = emi_base,
119 .n_base_values = ARRAY_SIZE(emi_base),
120
121 .div_bits = 3,
122 .div_shift = 0,
123 .div_step = 1,
124 .div_offset = 1,
125 }, {
126 .id = EN7523_CLK_BUS,
127 .name = "bus",
128
129 .base_reg = REG_BUS_CLK_DIV_SEL,
130 .base_bits = 1,
131 .base_shift = 8,
132 .base_values = bus_base,
133 .n_base_values = ARRAY_SIZE(bus_base),
134
135 .div_bits = 3,
136 .div_shift = 0,
137 .div_step = 1,
138 .div_offset = 1,
139 }, {
140 .id = EN7523_CLK_SLIC,
141 .name = "slic",
142
143 .base_reg = REG_SPI_CLK_FREQ_SEL,
144 .base_bits = 1,
145 .base_shift = 0,
146 .base_values = slic_base,
147 .n_base_values = ARRAY_SIZE(slic_base),
148
149 .div_reg = REG_SPI_CLK_DIV_SEL,
150 .div_bits = 5,
151 .div_shift = 24,
152 .div_val0 = 20,
153 .div_step = 2,
154 }, {
155 .id = EN7523_CLK_SPI,
156 .name = "spi",
157
158 .base_reg = REG_SPI_CLK_DIV_SEL,
159
160 .base_value = 400000000,
161
162 .div_bits = 5,
163 .div_shift = 8,
164 .div_val0 = 40,
165 .div_step = 2,
166 }, {
167 .id = EN7523_CLK_NPU,
168 .name = "npu",
169
170 .base_reg = REG_NPU_CLK_DIV_SEL,
171 .base_bits = 2,
172 .base_shift = 8,
173 .base_values = npu_base,
174 .n_base_values = ARRAY_SIZE(npu_base),
175
176 .div_bits = 3,
177 .div_shift = 0,
178 .div_step = 1,
179 .div_offset = 1,
180 }, {
181 .id = EN7523_CLK_CRYPTO,
182 .name = "crypto",
183
184 .base_reg = REG_CRYPTO_CLKSRC,
185 .base_bits = 1,
186 .base_shift = 0,
187 .base_values = emi_base,
188 .n_base_values = ARRAY_SIZE(emi_base),
189 }
190 };
191
192 static const u16 en7581_rst_ofs[] = {
193 REG_RST_CTRL2,
194 REG_RST_CTRL1,
195 };
196
197 static const u16 en7581_rst_map[] = {
198 /* RST_CTRL2 */
199 [EN7581_XPON_PHY_RST] = 0,
200 [EN7581_CPU_TIMER2_RST] = 2,
201 [EN7581_HSUART_RST] = 3,
202 [EN7581_UART4_RST] = 4,
203 [EN7581_UART5_RST] = 5,
204 [EN7581_I2C2_RST] = 6,
205 [EN7581_XSI_MAC_RST] = 7,
206 [EN7581_XSI_PHY_RST] = 8,
207 [EN7581_NPU_RST] = 9,
208 [EN7581_I2S_RST] = 10,
209 [EN7581_TRNG_RST] = 11,
210 [EN7581_TRNG_MSTART_RST] = 12,
211 [EN7581_DUAL_HSI0_RST] = 13,
212 [EN7581_DUAL_HSI1_RST] = 14,
213 [EN7581_HSI_RST] = 15,
214 [EN7581_DUAL_HSI0_MAC_RST] = 16,
215 [EN7581_DUAL_HSI1_MAC_RST] = 17,
216 [EN7581_HSI_MAC_RST] = 18,
217 [EN7581_WDMA_RST] = 19,
218 [EN7581_WOE0_RST] = 20,
219 [EN7581_WOE1_RST] = 21,
220 [EN7581_HSDMA_RST] = 22,
221 [EN7581_TDMA_RST] = 24,
222 [EN7581_EMMC_RST] = 25,
223 [EN7581_SOE_RST] = 26,
224 [EN7581_PCIE2_RST] = 27,
225 [EN7581_XFP_MAC_RST] = 28,
226 [EN7581_USB_HOST_P1_RST] = 29,
227 [EN7581_USB_HOST_P1_U3_PHY_RST] = 30,
228 /* RST_CTRL1 */
229 [EN7581_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0,
230 [EN7581_FE_PDMA_RST] = RST_NR_PER_BANK + 1,
231 [EN7581_FE_QDMA_RST] = RST_NR_PER_BANK + 2,
232 [EN7581_PCM_SPIWP_RST] = RST_NR_PER_BANK + 4,
233 [EN7581_CRYPTO_RST] = RST_NR_PER_BANK + 6,
234 [EN7581_TIMER_RST] = RST_NR_PER_BANK + 8,
235 [EN7581_PCM1_RST] = RST_NR_PER_BANK + 11,
236 [EN7581_UART_RST] = RST_NR_PER_BANK + 12,
237 [EN7581_GPIO_RST] = RST_NR_PER_BANK + 13,
238 [EN7581_GDMA_RST] = RST_NR_PER_BANK + 14,
239 [EN7581_I2C_MASTER_RST] = RST_NR_PER_BANK + 16,
240 [EN7581_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17,
241 [EN7581_SFC_RST] = RST_NR_PER_BANK + 18,
242 [EN7581_UART2_RST] = RST_NR_PER_BANK + 19,
243 [EN7581_GDMP_RST] = RST_NR_PER_BANK + 20,
244 [EN7581_FE_RST] = RST_NR_PER_BANK + 21,
245 [EN7581_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22,
246 [EN7581_GSW_RST] = RST_NR_PER_BANK + 23,
247 [EN7581_SFC2_PCM_RST] = RST_NR_PER_BANK + 25,
248 [EN7581_PCIE0_RST] = RST_NR_PER_BANK + 26,
249 [EN7581_PCIE1_RST] = RST_NR_PER_BANK + 27,
250 [EN7581_CPU_TIMER_RST] = RST_NR_PER_BANK + 28,
251 [EN7581_PCIE_HB_RST] = RST_NR_PER_BANK + 29,
252 [EN7581_XPON_MAC_RST] = RST_NR_PER_BANK + 31,
253 };
254
255 static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i)
256 {
257 const struct en_clk_desc *desc = &en7523_base_clks[i];
258 u32 val;
259
260 if (!desc->base_bits)
261 return desc->base_value;
262
263 val = readl(base + desc->base_reg);
264 val >>= desc->base_shift;
265 val &= (1 << desc->base_bits) - 1;
266
267 if (val >= desc->n_base_values)
268 return 0;
269
270 return desc->base_values[val];
271 }
272
273 static u32 en7523_get_div(void __iomem *base, int i)
274 {
275 const struct en_clk_desc *desc = &en7523_base_clks[i];
276 u32 reg, val;
277
278 if (!desc->div_bits)
279 return 1;
280
281 reg = desc->div_reg ? desc->div_reg : desc->base_reg;
282 val = readl(base + reg);
283 val >>= desc->div_shift;
284 val &= (1 << desc->div_bits) - 1;
285
286 if (!val && desc->div_val0)
287 return desc->div_val0;
288
289 return (val + desc->div_offset) * desc->div_step;
290 }
291
292 static int en7523_pci_is_enabled(struct clk_hw *hw)
293 {
294 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
295
296 return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1);
297 }
298
299 static int en7523_pci_prepare(struct clk_hw *hw)
300 {
301 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
302 void __iomem *np_base = cg->base;
303 u32 val, mask;
304
305 /* Need to pull device low before reset */
306 val = readl(np_base + REG_PCI_CONTROL);
307 val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT);
308 writel(val, np_base + REG_PCI_CONTROL);
309 usleep_range(1000, 2000);
310
311 /* Enable PCIe port 1 */
312 val |= REG_PCI_CONTROL_REFCLK_EN1;
313 writel(val, np_base + REG_PCI_CONTROL);
314 usleep_range(1000, 2000);
315
316 /* Reset to default */
317 val = readl(np_base + REG_RESET_CONTROL1);
318 mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
319 REG_RESET_CONTROL_PCIEHB;
320 writel(val & ~mask, np_base + REG_RESET_CONTROL1);
321 usleep_range(1000, 2000);
322 writel(val | mask, np_base + REG_RESET_CONTROL1);
323 msleep(100);
324 writel(val & ~mask, np_base + REG_RESET_CONTROL1);
325 usleep_range(5000, 10000);
326
327 /* Release device */
328 mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT;
329 val = readl(np_base + REG_PCI_CONTROL);
330 writel(val & ~mask, np_base + REG_PCI_CONTROL);
331 usleep_range(1000, 2000);
332 writel(val | mask, np_base + REG_PCI_CONTROL);
333 msleep(250);
334
335 return 0;
336 }
337
338 static void en7523_pci_unprepare(struct clk_hw *hw)
339 {
340 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
341 void __iomem *np_base = cg->base;
342 u32 val;
343
344 val = readl(np_base + REG_PCI_CONTROL);
345 val &= ~REG_PCI_CONTROL_REFCLK_EN1;
346 writel(val, np_base + REG_PCI_CONTROL);
347 }
348
349 static struct clk_hw *en7523_register_pcie_clk(struct device *dev,
350 void __iomem *np_base)
351 {
352 const struct en_clk_soc_data *soc_data = device_get_match_data(dev);
353 struct clk_init_data init = {
354 .name = "pcie",
355 .ops = &soc_data->pcie_ops,
356 };
357 struct en_clk_gate *cg;
358
359 cg = devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL);
360 if (!cg)
361 return NULL;
362
363 cg->base = np_base;
364 cg->hw.init = &init;
365
366 if (init.ops->unprepare)
367 init.ops->unprepare(&cg->hw);
368
369 if (clk_hw_register(dev, &cg->hw))
370 return NULL;
371
372 return &cg->hw;
373 }
374
375 static int en7581_pci_is_enabled(struct clk_hw *hw)
376 {
377 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
378 u32 val, mask;
379
380 mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1;
381 val = readl(cg->base + REG_PCI_CONTROL);
382 return (val & mask) == mask;
383 }
384
385 static int en7581_pci_enable(struct clk_hw *hw)
386 {
387 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
388 void __iomem *np_base = cg->base;
389 u32 val, mask;
390
391 mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 |
392 REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 |
393 REG_PCI_CONTROL_PERSTOUT;
394 val = readl(np_base + REG_PCI_CONTROL);
395 writel(val | mask, np_base + REG_PCI_CONTROL);
396 msleep(250);
397
398 return 0;
399 }
400
401 static void en7581_pci_disable(struct clk_hw *hw)
402 {
403 struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
404 void __iomem *np_base = cg->base;
405 u32 val, mask;
406
407 mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 |
408 REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 |
409 REG_PCI_CONTROL_PERSTOUT;
410 val = readl(np_base + REG_PCI_CONTROL);
411 writel(val & ~mask, np_base + REG_PCI_CONTROL);
412 usleep_range(1000, 2000);
413 }
414
415 static int en7581_clk_hw_init(struct platform_device *pdev,
416 void __iomem *np_base)
417 {
418 void __iomem *pb_base;
419 u32 val;
420
421 pb_base = devm_platform_ioremap_resource(pdev, 3);
422 if (IS_ERR(pb_base))
423 return PTR_ERR(pb_base);
424
425 val = readl(np_base + REG_NP_SCU_SSTR);
426 val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK);
427 writel(val, np_base + REG_NP_SCU_SSTR);
428 val = readl(np_base + REG_NP_SCU_PCIC);
429 writel(val | 3, np_base + REG_NP_SCU_PCIC);
430
431 writel(0x20000000, pb_base + REG_PCIE0_MEM);
432 writel(0xfc000000, pb_base + REG_PCIE0_MEM_MASK);
433 writel(0x24000000, pb_base + REG_PCIE1_MEM);
434 writel(0xfc000000, pb_base + REG_PCIE1_MEM_MASK);
435 writel(0x28000000, pb_base + REG_PCIE2_MEM);
436 writel(0xfc000000, pb_base + REG_PCIE2_MEM_MASK);
437
438 return 0;
439 }
440
441 static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data,
442 void __iomem *base, void __iomem *np_base)
443 {
444 struct clk_hw *hw;
445 u32 rate;
446 int i;
447
448 for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) {
449 const struct en_clk_desc *desc = &en7523_base_clks[i];
450
451 rate = en7523_get_base_rate(base, i);
452 rate /= en7523_get_div(base, i);
453
454 hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate);
455 if (IS_ERR(hw)) {
456 pr_err("Failed to register clk %s: %ld\n",
457 desc->name, PTR_ERR(hw));
458 continue;
459 }
460
461 clk_data->hws[desc->id] = hw;
462 }
463
464 hw = en7523_register_pcie_clk(dev, np_base);
465 clk_data->hws[EN7523_CLK_PCIE] = hw;
466
467 clk_data->num = EN7523_NUM_CLOCKS;
468 }
469
470 static int en7523_reset_update(struct reset_controller_dev *rcdev,
471 unsigned long id, bool assert)
472 {
473 struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev);
474 void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK];
475 u32 val;
476
477 val = readl(addr);
478 if (assert)
479 val |= BIT(id % RST_NR_PER_BANK);
480 else
481 val &= ~BIT(id % RST_NR_PER_BANK);
482 writel(val, addr);
483
484 return 0;
485 }
486
487 static int en7523_reset_assert(struct reset_controller_dev *rcdev,
488 unsigned long id)
489 {
490 return en7523_reset_update(rcdev, id, true);
491 }
492
493 static int en7523_reset_deassert(struct reset_controller_dev *rcdev,
494 unsigned long id)
495 {
496 return en7523_reset_update(rcdev, id, false);
497 }
498
499 static int en7523_reset_status(struct reset_controller_dev *rcdev,
500 unsigned long id)
501 {
502 struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev);
503 void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK];
504
505 return !!(readl(addr) & BIT(id % RST_NR_PER_BANK));
506 }
507
508 static int en7523_reset_xlate(struct reset_controller_dev *rcdev,
509 const struct of_phandle_args *reset_spec)
510 {
511 struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev);
512
513 if (reset_spec->args[0] >= rcdev->nr_resets)
514 return -EINVAL;
515
516 return rst_data->idx_map[reset_spec->args[0]];
517 }
518
519 static const struct reset_control_ops en7523_reset_ops = {
520 .assert = en7523_reset_assert,
521 .deassert = en7523_reset_deassert,
522 .status = en7523_reset_status,
523 };
524
525 static int en7523_reset_register(struct platform_device *pdev,
526 const struct en_clk_soc_data *soc_data)
527 {
528 struct device *dev = &pdev->dev;
529 struct en_rst_data *rst_data;
530 void __iomem *base;
531
532 /* no reset lines available */
533 if (!soc_data->reset.idx_map_nr)
534 return 0;
535
536 base = devm_platform_ioremap_resource(pdev, 2);
537 if (IS_ERR(base))
538 return PTR_ERR(base);
539
540 rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL);
541 if (!rst_data)
542 return -ENOMEM;
543
544 rst_data->bank_ofs = soc_data->reset.bank_ofs;
545 rst_data->idx_map = soc_data->reset.idx_map;
546 rst_data->base = base;
547
548 rst_data->rcdev.nr_resets = soc_data->reset.idx_map_nr;
549 rst_data->rcdev.of_xlate = en7523_reset_xlate;
550 rst_data->rcdev.ops = &en7523_reset_ops;
551 rst_data->rcdev.of_node = dev->of_node;
552 rst_data->rcdev.of_reset_n_cells = 1;
553 rst_data->rcdev.owner = THIS_MODULE;
554 rst_data->rcdev.dev = dev;
555
556 return devm_reset_controller_register(dev, &rst_data->rcdev);
557 }
558
559 static int en7523_clk_probe(struct platform_device *pdev)
560 {
561 struct device_node *node = pdev->dev.of_node;
562 const struct en_clk_soc_data *soc_data;
563 struct clk_hw_onecell_data *clk_data;
564 void __iomem *base, *np_base;
565 int r;
566
567 base = devm_platform_ioremap_resource(pdev, 0);
568 if (IS_ERR(base))
569 return PTR_ERR(base);
570
571 np_base = devm_platform_ioremap_resource(pdev, 1);
572 if (IS_ERR(np_base))
573 return PTR_ERR(np_base);
574
575 soc_data = device_get_match_data(&pdev->dev);
576 if (soc_data->hw_init) {
577 r = soc_data->hw_init(pdev, np_base);
578 if (r)
579 return r;
580 }
581
582 clk_data = devm_kzalloc(&pdev->dev,
583 struct_size(clk_data, hws, EN7523_NUM_CLOCKS),
584 GFP_KERNEL);
585 if (!clk_data)
586 return -ENOMEM;
587
588 en7523_register_clocks(&pdev->dev, clk_data, base, np_base);
589
590 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
591 if (r)
592 return dev_err_probe(&pdev->dev, r, "Could not register clock provider: %s\n",
593 pdev->name);
594
595 r = en7523_reset_register(pdev, soc_data);
596 if (r) {
597 of_clk_del_provider(node);
598 return dev_err_probe(&pdev->dev, r, "Could not register reset controller: %s\n",
599 pdev->name);
600 }
601
602 return 0;
603 }
604
605 static const struct en_clk_soc_data en7523_data = {
606 .pcie_ops = {
607 .is_enabled = en7523_pci_is_enabled,
608 .prepare = en7523_pci_prepare,
609 .unprepare = en7523_pci_unprepare,
610 },
611 };
612
613 static const struct en_clk_soc_data en7581_data = {
614 .pcie_ops = {
615 .is_enabled = en7581_pci_is_enabled,
616 .enable = en7581_pci_enable,
617 .disable = en7581_pci_disable,
618 },
619 .reset = {
620 .bank_ofs = en7581_rst_ofs,
621 .idx_map = en7581_rst_map,
622 .idx_map_nr = ARRAY_SIZE(en7581_rst_map),
623 },
624 .hw_init = en7581_clk_hw_init,
625 };
626
627 static const struct of_device_id of_match_clk_en7523[] = {
628 { .compatible = "airoha,en7523-scu", .data = &en7523_data },
629 { .compatible = "airoha,en7581-scu", .data = &en7581_data },
630 { /* sentinel */ }
631 };
632
633 static struct platform_driver clk_en7523_drv = {
634 .probe = en7523_clk_probe,
635 .driver = {
636 .name = "clk-en7523",
637 .of_match_table = of_match_clk_en7523,
638 .suppress_bind_attrs = true,
639 },
640 };
641
642 static int __init clk_en7523_init(void)
643 {
644 return platform_driver_register(&clk_en7523_drv);
645 }
646
647 arch_initcall(clk_en7523_init);
Kernel DRM miscellaneous fixes and cross-tree changes