drivers/clk/mediatek/clk-mt7988-topckgen.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2023 MediaTek Inc.
   4  * Author: Sam Shih <sam.shih@mediatek.com>
   5  * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
   6  */
   7
   8 #include <linux/clk-provider.h>
   9 #include <linux/of.h>
  10 #include <linux/of_address.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13 #include "clk-mtk.h"
  14 #include "clk-gate.h"
  15 #include "clk-mux.h"
  16 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
  17
  18 static DEFINE_SPINLOCK(mt7988_clk_lock);
  19
  20 static const struct mtk_fixed_clk top_fixed_clks[] = {
  21         FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
  22 };
  23
  24 static const struct mtk_fixed_factor top_divs[] = {
  25         FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
  26         FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
  27         FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
  28         FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2),
  29         FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2),
  30         FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4),
  31         FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8),
  32         FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16),
  33         FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
  34         FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15),
  35         FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
  36         FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12),
  37         FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8),
  38         FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
  39         FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4),
  40         FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5),
  41         FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10),
  42         FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20),
  43         FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8),
  44         FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16),
  45         FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32),
  46         FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64),
  47         FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128),
  48         FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2),
  49         FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4),
  50         FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16),
  51         FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32),
  52         FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6),
  53         FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8),
  54 };
  55
  56 static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2", "mmpll_d2" };
  57 static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5", "net1pll_d5_d2" };
  58 static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll", "mmpll" };
  59 static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4", "net1pll_d5" };
  60 static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" };
  61 static const char *const netsys_mcu_parents[] = { "top_xtal",   "net2pll",    "mmpll",
  62                                                   "net1pll_d4", "net1pll_d5", "mpll" };
  63 static const char *const eip197_parents[] = { "top_xtal", "netsyspll",  "net2pll",
  64                                               "mmpll",    "net1pll_d4", "net1pll_d5" };
  65 static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" };
  66 static const char *const uart_parents[] = { "top_xtal", "mpll_d8", "mpll_d8_d2" };
  67 static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2", "mmpll_d4" };
  68 static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll",  "mmpll_d2",
  69                                                  "mpll_d2",  "mmpll_d4", "net1pll_d8_d2" };
  70 static const char *const spi_parents[] = { "top_xtal",      "mpll_d2",      "mmpll_d4",
  71                                            "net1pll_d8_d2", "net2pll_d6",   "net1pll_d5_d4",
  72                                            "mpll_d4",       "net1pll_d8_d4" };
  73 static const char *const nfi1x_parents[] = { "top_xtal", "mmpll_d4", "net1pll_d8_d2", "net2pll_d6",
  74                                              "mpll_d4",  "mmpll_d8", "net1pll_d8_d4", "mpll_d8" };
  75 static const char *const spinfi_parents[] = { "top_xtal_d2", "top_xtal", "net1pll_d5_d4",
  76                                               "mpll_d4",     "mmpll_d8", "net1pll_d8_d4",
  77                                               "mmpll_d6_d2", "mpll_d8" };
  78 static const char *const pwm_parents[] = { "top_xtal", "net1pll_d8_d2", "net1pll_d5_d4",
  79                                            "mpll_d4",  "mpll_d8_d2",    "top_rtc_32k" };
  80 static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4", "mpll_d4",
  81                                            "net1pll_d8_d4" };
  82 static const char *const pcie_mbist_250m_parents[] = { "top_xtal", "net1pll_d5_d2" };
  83 static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6", "mmpll_d8",
  84                                                    "mpll_d8_d2", "top_rtc_32k" };
  85 static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" };
  86 static const char *const aud_parents[] = { "top_xtal", "apll2" };
  87 static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" };
  88 static const char *const aud_l_parents[] = { "top_xtal", "apll2", "mpll_d8_d2" };
  89 static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" };
  90 static const char *const usxgmii_sbus_0_parents[] = { "top_xtal", "net1pll_d8_d4" };
  91 static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" };
  92 static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" };
  93 static const char *const eth_refck_50m_parents[] = { "top_xtal", "net2pll_d4_d4" };
  94 static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" };
  95 static const char *const eth_xgmii_parents[] = { "top_xtal_d2", "net1pll_d8_d8", "net1pll_d8_d16" };
  96 static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5", "net2pll_d2" };
  97 static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" };
  98 static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2", "wedmcupll" };
  99 static const char *const da_xtp_glb_p0_parents[] = { "top_xtal", "net2pll_d8" };
 100 static const char *const mcusys_backup_625m_parents[] = { "top_xtal", "net1pll_d4" };
 101 static const char *const macsec_parents[] = { "top_xtal", "sgmpll", "net1pll_d8" };
 102 static const char *const netsys_tops_400m_parents[] = { "top_xtal", "net2pll_d2" };
 103 static const char *const eth_mii_parents[] = { "top_xtal_d2", "net2pll_d4_d8" };
 104
 105 static const struct mtk_mux top_muxes[] = {
 106         /* CLK_CFG_0 */
 107         MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x000, 0x004, 0x008,
 108                              0, 2, 7, 0x1c0, 0),
 109         MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, 0x000,
 110                              0x004, 0x008, 8, 2, 15, 0x1C0, 1),
 111         MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x000,
 112                              0x004, 0x008, 16, 2, 23, 0x1C0, 2),
 113         MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, 0x000,
 114                              0x004, 0x008, 24, 2, 31, 0x1C0, 3),
 115         /* CLK_CFG_1 */
 116         MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x010, 0x014,
 117                              0x018, 0, 1, 7, 0x1C0, 4),
 118         MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, 0x010,
 119                              0x014, 0x018, 8, 3, 15, 0x1C0, 5),
 120         MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel", netsys_mcu_parents,
 121                              0x010, 0x014, 0x018, 16, 3, 23, 0x1C0, 6),
 122         MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x010, 0x014, 0x018,
 123                              24, 3, 31, 0x1c0, 7),
 124         /* CLK_CFG_2 */
 125         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x020,
 126                                    0x024, 0x028, 0, 1, 7, 0x1C0, 8, CLK_IS_CRITICAL),
 127         MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020, 0x024, 0x028, 8, 2,
 128                              15, 0x1c0, 9),
 129         MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020,
 130                              0x024, 0x028, 16, 2, 23, 0x1C0, 10),
 131         MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x020,
 132                              0x024, 0x028, 24, 3, 31, 0x1C0, 11),
 133         /* CLK_CFG_3 */
 134         MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030, 0x034, 0x038, 0, 3, 7,
 135                              0x1c0, 12),
 136         MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x030, 0x034, 0x038,
 137                              8, 3, 15, 0x1c0, 13),
 138         MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x030, 0x034, 0x038, 16,
 139                              3, 23, 0x1c0, 14),
 140         MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x030, 0x034, 0x038,
 141                              24, 3, 31, 0x1c0, 15),
 142         /* CLK_CFG_4 */
 143         MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040, 0x044, 0x048, 0, 3, 7,
 144                              0x1c0, 16),
 145         MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040, 0x044, 0x048, 8, 2, 15,
 146                              0x1c0, 17),
 147         MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
 148                              pcie_mbist_250m_parents, 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
 149         MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel", pextp_tl_ck_parents, 0x040,
 150                              0x044, 0x048, 24, 3, 31, 0x1C0, 19),
 151         /* CLK_CFG_5 */
 152         MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel", pextp_tl_ck_parents, 0x050,
 153                              0x054, 0x058, 0, 3, 7, 0x1C0, 20),
 154         MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel", pextp_tl_ck_parents, 0x050,
 155                              0x054, 0x058, 8, 3, 15, 0x1C0, 21),
 156         MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel", pextp_tl_ck_parents, 0x050,
 157                              0x054, 0x058, 16, 3, 23, 0x1C0, 22),
 158         MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x050, 0x054,
 159                              0x058, 24, 1, 31, 0x1C0, 23),
 160         /* CLK_CFG_6 */
 161         MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x060,
 162                              0x064, 0x068, 0, 1, 7, 0x1C0, 24),
 163         MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x060, 0x064,
 164                              0x068, 8, 1, 15, 0x1C0, 25),
 165         MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents, 0x060,
 166                              0x064, 0x068, 16, 1, 23, 0x1C0, 26),
 167         MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents, 0x060,
 168                              0x064, 0x068, 24, 1, 31, 0x1C0, 27),
 169         /* CLK_CFG_7 */
 170         MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel", usb_frmcnt_parents,
 171                              0x070, 0x074, 0x078, 0, 1, 7, 0x1C0, 28),
 172         MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070, 0x074, 0x078, 8, 1, 15,
 173                              0x1c0, 29),
 174         MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x070, 0x074, 0x078, 16,
 175                              1, 23, 0x1c0, 30),
 176         MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074, 0x078, 24,
 177                              2, 31, 0x1c4, 0),
 178         /* CLK_CFG_8 */
 179         MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x080, 0x084, 0x088,
 180                              0, 1, 7, 0x1c4, 1),
 181         MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x080, 0x084, 0x088,
 182                              8, 1, 15, 0x1c4, 2),
 183         MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x080, 0x084,
 184                              0x088, 16, 1, 23, 0x1c4, 3),
 185         MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
 186                              usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24, 1, 31, 0x1C4, 4),
 187         /* CLK_CFG_9 */
 188         MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
 189                              usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5),
 190         MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x090, 0x094, 0x098, 8,
 191                              1, 15, 0x1c4, 6),
 192         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents,
 193                                    0x090, 0x094, 0x098, 16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL),
 194         MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x090, 0x094, 0x098, 24,
 195                              1, 31, 0x1c4, 8),
 196         /* CLK_CFG_10 */
 197         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents,
 198                                    0x0a0, 0x0a4, 0x0a8, 0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL),
 199         MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents,
 200                              0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x1C4, 10),
 201         MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents,
 202                              0x0a0, 0x0a4, 0x0a8, 16, 1, 23, 0x1C4, 11),
 203         /* CLK_CFG_11 */
 204         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0x0a0,
 205                                    0x0a4, 0x0a8, 24, 1, 31, 0x1C4, 12, CLK_IS_CRITICAL),
 206         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x0b0, 0x0b4,
 207                                    0x0b8, 0, 1, 7, 0x1c4, 13, CLK_IS_CRITICAL),
 208         MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", eth_refck_50m_parents,
 209                              0x0b0, 0x0b4, 0x0b8, 8, 1, 15, 0x1C4, 14),
 210         MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", eth_sys_200m_parents,
 211                              0x0b0, 0x0b4, 0x0b8, 16, 1, 23, 0x1C4, 15),
 212         MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents, 0x0b0,
 213                              0x0b4, 0x0b8, 24, 1, 31, 0x1C4, 16),
 214         /* CLK_CFG_12 */
 215         MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0x0c0,
 216                              0x0c4, 0x0c8, 0, 2, 7, 0x1C4, 17),
 217         MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0x0c0, 0x0c4,
 218                              0x0c8, 8, 2, 15, 0x1C4, 18),
 219         MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0x0c0, 0x0c4,
 220                              0x0c8, 16, 1, 23, 0x1C4, 19),
 221         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0x0c0, 0x0c4,
 222                                    0x0c8, 24, 1, 31, 0x1C4, 20, CLK_IS_CRITICAL),
 223         /* CLK_CFG_13 */
 224         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
 225                                    0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x1C4, 21, CLK_IS_CRITICAL),
 226         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
 227                                    0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL),
 228         MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0x0d0, 0x0d4,
 229                              0x0d8, 16, 1, 23, 0x1C4, 23),
 230         MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0x0d0, 0x0d4,
 231                              0x0d8, 24, 1, 31, 0x1C4, 24),
 232         /* CLK_CFG_14 */
 233         MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0x0e0, 0x0e4,
 234                              0x0e8, 0, 1, 7, 0x1C4, 25),
 235         MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0x0e0, 0x0e4,
 236                              0x0e8, 8, 1, 15, 0x1C4, 26),
 237         MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", da_xtp_glb_p0_parents,
 238                              0x0e0, 0x0e4, 0x0e8, 16, 1, 23, 0x1C4, 27),
 239         MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", da_xtp_glb_p0_parents,
 240                              0x0e0, 0x0e4, 0x0e8, 24, 1, 31, 0x1C4, 28),
 241         /* CLK_CFG_15 */
 242         MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel", da_xtp_glb_p0_parents,
 243                              0x0f0, 0x0f4, 0x0f8, 0, 1, 7, 0x1C4, 29),
 244         MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel", da_xtp_glb_p0_parents,
 245                              0x0f0, 0x0f4, 0x0f8, 8, 1, 15, 0x1C4, 30),
 246         MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0, 0x0f4, 0x0f8, 16, 1,
 247                              23, 0x1c8, 0),
 248         MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1,
 249                              31, 0x1C8, 1),
 250         /* CLK_CFG_16 */
 251         MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x0100, 0x104, 0x108,
 252                              0, 1, 7, 0x1c8, 2),
 253         MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents, 0x0100,
 254                              0x104, 0x108, 8, 1, 15, 0x1C8, 3),
 255         MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel",
 256                              mcusys_backup_625m_parents, 0x0100, 0x104, 0x108, 16, 1, 23, 0x1C8, 4),
 257         MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel",
 258                              pcie_mbist_250m_parents, 0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5),
 259         /* CLK_CFG_17 */
 260         MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x0110, 0x114, 0x118,
 261                              0, 2, 7, 0x1c8, 6),
 262         MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel",
 263                              netsys_tops_400m_parents, 0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7),
 264         MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel",
 265                              pcie_mbist_250m_parents, 0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8),
 266         MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents, 0x0110,
 267                              0x114, 0x118, 24, 2, 31, 0x1C8, 9),
 268         /* CLK_CFG_18 */
 269         MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x0120, 0x124,
 270                              0x128, 0, 1, 7, 0x1c8, 10),
 271         MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents, 0x0120, 0x124, 0x128,
 272                              8, 2, 15, 0x1c8, 11),
 273 };
 274
 275 static const struct mtk_composite top_aud_divs[] = {
 276         DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420, 8, 8),
 277 };
 278
 279 static const struct mtk_clk_desc topck_desc = {
 280         .fixed_clks = top_fixed_clks,
 281         .num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
 282         .factor_clks = top_divs,
 283         .num_factor_clks = ARRAY_SIZE(top_divs),
 284         .mux_clks = top_muxes,
 285         .num_mux_clks = ARRAY_SIZE(top_muxes),
 286         .composite_clks = top_aud_divs,
 287         .num_composite_clks = ARRAY_SIZE(top_aud_divs),
 288         .clk_lock = &mt7988_clk_lock,
 289 };
 290
 291 static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b", "net1pll_d4" };
 292
 293 static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b", "net1pll_d4" };
 294
 295 static struct mtk_composite mcu_muxes[] = {
 296         /* bus_pll_divider_cfg */
 297         MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel", mcu_bus_div_parents, 0x7C0, 9, 2, -1,
 298                        CLK_IS_CRITICAL),
 299         /* mp2_pll_divider_cfg */
 300         MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel", mcu_arm_div_parents, 0x7A8, 9, 2, -1,
 301                        CLK_IS_CRITICAL),
 302 };
 303
 304 static const struct mtk_clk_desc mcusys_desc = {
 305         .composite_clks = mcu_muxes,
 306         .num_composite_clks = ARRAY_SIZE(mcu_muxes),
 307 };
 308
 309 static const struct of_device_id of_match_clk_mt7988_topckgen[] = {
 310         { .compatible = "mediatek,mt7988-topckgen", .data = &topck_desc },
 311         { .compatible = "mediatek,mt7988-mcusys", .data = &mcusys_desc },
 312         { /* sentinel */ }
 313 };
 314 MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_topckgen);
 315
 316 static struct platform_driver clk_mt7988_topckgen_drv = {
 317         .probe = mtk_clk_simple_probe,
 318         .remove = mtk_clk_simple_remove,
 319         .driver = {
 320                 .name = "clk-mt7988-topckgen",
 321                 .of_match_table = of_match_clk_mt7988_topckgen,
 322         },
 323 };
 324 module_platform_driver(clk_mt7988_topckgen_drv);
 325
 326 MODULE_DESCRIPTION("MediaTek MT7988 top clock generators driver");
 327 MODULE_LICENSE("GPL");