drivers/clk/samsung/clk-exynos4412-isp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2017 Samsung Electronics Co., Ltd.
   4  * Author: Marek Szyprowski <m.szyprowski@samsung.com>
   5  *
   6  * Common Clock Framework support for Exynos4412 ISP module.
   7 */
   8
   9 #include <dt-bindings/clock/exynos4.h>
  10 #include <linux/slab.h>
  11 #include <linux/clk.h>
  12 #include <linux/clk-provider.h>
  13 #include <linux/of.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pm_runtime.h>
  16
  17 #include "clk.h"
  18
  19 /* Exynos4x12 specific registers, which belong to ISP power domain */
  20 #define E4X12_DIV_ISP0          0x0300
  21 #define E4X12_DIV_ISP1          0x0304
  22 #define E4X12_GATE_ISP0         0x0800
  23 #define E4X12_GATE_ISP1         0x0804
  24
  25 /* NOTE: Must be equal to the last clock ID increased by one */
  26 #define CLKS_NR_ISP             (CLK_ISP_DIV_MCUISP1 + 1)
  27
  28 /*
  29  * Support for CMU save/restore across system suspends
  30  */
  31 static struct samsung_clk_reg_dump *exynos4x12_save_isp;
  32
  33 static const unsigned long exynos4x12_clk_isp_save[] __initconst = {
  34         E4X12_DIV_ISP0,
  35         E4X12_DIV_ISP1,
  36         E4X12_GATE_ISP0,
  37         E4X12_GATE_ISP1,
  38 };
  39
  40 static struct samsung_div_clock exynos4x12_isp_div_clks[] = {
  41         DIV(CLK_ISP_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3),
  42         DIV(CLK_ISP_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3),
  43         DIV(CLK_ISP_DIV_MCUISP0, "div_mcuisp0", "aclk400_mcuisp",
  44             E4X12_DIV_ISP1, 4, 3),
  45         DIV(CLK_ISP_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0",
  46             E4X12_DIV_ISP1, 8, 3),
  47         DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
  48 };
  49
  50 static struct samsung_gate_clock exynos4x12_isp_gate_clks[] = {
  51         GATE(CLK_ISP_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, 0, 0),
  52         GATE(CLK_ISP_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, 0, 0),
  53         GATE(CLK_ISP_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2, 0, 0),
  54         GATE(CLK_ISP_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, 0, 0),
  55         GATE(CLK_ISP_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, 0, 0),
  56         GATE(CLK_ISP_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, 0, 0),
  57         GATE(CLK_ISP_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, 0, 0),
  58         GATE(CLK_ISP_SMMU_ISP, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, 0, 0),
  59         GATE(CLK_ISP_SMMU_DRC, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, 0, 0),
  60         GATE(CLK_ISP_SMMU_FD, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, 0, 0),
  61         GATE(CLK_ISP_SMMU_LITE0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
  62              0, 0),
  63         GATE(CLK_ISP_SMMU_LITE1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
  64              0, 0),
  65         GATE(CLK_ISP_PPMUISPMX, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
  66              0, 0),
  67         GATE(CLK_ISP_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
  68              0, 0),
  69         GATE(CLK_ISP_MCUCTL_ISP, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
  70              0, 0),
  71         GATE(CLK_ISP_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
  72              0, 0),
  73         GATE(CLK_ISP_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
  74              0, 0),
  75         GATE(CLK_ISP_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
  76              0, 0),
  77         GATE(CLK_ISP_MTCADC_ISP, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
  78              0, 0),
  79         GATE(CLK_ISP_PWM_ISP, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, 0, 0),
  80         GATE(CLK_ISP_WDT_ISP, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, 0, 0),
  81         GATE(CLK_ISP_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
  82              0, 0),
  83         GATE(CLK_ISP_ASYNCAXIM, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
  84              0, 0),
  85         GATE(CLK_ISP_SMMU_ISPCX, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
  86              0, 0),
  87         GATE(CLK_ISP_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
  88              0, 0),
  89         GATE(CLK_ISP_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
  90              0, 0),
  91 };
  92
  93 static int __maybe_unused exynos4x12_isp_clk_suspend(struct device *dev)
  94 {
  95         struct samsung_clk_provider *ctx = dev_get_drvdata(dev);
  96
  97         samsung_clk_save(ctx->reg_base, exynos4x12_save_isp,
  98                          ARRAY_SIZE(exynos4x12_clk_isp_save));
  99         return 0;
 100 }
 101
 102 static int __maybe_unused exynos4x12_isp_clk_resume(struct device *dev)
 103 {
 104         struct samsung_clk_provider *ctx = dev_get_drvdata(dev);
 105
 106         samsung_clk_restore(ctx->reg_base, exynos4x12_save_isp,
 107                             ARRAY_SIZE(exynos4x12_clk_isp_save));
 108         return 0;
 109 }
 110
 111 static int __init exynos4x12_isp_clk_probe(struct platform_device *pdev)
 112 {
 113         struct samsung_clk_provider *ctx;
 114         struct device *dev = &pdev->dev;
 115         struct device_node *np = dev->of_node;
 116         void __iomem *reg_base;
 117
 118         reg_base = devm_platform_ioremap_resource(pdev, 0);
 119         if (IS_ERR(reg_base))
 120                 return PTR_ERR(reg_base);
 121
 122         exynos4x12_save_isp = samsung_clk_alloc_reg_dump(exynos4x12_clk_isp_save,
 123                                         ARRAY_SIZE(exynos4x12_clk_isp_save));
 124         if (!exynos4x12_save_isp)
 125                 return -ENOMEM;
 126
 127         ctx = samsung_clk_init(dev, reg_base, CLKS_NR_ISP);
 128
 129         platform_set_drvdata(pdev, ctx);
 130
 131         pm_runtime_set_active(dev);
 132         pm_runtime_enable(dev);
 133         pm_runtime_get_sync(dev);
 134
 135         samsung_clk_register_div(ctx, exynos4x12_isp_div_clks,
 136                                  ARRAY_SIZE(exynos4x12_isp_div_clks));
 137         samsung_clk_register_gate(ctx, exynos4x12_isp_gate_clks,
 138                                   ARRAY_SIZE(exynos4x12_isp_gate_clks));
 139
 140         samsung_clk_of_add_provider(np, ctx);
 141         pm_runtime_put(dev);
 142
 143         return 0;
 144 }
 145
 146 static const struct of_device_id exynos4x12_isp_clk_of_match[] = {
 147         { .compatible = "samsung,exynos4412-isp-clock", },
 148         { },
 149 };
 150
 151 static const struct dev_pm_ops exynos4x12_isp_pm_ops = {
 152         SET_RUNTIME_PM_OPS(exynos4x12_isp_clk_suspend,
 153                            exynos4x12_isp_clk_resume, NULL)
 154         SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 155                                      pm_runtime_force_resume)
 156 };
 157
 158 static struct platform_driver exynos4x12_isp_clk_driver __refdata = {
 159         .driver = {
 160                 .name = "exynos4x12-isp-clk",
 161                 .of_match_table = exynos4x12_isp_clk_of_match,
 162                 .suppress_bind_attrs = true,
 163                 .pm = &exynos4x12_isp_pm_ops,
 164         },
 165         .probe = exynos4x12_isp_clk_probe,
 166 };
 167
 168 static int __init exynos4x12_isp_clk_init(void)
 169 {
 170         return platform_driver_register(&exynos4x12_isp_clk_driver);
 171 }
 172 core_initcall(exynos4x12_isp_clk_init);