1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 ST Microelectronics
4 * Viresh Kumar <vireshk@kernel.org>
6 * General Purpose Timer Synthesizer clock implementation
9 #define pr_fmt(fmt) "clk-gpt-synth: " fmt
11 #include <linux/clk-provider.h>
12 #include <linux/slab.h>
14 #include <linux/err.h>
17 #define GPT_MSCALE_MASK 0xFFF
18 #define GPT_NSCALE_SHIFT 12
19 #define GPT_NSCALE_MASK 0xF
22 * DOC: General Purpose Timer Synthesizer clock
24 * Calculates gpt synth clk rate for different values of mscale and nscale
26 * Fout= Fin/((2 ^ (N+1)) * (M+1))
29 #define to_clk_gpt(_hw) container_of(_hw, struct clk_gpt, hw)
31 static unsigned long gpt_calc_rate(struct clk_hw
*hw
, unsigned long prate
,
34 struct clk_gpt
*gpt
= to_clk_gpt(hw
);
35 struct gpt_rate_tbl
*rtbl
= gpt
->rtbl
;
37 prate
/= ((1 << (rtbl
[index
].nscale
+ 1)) * (rtbl
[index
].mscale
+ 1));
42 static long clk_gpt_round_rate(struct clk_hw
*hw
, unsigned long drate
,
45 struct clk_gpt
*gpt
= to_clk_gpt(hw
);
48 return clk_round_rate_index(hw
, drate
, *prate
, gpt_calc_rate
,
49 gpt
->rtbl_cnt
, &unused
);
52 static unsigned long clk_gpt_recalc_rate(struct clk_hw
*hw
,
53 unsigned long parent_rate
)
55 struct clk_gpt
*gpt
= to_clk_gpt(hw
);
56 unsigned long flags
= 0;
57 unsigned int div
= 1, val
;
60 spin_lock_irqsave(gpt
->lock
, flags
);
62 val
= readl_relaxed(gpt
->reg
);
65 spin_unlock_irqrestore(gpt
->lock
, flags
);
67 div
+= val
& GPT_MSCALE_MASK
;
68 div
*= 1 << (((val
>> GPT_NSCALE_SHIFT
) & GPT_NSCALE_MASK
) + 1);
73 return parent_rate
/ div
;
76 /* Configures new clock rate of gpt */
77 static int clk_gpt_set_rate(struct clk_hw
*hw
, unsigned long drate
,
80 struct clk_gpt
*gpt
= to_clk_gpt(hw
);
81 struct gpt_rate_tbl
*rtbl
= gpt
->rtbl
;
82 unsigned long flags
= 0, val
;
85 clk_round_rate_index(hw
, drate
, prate
, gpt_calc_rate
, gpt
->rtbl_cnt
,
89 spin_lock_irqsave(gpt
->lock
, flags
);
91 val
= readl(gpt
->reg
) & ~GPT_MSCALE_MASK
;
92 val
&= ~(GPT_NSCALE_MASK
<< GPT_NSCALE_SHIFT
);
94 val
|= rtbl
[i
].mscale
& GPT_MSCALE_MASK
;
95 val
|= (rtbl
[i
].nscale
& GPT_NSCALE_MASK
) << GPT_NSCALE_SHIFT
;
97 writel_relaxed(val
, gpt
->reg
);
100 spin_unlock_irqrestore(gpt
->lock
, flags
);
105 static const struct clk_ops clk_gpt_ops
= {
106 .recalc_rate
= clk_gpt_recalc_rate
,
107 .round_rate
= clk_gpt_round_rate
,
108 .set_rate
= clk_gpt_set_rate
,
111 struct clk
*clk_register_gpt(const char *name
, const char *parent_name
, unsigned
112 long flags
, void __iomem
*reg
, struct gpt_rate_tbl
*rtbl
, u8
113 rtbl_cnt
, spinlock_t
*lock
)
115 struct clk_init_data init
;
119 if (!name
|| !parent_name
|| !reg
|| !rtbl
|| !rtbl_cnt
) {
120 pr_err("Invalid arguments passed\n");
121 return ERR_PTR(-EINVAL
);
124 gpt
= kzalloc(sizeof(*gpt
), GFP_KERNEL
);
126 return ERR_PTR(-ENOMEM
);
128 /* struct clk_gpt assignments */
131 gpt
->rtbl_cnt
= rtbl_cnt
;
133 gpt
->hw
.init
= &init
;
136 init
.ops
= &clk_gpt_ops
;
138 init
.parent_names
= &parent_name
;
139 init
.num_parents
= 1;
141 clk
= clk_register(NULL
, &gpt
->hw
);
142 if (!IS_ERR_OR_NULL(clk
))
145 pr_err("clk register failed\n");