drivers/clk/spear/clk.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Clock framework definitions for SPEAr platform
   4  *
   5  * Copyright (C) 2012 ST Microelectronics
   6  * Viresh Kumar <vireshk@kernel.org>
   7  */
   8
   9 #ifndef __SPEAR_CLK_H
  10 #define __SPEAR_CLK_H
  11
  12 #include <linux/clk-provider.h>
  13 #include <linux/spinlock_types.h>
  14 #include <linux/types.h>
  15
  16 /* Auxiliary Synth clk */
  17 /* Default masks */
  18 #define AUX_EQ_SEL_SHIFT        30
  19 #define AUX_EQ_SEL_MASK         1
  20 #define AUX_EQ1_SEL             0
  21 #define AUX_EQ2_SEL             1
  22 #define AUX_XSCALE_SHIFT        16
  23 #define AUX_XSCALE_MASK         0xFFF
  24 #define AUX_YSCALE_SHIFT        0
  25 #define AUX_YSCALE_MASK         0xFFF
  26 #define AUX_SYNT_ENB            31
  27
  28 struct aux_clk_masks {
  29         u32 eq_sel_mask;
  30         u32 eq_sel_shift;
  31         u32 eq1_mask;
  32         u32 eq2_mask;
  33         u32 xscale_sel_mask;
  34         u32 xscale_sel_shift;
  35         u32 yscale_sel_mask;
  36         u32 yscale_sel_shift;
  37         u32 enable_bit;
  38 };
  39
  40 struct aux_rate_tbl {
  41         u16 xscale;
  42         u16 yscale;
  43         u8 eq;
  44 };
  45
  46 struct clk_aux {
  47         struct                  clk_hw hw;
  48         void __iomem            *reg;
  49         const struct aux_clk_masks *masks;
  50         struct aux_rate_tbl     *rtbl;
  51         u8                      rtbl_cnt;
  52         spinlock_t              *lock;
  53 };
  54
  55 /* Fractional Synth clk */
  56 struct frac_rate_tbl {
  57         u32 div;
  58 };
  59
  60 struct clk_frac {
  61         struct                  clk_hw hw;
  62         void __iomem            *reg;
  63         struct frac_rate_tbl    *rtbl;
  64         u8                      rtbl_cnt;
  65         spinlock_t              *lock;
  66 };
  67
  68 /* GPT clk */
  69 struct gpt_rate_tbl {
  70         u16 mscale;
  71         u16 nscale;
  72 };
  73
  74 struct clk_gpt {
  75         struct                  clk_hw hw;
  76         void __iomem            *reg;
  77         struct gpt_rate_tbl     *rtbl;
  78         u8                      rtbl_cnt;
  79         spinlock_t              *lock;
  80 };
  81
  82 /* VCO-PLL clk */
  83 struct pll_rate_tbl {
  84         u8 mode;
  85         u16 m;
  86         u8 n;
  87         u8 p;
  88 };
  89
  90 struct clk_vco {
  91         struct                  clk_hw hw;
  92         void __iomem            *mode_reg;
  93         void __iomem            *cfg_reg;
  94         struct pll_rate_tbl     *rtbl;
  95         u8                      rtbl_cnt;
  96         spinlock_t              *lock;
  97 };
  98
  99 struct clk_pll {
 100         struct                  clk_hw hw;
 101         struct clk_vco          *vco;
 102         const char              *parent[1];
 103         spinlock_t              *lock;
 104 };
 105
 106 typedef unsigned long (*clk_calc_rate)(struct clk_hw *hw, unsigned long prate,
 107                 int index);
 108
 109 /* clk register routines */
 110 struct clk *clk_register_aux(const char *aux_name, const char *gate_name,
 111                 const char *parent_name, unsigned long flags, void __iomem *reg,
 112                 const struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl,
 113                 u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk);
 114 struct clk *clk_register_frac(const char *name, const char *parent_name,
 115                 unsigned long flags, void __iomem *reg,
 116                 struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock);
 117 struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned
 118                 long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8
 119                 rtbl_cnt, spinlock_t *lock);
 120 struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name,
 121                 const char *vco_gate_name, const char *parent_name,
 122                 unsigned long flags, void __iomem *mode_reg, void __iomem
 123                 *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt,
 124                 spinlock_t *lock, struct clk **pll_clk,
 125                 struct clk **vco_gate_clk);
 126
 127 long clk_round_rate_index(struct clk_hw *hw, unsigned long drate,
 128                 unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt,
 129                 int *index);
 130
 131 #endif /* __SPEAR_CLK_H */