drivers/clk/tegra/clk.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2         /*
   3  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
   4  */
   5
   6 #ifndef __TEGRA_CLK_H
   7 #define __TEGRA_CLK_H
   8
   9 #include <linux/clk-provider.h>
  10 #include <linux/clkdev.h>
  11 #include <linux/delay.h>
  12
  13 #define CLK_OUT_ENB_L                   0x010
  14 #define CLK_OUT_ENB_H                   0x014
  15 #define CLK_OUT_ENB_U                   0x018
  16 #define CLK_OUT_ENB_V                   0x360
  17 #define CLK_OUT_ENB_W                   0x364
  18 #define CLK_OUT_ENB_X                   0x280
  19 #define CLK_OUT_ENB_Y                   0x298
  20 #define CLK_ENB_PLLP_OUT_CPU            BIT(31)
  21 #define CLK_OUT_ENB_SET_L               0x320
  22 #define CLK_OUT_ENB_CLR_L               0x324
  23 #define CLK_OUT_ENB_SET_H               0x328
  24 #define CLK_OUT_ENB_CLR_H               0x32c
  25 #define CLK_OUT_ENB_SET_U               0x330
  26 #define CLK_OUT_ENB_CLR_U               0x334
  27 #define CLK_OUT_ENB_SET_V               0x440
  28 #define CLK_OUT_ENB_CLR_V               0x444
  29 #define CLK_OUT_ENB_SET_W               0x448
  30 #define CLK_OUT_ENB_CLR_W               0x44c
  31 #define CLK_OUT_ENB_SET_X               0x284
  32 #define CLK_OUT_ENB_CLR_X               0x288
  33 #define CLK_OUT_ENB_SET_Y               0x29c
  34 #define CLK_OUT_ENB_CLR_Y               0x2a0
  35
  36 #define RST_DEVICES_L                   0x004
  37 #define RST_DEVICES_H                   0x008
  38 #define RST_DEVICES_U                   0x00C
  39 #define RST_DEVICES_V                   0x358
  40 #define RST_DEVICES_W                   0x35C
  41 #define RST_DEVICES_X                   0x28C
  42 #define RST_DEVICES_Y                   0x2a4
  43 #define RST_DEVICES_SET_L               0x300
  44 #define RST_DEVICES_CLR_L               0x304
  45 #define RST_DEVICES_SET_H               0x308
  46 #define RST_DEVICES_CLR_H               0x30c
  47 #define RST_DEVICES_SET_U               0x310
  48 #define RST_DEVICES_CLR_U               0x314
  49 #define RST_DEVICES_SET_V               0x430
  50 #define RST_DEVICES_CLR_V               0x434
  51 #define RST_DEVICES_SET_W               0x438
  52 #define RST_DEVICES_CLR_W               0x43c
  53 #define RST_DEVICES_SET_X               0x290
  54 #define RST_DEVICES_CLR_X               0x294
  55 #define RST_DEVICES_SET_Y               0x2a8
  56 #define RST_DEVICES_CLR_Y               0x2ac
  57
  58 /*
  59  * Tegra CLK_OUT_ENB registers have some undefined bits which are not used and
  60  * any accidental write of 1 to these bits can cause PSLVERR.
  61  * So below are the valid mask defines for each CLK_OUT_ENB register used to
  62  * turn ON only the valid clocks.
  63  */
  64 #define TEGRA210_CLK_ENB_VLD_MSK_L      0xdcd7dff9
  65 #define TEGRA210_CLK_ENB_VLD_MSK_H      0x87d1f3e7
  66 #define TEGRA210_CLK_ENB_VLD_MSK_U      0xf3fed3fa
  67 #define TEGRA210_CLK_ENB_VLD_MSK_V      0xffc18cfb
  68 #define TEGRA210_CLK_ENB_VLD_MSK_W      0x793fb7ff
  69 #define TEGRA210_CLK_ENB_VLD_MSK_X      0x3fe66fff
  70 #define TEGRA210_CLK_ENB_VLD_MSK_Y      0xfc1fc7ff
  71
  72 /**
  73  * struct tegra_clk_sync_source - external clock source from codec
  74  *
  75  * @hw: handle between common and hardware-specific interfaces
  76  * @rate: input frequency from source
  77  * @max_rate: max rate allowed
  78  */
  79 struct tegra_clk_sync_source {
  80         struct          clk_hw hw;
  81         unsigned long   rate;
  82         unsigned long   max_rate;
  83 };
  84
  85 #define to_clk_sync_source(_hw)                                 \
  86         container_of(_hw, struct tegra_clk_sync_source, hw)
  87
  88 extern const struct clk_ops tegra_clk_sync_source_ops;
  89 extern int *periph_clk_enb_refcnt;
  90
  91 struct clk *tegra_clk_register_sync_source(const char *name,
  92                                            unsigned long max_rate);
  93
  94 /**
  95  * struct tegra_clk_frac_div - fractional divider clock
  96  *
  97  * @hw:         handle between common and hardware-specific interfaces
  98  * @reg:        register containing divider
  99  * @flags:      hardware-specific flags
 100  * @shift:      shift to the divider bit field
 101  * @width:      width of the divider bit field
 102  * @frac_width: width of the fractional bit field
 103  * @lock:       register lock
 104  *
 105  * Flags:
 106  * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
 107  * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
 108  *      flag indicates that this divider is for fixed rate PLL.
 109  * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when
 110  *      fraction bit is set. This flags indicates to calculate divider for which
 111  *      fracton bit will be zero.
 112  * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is
 113  *      set when divider value is not 0. This flags indicates that the divider
 114  *      is for UART module.
 115  */
 116 struct tegra_clk_frac_div {
 117         struct clk_hw   hw;
 118         void __iomem    *reg;
 119         u8              flags;
 120         u8              shift;
 121         u8              width;
 122         u8              frac_width;
 123         spinlock_t      *lock;
 124 };
 125
 126 #define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw)
 127
 128 #define TEGRA_DIVIDER_ROUND_UP BIT(0)
 129 #define TEGRA_DIVIDER_FIXED BIT(1)
 130 #define TEGRA_DIVIDER_INT BIT(2)
 131 #define TEGRA_DIVIDER_UART BIT(3)
 132
 133 extern const struct clk_ops tegra_clk_frac_div_ops;
 134 struct clk *tegra_clk_register_divider(const char *name,
 135                 const char *parent_name, void __iomem *reg,
 136                 unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width,
 137                 u8 frac_width, spinlock_t *lock);
 138 struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
 139                                   void __iomem *reg, spinlock_t *lock);
 140
 141 /*
 142  * Tegra PLL:
 143  *
 144  * In general, there are 3 requirements for each PLL
 145  * that SW needs to be comply with.
 146  * (1) Input frequency range (REF).
 147  * (2) Comparison frequency range (CF). CF = REF/DIVM.
 148  * (3) VCO frequency range (VCO).  VCO = CF * DIVN.
 149  *
 150  * The final PLL output frequency (FO) = VCO >> DIVP.
 151  */
 152
 153 /**
 154  * struct tegra_clk_pll_freq_table - PLL frequecy table
 155  *
 156  * @input_rate:         input rate from source
 157  * @output_rate:        output rate from PLL for the input rate
 158  * @n:                  feedback divider
 159  * @m:                  input divider
 160  * @p:                  post divider
 161  * @cpcon:              charge pump current
 162  * @sdm_data:           fraction divider setting (0 = disabled)
 163  */
 164 struct tegra_clk_pll_freq_table {
 165         unsigned long   input_rate;
 166         unsigned long   output_rate;
 167         u32             n;
 168         u32             m;
 169         u8              p;
 170         u8              cpcon;
 171         u16             sdm_data;
 172 };
 173
 174 /**
 175  * struct pdiv_map - map post divider to hw value
 176  *
 177  * @pdiv:               post divider
 178  * @hw_val:             value to be written to the PLL hw
 179  */
 180 struct pdiv_map {
 181         u8 pdiv;
 182         u8 hw_val;
 183 };
 184
 185 /**
 186  * struct div_nmp - offset and width of m,n and p fields
 187  *
 188  * @divn_shift: shift to the feedback divider bit field
 189  * @divn_width: width of the feedback divider bit field
 190  * @divm_shift: shift to the input divider bit field
 191  * @divm_width: width of the input divider bit field
 192  * @divp_shift: shift to the post divider bit field
 193  * @divp_width: width of the post divider bit field
 194  * @override_divn_shift: shift to the feedback divider bitfield in override reg
 195  * @override_divm_shift: shift to the input divider bitfield in override reg
 196  * @override_divp_shift: shift to the post divider bitfield in override reg
 197  */
 198 struct div_nmp {
 199         u8              divn_shift;
 200         u8              divn_width;
 201         u8              divm_shift;
 202         u8              divm_width;
 203         u8              divp_shift;
 204         u8              divp_width;
 205         u8              override_divn_shift;
 206         u8              override_divm_shift;
 207         u8              override_divp_shift;
 208 };
 209
 210 #define MAX_PLL_MISC_REG_COUNT  6
 211
 212 struct tegra_clk_pll;
 213
 214 /**
 215  * struct tegra_clk_pll_params - PLL parameters
 216  *
 217  * @input_min:                  Minimum input frequency
 218  * @input_max:                  Maximum input frequency
 219  * @cf_min:                     Minimum comparison frequency
 220  * @cf_max:                     Maximum comparison frequency
 221  * @vco_min:                    Minimum VCO frequency
 222  * @vco_max:                    Maximum VCO frequency
 223  * @base_reg:                   PLL base reg offset
 224  * @misc_reg:                   PLL misc reg offset
 225  * @lock_reg:                   PLL lock reg offset
 226  * @lock_mask:                  Bitmask for PLL lock status
 227  * @lock_enable_bit_idx:        Bit index to enable PLL lock
 228  * @iddq_reg:                   PLL IDDQ register offset
 229  * @iddq_bit_idx:               Bit index to enable PLL IDDQ
 230  * @reset_reg:                  Register offset of where RESET bit is
 231  * @reset_bit_idx:              Shift of reset bit in reset_reg
 232  * @sdm_din_reg:                Register offset where SDM settings are
 233  * @sdm_din_mask:               Mask of SDM divider bits
 234  * @sdm_ctrl_reg:               Register offset where SDM enable is
 235  * @sdm_ctrl_en_mask:           Mask of SDM enable bit
 236  * @ssc_ctrl_reg:               Register offset where SSC settings are
 237  * @ssc_ctrl_en_mask:           Mask of SSC enable bit
 238  * @aux_reg:                    AUX register offset
 239  * @dyn_ramp_reg:               Dynamic ramp control register offset
 240  * @ext_misc_reg:               Miscellaneous control register offsets
 241  * @pmc_divnm_reg:              n, m divider PMC override register offset (PLLM)
 242  * @pmc_divp_reg:               p divider PMC override register offset (PLLM)
 243  * @flags:                      PLL flags
 244  * @stepa_shift:                Dynamic ramp step A field shift
 245  * @stepb_shift:                Dynamic ramp step B field shift
 246  * @lock_delay:                 Delay in us if PLL lock is not used
 247  * @max_p:                      maximum value for the p divider
 248  * @defaults_set:               Boolean signaling all reg defaults for PLL set.
 249  * @pdiv_tohw:                  mapping of p divider to register values
 250  * @div_nmp:                    offsets and widths on n, m and p fields
 251  * @freq_table:                 array of frequencies supported by PLL
 252  * @fixed_rate:                 PLL rate if it is fixed
 253  * @mdiv_default:               Default value for fixed mdiv for this PLL
 254  * @round_p_to_pdiv:            Callback used to round p to the closed pdiv
 255  * @set_gain:                   Callback to adjust N div for SDM enabled
 256  *                              PLL's based on fractional divider value.
 257  * @calc_rate:                  Callback used to change how out of table
 258  *                              rates (dividers and multipler) are calculated.
 259  * @adjust_vco:                 Callback to adjust the programming range of the
 260  *                              divider range (if SDM is present)
 261  * @set_defaults:               Callback which will try to initialize PLL
 262  *                              registers to sane default values. This is first
 263  *                              tried during PLL registration, but if the PLL
 264  *                              is already enabled, it will be done the first
 265  *                              time the rate is changed while the PLL is
 266  *                              disabled.
 267  * @dyn_ramp:                   Callback which can be used to define a custom
 268  *                              dynamic ramp function for a given PLL.
 269  * @pre_rate_change:            Callback which is invoked just before changing
 270  *                              PLL's rate.
 271  * @post_rate_change:           Callback which is invoked right after changing
 272  *                              PLL's rate.
 273  *
 274  * Flags:
 275  * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
 276  *     PLL locking. If not set it will use lock_delay value to wait.
 277  * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs
 278  *     to be programmed to change output frequency of the PLL.
 279  * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs
 280  *     to be programmed to change output frequency of the PLL.
 281  * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs
 282  *     to be programmed to change output frequency of the PLL.
 283  * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated
 284  *     that it is PLLU and invert post divider value.
 285  * TEGRA_PLLM - PLLM has additional override settings in PMC. This
 286  *     flag indicates that it is PLLM and use override settings.
 287  * TEGRA_PLL_FIXED - We are not supposed to change output frequency
 288  *     of some plls.
 289  * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
 290  * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
 291  *     base register.
 292  * TEGRA_PLL_BYPASS - PLL has bypass bit
 293  * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
 294  * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv
 295  *     it may be more accurate (especially if SDM present)
 296  * TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This
 297  *     flag indicated that it is PLLMB.
 298  * TEGRA_PLL_VCO_OUT - Used to indicate that the PLL has a VCO output
 299  */
 300 struct tegra_clk_pll_params {
 301         unsigned long   input_min;
 302         unsigned long   input_max;
 303         unsigned long   cf_min;
 304         unsigned long   cf_max;
 305         unsigned long   vco_min;
 306         unsigned long   vco_max;
 307
 308         u32             base_reg;
 309         u32             misc_reg;
 310         u32             lock_reg;
 311         u32             lock_mask;
 312         u32             lock_enable_bit_idx;
 313         u32             iddq_reg;
 314         u32             iddq_bit_idx;
 315         u32             reset_reg;
 316         u32             reset_bit_idx;
 317         u32             sdm_din_reg;
 318         u32             sdm_din_mask;
 319         u32             sdm_ctrl_reg;
 320         u32             sdm_ctrl_en_mask;
 321         u32             ssc_ctrl_reg;
 322         u32             ssc_ctrl_en_mask;
 323         u32             aux_reg;
 324         u32             dyn_ramp_reg;
 325         u32             ext_misc_reg[MAX_PLL_MISC_REG_COUNT];
 326         u32             pmc_divnm_reg;
 327         u32             pmc_divp_reg;
 328         u32             flags;
 329         int             stepa_shift;
 330         int             stepb_shift;
 331         int             lock_delay;
 332         int             max_p;
 333         bool            defaults_set;
 334         const struct pdiv_map *pdiv_tohw;
 335         struct div_nmp  *div_nmp;
 336         struct tegra_clk_pll_freq_table *freq_table;
 337         unsigned long   fixed_rate;
 338         u16             mdiv_default;
 339         u32     (*round_p_to_pdiv)(u32 p, u32 *pdiv);
 340         void    (*set_gain)(struct tegra_clk_pll_freq_table *cfg);
 341         int     (*calc_rate)(struct clk_hw *hw,
 342                         struct tegra_clk_pll_freq_table *cfg,
 343                         unsigned long rate, unsigned long parent_rate);
 344         unsigned long   (*adjust_vco)(struct tegra_clk_pll_params *pll_params,
 345                                 unsigned long parent_rate);
 346         void    (*set_defaults)(struct tegra_clk_pll *pll);
 347         int     (*dyn_ramp)(struct tegra_clk_pll *pll,
 348                         struct tegra_clk_pll_freq_table *cfg);
 349         int     (*pre_rate_change)(void);
 350         void    (*post_rate_change)(void);
 351 };
 352
 353 #define TEGRA_PLL_USE_LOCK BIT(0)
 354 #define TEGRA_PLL_HAS_CPCON BIT(1)
 355 #define TEGRA_PLL_SET_LFCON BIT(2)
 356 #define TEGRA_PLL_SET_DCCON BIT(3)
 357 #define TEGRA_PLLU BIT(4)
 358 #define TEGRA_PLLM BIT(5)
 359 #define TEGRA_PLL_FIXED BIT(6)
 360 #define TEGRA_PLLE_CONFIGURE BIT(7)
 361 #define TEGRA_PLL_LOCK_MISC BIT(8)
 362 #define TEGRA_PLL_BYPASS BIT(9)
 363 #define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)
 364 #define TEGRA_MDIV_NEW BIT(11)
 365 #define TEGRA_PLLMB BIT(12)
 366 #define TEGRA_PLL_VCO_OUT BIT(13)
 367
 368 /**
 369  * struct tegra_clk_pll - Tegra PLL clock
 370  *
 371  * @hw:         handle between common and hardware-specifix interfaces
 372  * @clk_base:   address of CAR controller
 373  * @pmc:        address of PMC, required to read override bits
 374  * @lock:       register lock
 375  * @params:     PLL parameters
 376  */
 377 struct tegra_clk_pll {
 378         struct clk_hw   hw;
 379         void __iomem    *clk_base;
 380         void __iomem    *pmc;
 381         spinlock_t      *lock;
 382         struct tegra_clk_pll_params     *params;
 383 };
 384
 385 #define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw)
 386
 387 /**
 388  * struct tegra_audio_clk_info - Tegra Audio Clk Information
 389  *
 390  * @name:       name for the audio pll
 391  * @pll_params: pll_params for audio pll
 392  * @clk_id:     clk_ids for the audio pll
 393  * @parent:     name of the parent of the audio pll
 394  */
 395 struct tegra_audio_clk_info {
 396         char *name;
 397         struct tegra_clk_pll_params *pll_params;
 398         int clk_id;
 399         char *parent;
 400 };
 401
 402 extern const struct clk_ops tegra_clk_pll_ops;
 403 extern const struct clk_ops tegra_clk_plle_ops;
 404 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
 405                 void __iomem *clk_base, void __iomem *pmc,
 406                 unsigned long flags, struct tegra_clk_pll_params *pll_params,
 407                 spinlock_t *lock);
 408
 409 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
 410                 void __iomem *clk_base, void __iomem *pmc,
 411                 unsigned long flags, struct tegra_clk_pll_params *pll_params,
 412                 spinlock_t *lock);
 413
 414 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
 415                             void __iomem *clk_base, void __iomem *pmc,
 416                             unsigned long flags,
 417                             struct tegra_clk_pll_params *pll_params,
 418                             spinlock_t *lock);
 419
 420 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
 421                            void __iomem *clk_base, void __iomem *pmc,
 422                            unsigned long flags,
 423                            struct tegra_clk_pll_params *pll_params,
 424                            spinlock_t *lock);
 425
 426 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
 427                            void __iomem *clk_base, void __iomem *pmc,
 428                            unsigned long flags,
 429                            struct tegra_clk_pll_params *pll_params,
 430                            spinlock_t *lock);
 431
 432 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
 433                            void __iomem *clk_base, void __iomem *pmc,
 434                            unsigned long flags,
 435                            struct tegra_clk_pll_params *pll_params,
 436                            spinlock_t *lock, unsigned long parent_rate);
 437
 438 struct clk *tegra_clk_register_pllre_tegra210(const char *name,
 439                            const char *parent_name, void __iomem *clk_base,
 440                            void __iomem *pmc, unsigned long flags,
 441                            struct tegra_clk_pll_params *pll_params,
 442                            spinlock_t *lock, unsigned long parent_rate);
 443
 444 struct clk *tegra_clk_register_plle_tegra114(const char *name,
 445                                 const char *parent_name,
 446                                 void __iomem *clk_base, unsigned long flags,
 447                                 struct tegra_clk_pll_params *pll_params,
 448                                 spinlock_t *lock);
 449
 450 struct clk *tegra_clk_register_plle_tegra210(const char *name,
 451                                 const char *parent_name,
 452                                 void __iomem *clk_base, unsigned long flags,
 453                                 struct tegra_clk_pll_params *pll_params,
 454                                 spinlock_t *lock);
 455
 456 struct clk *tegra_clk_register_pllc_tegra210(const char *name,
 457                                 const char *parent_name, void __iomem *clk_base,
 458                                 void __iomem *pmc, unsigned long flags,
 459                                 struct tegra_clk_pll_params *pll_params,
 460                                 spinlock_t *lock);
 461
 462 struct clk *tegra_clk_register_pllss_tegra210(const char *name,
 463                                 const char *parent_name, void __iomem *clk_base,
 464                                 unsigned long flags,
 465                                 struct tegra_clk_pll_params *pll_params,
 466                                 spinlock_t *lock);
 467
 468 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
 469                            void __iomem *clk_base, unsigned long flags,
 470                            struct tegra_clk_pll_params *pll_params,
 471                            spinlock_t *lock);
 472
 473 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
 474                            void __iomem *clk_base, void __iomem *pmc,
 475                            unsigned long flags,
 476                            struct tegra_clk_pll_params *pll_params,
 477                            spinlock_t *lock);
 478
 479 struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name,
 480                                 void __iomem *clk_base, unsigned long flags,
 481                                 struct tegra_clk_pll_params *pll_params,
 482                                 spinlock_t *lock);
 483
 484 struct clk *tegra_clk_register_pllu_tegra114(const char *name,
 485                                 const char *parent_name,
 486                                 void __iomem *clk_base, unsigned long flags,
 487                                 struct tegra_clk_pll_params *pll_params,
 488                                 spinlock_t *lock);
 489
 490 struct clk *tegra_clk_register_pllu_tegra210(const char *name,
 491                                 const char *parent_name,
 492                                 void __iomem *clk_base, unsigned long flags,
 493                                 struct tegra_clk_pll_params *pll_params,
 494                                 spinlock_t *lock);
 495
 496 /**
 497  * struct tegra_clk_pll_out - PLL divider down clock
 498  *
 499  * @hw:                 handle between common and hardware-specific interfaces
 500  * @reg:                register containing the PLL divider
 501  * @enb_bit_idx:        bit to enable/disable PLL divider
 502  * @rst_bit_idx:        bit to reset PLL divider
 503  * @lock:               register lock
 504  * @flags:              hardware-specific flags
 505  */
 506 struct tegra_clk_pll_out {
 507         struct clk_hw   hw;
 508         void __iomem    *reg;
 509         u8              enb_bit_idx;
 510         u8              rst_bit_idx;
 511         spinlock_t      *lock;
 512         u8              flags;
 513 };
 514
 515 #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw)
 516
 517 extern const struct clk_ops tegra_clk_pll_out_ops;
 518 struct clk *tegra_clk_register_pll_out(const char *name,
 519                 const char *parent_name, void __iomem *reg, u8 enb_bit_idx,
 520                 u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags,
 521                 spinlock_t *lock);
 522
 523 /**
 524  * struct tegra_clk_periph_regs -  Registers controlling peripheral clock
 525  *
 526  * @enb_reg:            read the enable status
 527  * @enb_set_reg:        write 1 to enable clock
 528  * @enb_clr_reg:        write 1 to disable clock
 529  * @rst_reg:            read the reset status
 530  * @rst_set_reg:        write 1 to assert the reset of peripheral
 531  * @rst_clr_reg:        write 1 to deassert the reset of peripheral
 532  */
 533 struct tegra_clk_periph_regs {
 534         u32 enb_reg;
 535         u32 enb_set_reg;
 536         u32 enb_clr_reg;
 537         u32 rst_reg;
 538         u32 rst_set_reg;
 539         u32 rst_clr_reg;
 540 };
 541
 542 /**
 543  * struct tegra_clk_periph_gate - peripheral gate clock
 544  *
 545  * @magic:              magic number to validate type
 546  * @hw:                 handle between common and hardware-specific interfaces
 547  * @clk_base:           address of CAR controller
 548  * @regs:               Registers to control the peripheral
 549  * @flags:              hardware-specific flags
 550  * @clk_num:            Clock number
 551  * @enable_refcnt:      array to maintain reference count of the clock
 552  *
 553  * Flags:
 554  * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed
 555  *     for this module.
 556  * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the
 557  *     bus to flush the write operation in apb bus. This flag indicates
 558  *     that this peripheral is in apb bus.
 559  * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug
 560  */
 561 struct tegra_clk_periph_gate {
 562         u32                     magic;
 563         struct clk_hw           hw;
 564         void __iomem            *clk_base;
 565         u8                      flags;
 566         int                     clk_num;
 567         int                     *enable_refcnt;
 568         const struct tegra_clk_periph_regs *regs;
 569 };
 570
 571 #define to_clk_periph_gate(_hw)                                 \
 572         container_of(_hw, struct tegra_clk_periph_gate, hw)
 573
 574 #define TEGRA_CLK_PERIPH_GATE_MAGIC 0x17760309
 575
 576 #define TEGRA_PERIPH_NO_RESET BIT(0)
 577 #define TEGRA_PERIPH_ON_APB BIT(2)
 578 #define TEGRA_PERIPH_WAR_1005168 BIT(3)
 579 #define TEGRA_PERIPH_NO_DIV BIT(4)
 580 #define TEGRA_PERIPH_NO_GATE BIT(5)
 581
 582 extern const struct clk_ops tegra_clk_periph_gate_ops;
 583 struct clk *tegra_clk_register_periph_gate(const char *name,
 584                 const char *parent_name, u8 gate_flags, void __iomem *clk_base,
 585                 unsigned long flags, int clk_num, int *enable_refcnt);
 586
 587 struct tegra_clk_periph_fixed {
 588         struct clk_hw hw;
 589         void __iomem *base;
 590         const struct tegra_clk_periph_regs *regs;
 591         unsigned int mul;
 592         unsigned int div;
 593         unsigned int num;
 594 };
 595
 596 struct clk *tegra_clk_register_periph_fixed(const char *name,
 597                                             const char *parent,
 598                                             unsigned long flags,
 599                                             void __iomem *base,
 600                                             unsigned int mul,
 601                                             unsigned int div,
 602                                             unsigned int num);
 603
 604 /**
 605  * struct clk-periph - peripheral clock
 606  *
 607  * @magic:      magic number to validate type
 608  * @hw:         handle between common and hardware-specific interfaces
 609  * @mux:        mux clock
 610  * @divider:    divider clock
 611  * @gate:       gate clock
 612  * @mux_ops:    mux clock ops
 613  * @div_ops:    divider clock ops
 614  * @gate_ops:   gate clock ops
 615  */
 616 struct tegra_clk_periph {
 617         u32                     magic;
 618         struct clk_hw           hw;
 619         struct clk_mux          mux;
 620         struct tegra_clk_frac_div       divider;
 621         struct tegra_clk_periph_gate    gate;
 622
 623         const struct clk_ops    *mux_ops;
 624         const struct clk_ops    *div_ops;
 625         const struct clk_ops    *gate_ops;
 626 };
 627
 628 #define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw)
 629
 630 #define TEGRA_CLK_PERIPH_MAGIC 0x18221223
 631
 632 extern const struct clk_ops tegra_clk_periph_ops;
 633 struct clk *tegra_clk_register_periph(const char *name,
 634                 const char * const *parent_names, int num_parents,
 635                 struct tegra_clk_periph *periph, void __iomem *clk_base,
 636                 u32 offset, unsigned long flags);
 637 struct clk *tegra_clk_register_periph_nodiv(const char *name,
 638                 const char * const *parent_names, int num_parents,
 639                 struct tegra_clk_periph *periph, void __iomem *clk_base,
 640                 u32 offset);
 641
 642 #define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags,             \
 643                          _div_shift, _div_width, _div_frac_width,       \
 644                          _div_flags, _clk_num,\
 645                          _gate_flags, _table, _lock)                    \
 646         {                                                               \
 647                 .mux = {                                                \
 648                         .flags = _mux_flags,                            \
 649                         .shift = _mux_shift,                            \
 650                         .mask = _mux_mask,                              \
 651                         .table = _table,                                \
 652                         .lock = _lock,                                  \
 653                 },                                                      \
 654                 .divider = {                                            \
 655                         .flags = _div_flags,                            \
 656                         .shift = _div_shift,                            \
 657                         .width = _div_width,                            \
 658                         .frac_width = _div_frac_width,                  \
 659                         .lock = _lock,                                  \
 660                 },                                                      \
 661                 .gate = {                                               \
 662                         .flags = _gate_flags,                           \
 663                         .clk_num = _clk_num,                            \
 664                 },                                                      \
 665                 .mux_ops = &clk_mux_ops,                                \
 666                 .div_ops = &tegra_clk_frac_div_ops,                     \
 667                 .gate_ops = &tegra_clk_periph_gate_ops,                 \
 668         }
 669
 670 struct tegra_periph_init_data {
 671         const char *name;
 672         int clk_id;
 673         union {
 674                 const char *const *parent_names;
 675                 const char *parent_name;
 676         } p;
 677         int num_parents;
 678         struct tegra_clk_periph periph;
 679         u32 offset;
 680         const char *con_id;
 681         const char *dev_id;
 682         unsigned long flags;
 683 };
 684
 685 #define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
 686                         _mux_shift, _mux_mask, _mux_flags, _div_shift,  \
 687                         _div_width, _div_frac_width, _div_flags,        \
 688                         _clk_num, _gate_flags, _clk_id, _table,         \
 689                         _flags, _lock) \
 690         {                                                               \
 691                 .name = _name,                                          \
 692                 .clk_id = _clk_id,                                      \
 693                 .p.parent_names = _parent_names,                        \
 694                 .num_parents = ARRAY_SIZE(_parent_names),               \
 695                 .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask,       \
 696                                            _mux_flags, _div_shift,      \
 697                                            _div_width, _div_frac_width, \
 698                                            _div_flags, _clk_num,        \
 699                                            _gate_flags, _table, _lock), \
 700                 .offset = _offset,                                      \
 701                 .con_id = _con_id,                                      \
 702                 .dev_id = _dev_id,                                      \
 703                 .flags = _flags                                         \
 704         }
 705
 706 #define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\
 707                         _mux_shift, _mux_width, _mux_flags, _div_shift, \
 708                         _div_width, _div_frac_width, _div_flags, \
 709                         _clk_num, _gate_flags, _clk_id) \
 710         TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
 711                         _mux_shift, BIT(_mux_width) - 1, _mux_flags,    \
 712                         _div_shift, _div_width, _div_frac_width, _div_flags, \
 713                         _clk_num, _gate_flags, _clk_id,\
 714                         NULL, 0, NULL)
 715
 716 struct clk *tegra_clk_register_periph_data(void __iomem *clk_base,
 717                                            struct tegra_periph_init_data *init);
 718
 719 /**
 720  * struct clk_super_mux - super clock
 721  *
 722  * @hw:         handle between common and hardware-specific interfaces
 723  * @reg:        register controlling multiplexer
 724  * @width:      width of the multiplexer bit field
 725  * @flags:      hardware-specific flags
 726  * @div2_index: bit controlling divide-by-2
 727  * @pllx_index: PLLX index in the parent list
 728  * @lock:       register lock
 729  *
 730  * Flags:
 731  * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates
 732  *     that this is LP cluster clock.
 733  * TEGRA210_CPU_CLK - This flag is used to identify CPU cluster for gen5
 734  *     super mux parent using PLLP branches. To use PLLP branches to CPU, need
 735  *     to configure additional bit PLLP_OUT_CPU in the clock registers.
 736  * TEGRA20_SUPER_CLK - Tegra20 doesn't have a dedicated divider for Super
 737  *     clocks, it only has a clock-skipper.
 738  */
 739 struct tegra_clk_super_mux {
 740         struct clk_hw   hw;
 741         void __iomem    *reg;
 742         struct tegra_clk_frac_div frac_div;
 743         const struct clk_ops    *div_ops;
 744         u8              width;
 745         u8              flags;
 746         u8              div2_index;
 747         u8              pllx_index;
 748         spinlock_t      *lock;
 749 };
 750
 751 #define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw)
 752
 753 #define TEGRA_DIVIDER_2 BIT(0)
 754 #define TEGRA210_CPU_CLK BIT(1)
 755 #define TEGRA20_SUPER_CLK BIT(2)
 756
 757 extern const struct clk_ops tegra_clk_super_ops;
 758 struct clk *tegra_clk_register_super_mux(const char *name,
 759                 const char **parent_names, u8 num_parents,
 760                 unsigned long flags, void __iomem *reg, u8 clk_super_flags,
 761                 u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock);
 762 struct clk *tegra_clk_register_super_clk(const char *name,
 763                 const char * const *parent_names, u8 num_parents,
 764                 unsigned long flags, void __iomem *reg, u8 clk_super_flags,
 765                 spinlock_t *lock);
 766 struct clk *tegra_clk_register_super_cclk(const char *name,
 767                 const char * const *parent_names, u8 num_parents,
 768                 unsigned long flags, void __iomem *reg, u8 clk_super_flags,
 769                 spinlock_t *lock);
 770 int tegra_cclk_pre_pllx_rate_change(void);
 771 void tegra_cclk_post_pllx_rate_change(void);
 772
 773 /**
 774  * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC
 775  *
 776  * @hw:         handle between common and hardware-specific interfaces
 777  * @reg:        register controlling mux and divider
 778  * @flags:      hardware-specific flags
 779  * @lock:       optional register lock
 780  * @gate:       gate clock
 781  * @gate_ops:   gate clock ops
 782  */
 783 struct tegra_sdmmc_mux {
 784         struct clk_hw           hw;
 785         void __iomem            *reg;
 786         spinlock_t              *lock;
 787         const struct clk_ops    *gate_ops;
 788         struct tegra_clk_periph_gate    gate;
 789         u8                      div_flags;
 790 };
 791
 792 #define to_clk_sdmmc_mux(_hw) container_of(_hw, struct tegra_sdmmc_mux, hw)
 793
 794 struct clk *tegra_clk_register_sdmmc_mux_div(const char *name,
 795                 void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags,
 796                 unsigned long flags, void *lock);
 797
 798 /**
 799  * struct clk_init_table - clock initialization table
 800  * @clk_id:     clock id as mentioned in device tree bindings
 801  * @parent_id:  parent clock id as mentioned in device tree bindings
 802  * @rate:       rate to set
 803  * @state:      enable/disable
 804  */
 805 struct tegra_clk_init_table {
 806         unsigned int    clk_id;
 807         unsigned int    parent_id;
 808         unsigned long   rate;
 809         int             state;
 810 };
 811
 812 /**
 813  * struct clk_duplicate - duplicate clocks
 814  * @clk_id:     clock id as mentioned in device tree bindings
 815  * @lookup:     duplicate lookup entry for the clock
 816  */
 817 struct tegra_clk_duplicate {
 818         int                     clk_id;
 819         struct clk_lookup       lookup;
 820 };
 821
 822 #define TEGRA_CLK_DUPLICATE(_clk_id, _dev, _con) \
 823         {                                       \
 824                 .clk_id = _clk_id,              \
 825                 .lookup = {                     \
 826                         .dev_id = _dev,         \
 827                         .con_id = _con,         \
 828                 },                              \
 829         }
 830
 831 struct tegra_clk {
 832         int                     dt_id;
 833         bool                    present;
 834 };
 835
 836 struct tegra_devclk {
 837         int             dt_id;
 838         char            *dev_id;
 839         char            *con_id;
 840 };
 841
 842 void tegra_init_special_resets(unsigned int num, int (*assert)(unsigned long),
 843                                int (*deassert)(unsigned long));
 844
 845 void tegra_init_from_table(struct tegra_clk_init_table *tbl,
 846                 struct clk *clks[], int clk_max);
 847
 848 void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
 849                 struct clk *clks[], int clk_max);
 850
 851 const struct tegra_clk_periph_regs *get_reg_bank(int clkid);
 852 struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks);
 853
 854 struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk);
 855
 856 void tegra_add_of_provider(struct device_node *np, void *clk_src_onecell_get);
 857 void tegra_register_devclks(struct tegra_devclk *dev_clks, int num);
 858
 859 void tegra_audio_clk_init(void __iomem *clk_base,
 860                         void __iomem *pmc_base, struct tegra_clk *tegra_clks,
 861                         struct tegra_audio_clk_info *audio_info,
 862                         unsigned int num_plls, unsigned long sync_max_rate);
 863
 864 void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base,
 865                         struct tegra_clk *tegra_clks,
 866                         struct tegra_clk_pll_params *pll_params);
 867
 868 void tegra_fixed_clk_init(struct tegra_clk *tegra_clks);
 869 int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
 870                        unsigned long *input_freqs, unsigned int num,
 871                        unsigned int clk_m_div, unsigned long *osc_freq,
 872                        unsigned long *pll_ref_freq);
 873 void tegra_super_clk_gen4_init(void __iomem *clk_base,
 874                         void __iomem *pmc_base, struct tegra_clk *tegra_clks,
 875                         struct tegra_clk_pll_params *pll_params);
 876 void tegra_super_clk_gen5_init(void __iomem *clk_base,
 877                         void __iomem *pmc_base, struct tegra_clk *tegra_clks,
 878                         struct tegra_clk_pll_params *pll_params);
 879
 880 #ifdef CONFIG_TEGRA124_CLK_EMC
 881 struct clk *tegra124_clk_register_emc(void __iomem *base, struct device_node *np,
 882                                       spinlock_t *lock);
 883 bool tegra124_clk_emc_driver_available(struct clk_hw *emc_hw);
 884 #else
 885 static inline struct clk *
 886 tegra124_clk_register_emc(void __iomem *base, struct device_node *np,
 887                           spinlock_t *lock)
 888 {
 889         return NULL;
 890 }
 891
 892 static inline bool tegra124_clk_emc_driver_available(struct clk_hw *emc_hw)
 893 {
 894         return false;
 895 }
 896 #endif
 897
 898 void tegra114_clock_tune_cpu_trimmers_high(void);
 899 void tegra114_clock_tune_cpu_trimmers_low(void);
 900 void tegra114_clock_tune_cpu_trimmers_init(void);
 901 void tegra114_clock_assert_dfll_dvco_reset(void);
 902 void tegra114_clock_deassert_dfll_dvco_reset(void);
 903
 904 typedef void (*tegra_clk_apply_init_table_func)(void);
 905 extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
 906 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll);
 907 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
 908 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
 909 int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
 910                  u8 frac_width, u8 flags);
 911 void tegra_clk_osc_resume(void __iomem *clk_base);
 912 void tegra_clk_set_pllp_out_cpu(bool enable);
 913 void tegra_clk_periph_suspend(void);
 914 void tegra_clk_periph_resume(void);
 915
 916
 917 /* Combined read fence with delay */
 918 #define fence_udelay(delay, reg)        \
 919         do {                            \
 920                 readl(reg);             \
 921                 udelay(delay);          \
 922         } while (0)
 923
 924 bool tegra20_clk_emc_driver_available(struct clk_hw *emc_hw);
 925 struct clk *tegra20_clk_register_emc(void __iomem *ioaddr, bool low_jitter);
 926
 927 struct clk *tegra210_clk_register_emc(struct device_node *np,
 928                                       void __iomem *regs);
 929
 930 struct clk *tegra_clk_dev_register(struct clk_hw *hw);
 931
 932 #endif /* TEGRA_CLK_H */