drivers/clk/ti/fapll.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2
   3 #include <linux/clk.h>
   4 #include <linux/clk-provider.h>
   5 #include <linux/delay.h>
   6 #include <linux/err.h>
   7 #include <linux/io.h>
   8 #include <linux/math64.h>
   9 #include <linux/of.h>
  10 #include <linux/of_address.h>
  11 #include <linux/clk/ti.h>
  12
  13 #include "clock.h"
  14
  15 /* FAPLL Control Register PLL_CTRL */
  16 #define FAPLL_MAIN_MULT_N_SHIFT 16
  17 #define FAPLL_MAIN_DIV_P_SHIFT  8
  18 #define FAPLL_MAIN_LOCK         BIT(7)
  19 #define FAPLL_MAIN_PLLEN        BIT(3)
  20 #define FAPLL_MAIN_BP           BIT(2)
  21 #define FAPLL_MAIN_LOC_CTL      BIT(0)
  22
  23 #define FAPLL_MAIN_MAX_MULT_N   0xffff
  24 #define FAPLL_MAIN_MAX_DIV_P    0xff
  25 #define FAPLL_MAIN_CLEAR_MASK   \
  26         ((FAPLL_MAIN_MAX_MULT_N << FAPLL_MAIN_MULT_N_SHIFT) | \
  27          (FAPLL_MAIN_DIV_P_SHIFT << FAPLL_MAIN_DIV_P_SHIFT) | \
  28          FAPLL_MAIN_LOC_CTL)
  29
  30 /* FAPLL powerdown register PWD */
  31 #define FAPLL_PWD_OFFSET        4
  32
  33 #define MAX_FAPLL_OUTPUTS       7
  34 #define FAPLL_MAX_RETRIES       1000
  35
  36 #define to_fapll(_hw)           container_of(_hw, struct fapll_data, hw)
  37 #define to_synth(_hw)           container_of(_hw, struct fapll_synth, hw)
  38
  39 /* The bypass bit is inverted on the ddr_pll.. */
  40 #define fapll_is_ddr_pll(va)    (((u32)(va) & 0xffff) == 0x0440)
  41
  42 /*
  43  * The audio_pll_clk1 input is hard wired to the 27MHz bypass clock,
  44  * and the audio_pll_clk1 synthesizer is hardwared to 32KiHz output.
  45  */
  46 #define is_ddr_pll_clk1(va)     (((u32)(va) & 0xffff) == 0x044c)
  47 #define is_audio_pll_clk1(va)   (((u32)(va) & 0xffff) == 0x04a8)
  48
  49 /* Synthesizer divider register */
  50 #define SYNTH_LDMDIV1           BIT(8)
  51
  52 /* Synthesizer frequency register */
  53 #define SYNTH_LDFREQ            BIT(31)
  54
  55 #define SYNTH_PHASE_K           8
  56 #define SYNTH_MAX_INT_DIV       0xf
  57 #define SYNTH_MAX_DIV_M         0xff
  58
  59 struct fapll_data {
  60         struct clk_hw hw;
  61         void __iomem *base;
  62         const char *name;
  63         struct clk *clk_ref;
  64         struct clk *clk_bypass;
  65         struct clk_onecell_data outputs;
  66         bool bypass_bit_inverted;
  67 };
  68
  69 struct fapll_synth {
  70         struct clk_hw hw;
  71         struct fapll_data *fd;
  72         int index;
  73         void __iomem *freq;
  74         void __iomem *div;
  75         const char *name;
  76         struct clk *clk_pll;
  77 };
  78
  79 static bool ti_fapll_clock_is_bypass(struct fapll_data *fd)
  80 {
  81         u32 v = readl_relaxed(fd->base);
  82
  83         if (fd->bypass_bit_inverted)
  84                 return !(v & FAPLL_MAIN_BP);
  85         else
  86                 return !!(v & FAPLL_MAIN_BP);
  87 }
  88
  89 static void ti_fapll_set_bypass(struct fapll_data *fd)
  90 {
  91         u32 v = readl_relaxed(fd->base);
  92
  93         if (fd->bypass_bit_inverted)
  94                 v &= ~FAPLL_MAIN_BP;
  95         else
  96                 v |= FAPLL_MAIN_BP;
  97         writel_relaxed(v, fd->base);
  98 }
  99
 100 static void ti_fapll_clear_bypass(struct fapll_data *fd)
 101 {
 102         u32 v = readl_relaxed(fd->base);
 103
 104         if (fd->bypass_bit_inverted)
 105                 v |= FAPLL_MAIN_BP;
 106         else
 107                 v &= ~FAPLL_MAIN_BP;
 108         writel_relaxed(v, fd->base);
 109 }
 110
 111 static int ti_fapll_wait_lock(struct fapll_data *fd)
 112 {
 113         int retries = FAPLL_MAX_RETRIES;
 114         u32 v;
 115
 116         while ((v = readl_relaxed(fd->base))) {
 117                 if (v & FAPLL_MAIN_LOCK)
 118                         return 0;
 119
 120                 if (retries-- <= 0)
 121                         break;
 122
 123                 udelay(1);
 124         }
 125
 126         pr_err("%s failed to lock\n", fd->name);
 127
 128         return -ETIMEDOUT;
 129 }
 130
 131 static int ti_fapll_enable(struct clk_hw *hw)
 132 {
 133         struct fapll_data *fd = to_fapll(hw);
 134         u32 v = readl_relaxed(fd->base);
 135
 136         v |= FAPLL_MAIN_PLLEN;
 137         writel_relaxed(v, fd->base);
 138         ti_fapll_wait_lock(fd);
 139
 140         return 0;
 141 }
 142
 143 static void ti_fapll_disable(struct clk_hw *hw)
 144 {
 145         struct fapll_data *fd = to_fapll(hw);
 146         u32 v = readl_relaxed(fd->base);
 147
 148         v &= ~FAPLL_MAIN_PLLEN;
 149         writel_relaxed(v, fd->base);
 150 }
 151
 152 static int ti_fapll_is_enabled(struct clk_hw *hw)
 153 {
 154         struct fapll_data *fd = to_fapll(hw);
 155         u32 v = readl_relaxed(fd->base);
 156
 157         return v & FAPLL_MAIN_PLLEN;
 158 }
 159
 160 static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw,
 161                                           unsigned long parent_rate)
 162 {
 163         struct fapll_data *fd = to_fapll(hw);
 164         u32 fapll_n, fapll_p, v;
 165         u64 rate;
 166
 167         if (ti_fapll_clock_is_bypass(fd))
 168                 return parent_rate;
 169
 170         rate = parent_rate;
 171
 172         /* PLL pre-divider is P and multiplier is N */
 173         v = readl_relaxed(fd->base);
 174         fapll_p = (v >> 8) & 0xff;
 175         if (fapll_p)
 176                 do_div(rate, fapll_p);
 177         fapll_n = v >> 16;
 178         if (fapll_n)
 179                 rate *= fapll_n;
 180
 181         return rate;
 182 }
 183
 184 static u8 ti_fapll_get_parent(struct clk_hw *hw)
 185 {
 186         struct fapll_data *fd = to_fapll(hw);
 187
 188         if (ti_fapll_clock_is_bypass(fd))
 189                 return 1;
 190
 191         return 0;
 192 }
 193
 194 static int ti_fapll_set_div_mult(unsigned long rate,
 195                                  unsigned long parent_rate,
 196                                  u32 *pre_div_p, u32 *mult_n)
 197 {
 198         /*
 199          * So far no luck getting decent clock with PLL divider,
 200          * PLL does not seem to lock and the signal does not look
 201          * right. It seems the divider can only be used together
 202          * with the multiplier?
 203          */
 204         if (rate < parent_rate) {
 205                 pr_warn("FAPLL main divider rates unsupported\n");
 206                 return -EINVAL;
 207         }
 208
 209         *mult_n = rate / parent_rate;
 210         if (*mult_n > FAPLL_MAIN_MAX_MULT_N)
 211                 return -EINVAL;
 212         *pre_div_p = 1;
 213
 214         return 0;
 215 }
 216
 217 static long ti_fapll_round_rate(struct clk_hw *hw, unsigned long rate,
 218                                 unsigned long *parent_rate)
 219 {
 220         u32 pre_div_p, mult_n;
 221         int error;
 222
 223         if (!rate)
 224                 return -EINVAL;
 225
 226         error = ti_fapll_set_div_mult(rate, *parent_rate,
 227                                       &pre_div_p, &mult_n);
 228         if (error)
 229                 return error;
 230
 231         rate = *parent_rate / pre_div_p;
 232         rate *= mult_n;
 233
 234         return rate;
 235 }
 236
 237 static int ti_fapll_set_rate(struct clk_hw *hw, unsigned long rate,
 238                              unsigned long parent_rate)
 239 {
 240         struct fapll_data *fd = to_fapll(hw);
 241         u32 pre_div_p, mult_n, v;
 242         int error;
 243
 244         if (!rate)
 245                 return -EINVAL;
 246
 247         error = ti_fapll_set_div_mult(rate, parent_rate,
 248                                       &pre_div_p, &mult_n);
 249         if (error)
 250                 return error;
 251
 252         ti_fapll_set_bypass(fd);
 253         v = readl_relaxed(fd->base);
 254         v &= ~FAPLL_MAIN_CLEAR_MASK;
 255         v |= pre_div_p << FAPLL_MAIN_DIV_P_SHIFT;
 256         v |= mult_n << FAPLL_MAIN_MULT_N_SHIFT;
 257         writel_relaxed(v, fd->base);
 258         if (ti_fapll_is_enabled(hw))
 259                 ti_fapll_wait_lock(fd);
 260         ti_fapll_clear_bypass(fd);
 261
 262         return 0;
 263 }
 264
 265 static const struct clk_ops ti_fapll_ops = {
 266         .enable = ti_fapll_enable,
 267         .disable = ti_fapll_disable,
 268         .is_enabled = ti_fapll_is_enabled,
 269         .recalc_rate = ti_fapll_recalc_rate,
 270         .get_parent = ti_fapll_get_parent,
 271         .round_rate = ti_fapll_round_rate,
 272         .set_rate = ti_fapll_set_rate,
 273 };
 274
 275 static int ti_fapll_synth_enable(struct clk_hw *hw)
 276 {
 277         struct fapll_synth *synth = to_synth(hw);
 278         u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
 279
 280         v &= ~(1 << synth->index);
 281         writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
 282
 283         return 0;
 284 }
 285
 286 static void ti_fapll_synth_disable(struct clk_hw *hw)
 287 {
 288         struct fapll_synth *synth = to_synth(hw);
 289         u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
 290
 291         v |= 1 << synth->index;
 292         writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
 293 }
 294
 295 static int ti_fapll_synth_is_enabled(struct clk_hw *hw)
 296 {
 297         struct fapll_synth *synth = to_synth(hw);
 298         u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
 299
 300         return !(v & (1 << synth->index));
 301 }
 302
 303 /*
 304  * See dm816x TRM chapter 1.10.3 Flying Adder PLL fore more info
 305  */
 306 static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw,
 307                                                 unsigned long parent_rate)
 308 {
 309         struct fapll_synth *synth = to_synth(hw);
 310         u32 synth_div_m;
 311         u64 rate;
 312
 313         /* The audio_pll_clk1 is hardwired to produce 32.768KiHz clock */
 314         if (!synth->div)
 315                 return 32768;
 316
 317         /*
 318          * PLL in bypass sets the synths in bypass mode too. The PLL rate
 319          * can be also be set to 27MHz, so we can't use parent_rate to
 320          * check for bypass mode.
 321          */
 322         if (ti_fapll_clock_is_bypass(synth->fd))
 323                 return parent_rate;
 324
 325         rate = parent_rate;
 326
 327         /*
 328          * Synth frequency integer and fractional divider.
 329          * Note that the phase output K is 8, so the result needs
 330          * to be multiplied by SYNTH_PHASE_K.
 331          */
 332         if (synth->freq) {
 333                 u32 v, synth_int_div, synth_frac_div, synth_div_freq;
 334
 335                 v = readl_relaxed(synth->freq);
 336                 synth_int_div = (v >> 24) & 0xf;
 337                 synth_frac_div = v & 0xffffff;
 338                 synth_div_freq = (synth_int_div * 10000000) + synth_frac_div;
 339                 rate *= 10000000;
 340                 do_div(rate, synth_div_freq);
 341                 rate *= SYNTH_PHASE_K;
 342         }
 343
 344         /* Synth post-divider M */
 345         synth_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;
 346
 347         return DIV_ROUND_UP_ULL(rate, synth_div_m);
 348 }
 349
 350 static unsigned long ti_fapll_synth_get_frac_rate(struct clk_hw *hw,
 351                                                   unsigned long parent_rate)
 352 {
 353         struct fapll_synth *synth = to_synth(hw);
 354         unsigned long current_rate, frac_rate;
 355         u32 post_div_m;
 356
 357         current_rate = ti_fapll_synth_recalc_rate(hw, parent_rate);
 358         post_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;
 359         frac_rate = current_rate * post_div_m;
 360
 361         return frac_rate;
 362 }
 363
 364 static u32 ti_fapll_synth_set_frac_rate(struct fapll_synth *synth,
 365                                         unsigned long rate,
 366                                         unsigned long parent_rate)
 367 {
 368         u32 post_div_m, synth_int_div = 0, synth_frac_div = 0, v;
 369
 370         post_div_m = DIV_ROUND_UP_ULL((u64)parent_rate * SYNTH_PHASE_K, rate);
 371         post_div_m = post_div_m / SYNTH_MAX_INT_DIV;
 372         if (post_div_m > SYNTH_MAX_DIV_M)
 373                 return -EINVAL;
 374         if (!post_div_m)
 375                 post_div_m = 1;
 376
 377         for (; post_div_m < SYNTH_MAX_DIV_M; post_div_m++) {
 378                 synth_int_div = DIV_ROUND_UP_ULL((u64)parent_rate *
 379                                                  SYNTH_PHASE_K *
 380                                                  10000000,
 381                                                  rate * post_div_m);
 382                 synth_frac_div = synth_int_div % 10000000;
 383                 synth_int_div /= 10000000;
 384
 385                 if (synth_int_div <= SYNTH_MAX_INT_DIV)
 386                         break;
 387         }
 388
 389         if (synth_int_div > SYNTH_MAX_INT_DIV)
 390                 return -EINVAL;
 391
 392         v = readl_relaxed(synth->freq);
 393         v &= ~0x1fffffff;
 394         v |= (synth_int_div & SYNTH_MAX_INT_DIV) << 24;
 395         v |= (synth_frac_div & 0xffffff);
 396         v |= SYNTH_LDFREQ;
 397         writel_relaxed(v, synth->freq);
 398
 399         return post_div_m;
 400 }
 401
 402 static long ti_fapll_synth_round_rate(struct clk_hw *hw, unsigned long rate,
 403                                       unsigned long *parent_rate)
 404 {
 405         struct fapll_synth *synth = to_synth(hw);
 406         struct fapll_data *fd = synth->fd;
 407         unsigned long r;
 408
 409         if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)
 410                 return -EINVAL;
 411
 412         /* Only post divider m available with no fractional divider? */
 413         if (!synth->freq) {
 414                 unsigned long frac_rate;
 415                 u32 synth_post_div_m;
 416
 417                 frac_rate = ti_fapll_synth_get_frac_rate(hw, *parent_rate);
 418                 synth_post_div_m = DIV_ROUND_UP(frac_rate, rate);
 419                 r = DIV_ROUND_UP(frac_rate, synth_post_div_m);
 420                 goto out;
 421         }
 422
 423         r = *parent_rate * SYNTH_PHASE_K;
 424         if (rate > r)
 425                 goto out;
 426
 427         r = DIV_ROUND_UP_ULL(r, SYNTH_MAX_INT_DIV * SYNTH_MAX_DIV_M);
 428         if (rate < r)
 429                 goto out;
 430
 431         r = rate;
 432 out:
 433         return r;
 434 }
 435
 436 static int ti_fapll_synth_set_rate(struct clk_hw *hw, unsigned long rate,
 437                                    unsigned long parent_rate)
 438 {
 439         struct fapll_synth *synth = to_synth(hw);
 440         struct fapll_data *fd = synth->fd;
 441         unsigned long frac_rate, post_rate = 0;
 442         u32 post_div_m = 0, v;
 443
 444         if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)
 445                 return -EINVAL;
 446
 447         /* Produce the rate with just post divider M? */
 448         frac_rate = ti_fapll_synth_get_frac_rate(hw, parent_rate);
 449         if (frac_rate < rate) {
 450                 if (!synth->freq)
 451                         return -EINVAL;
 452         } else {
 453                 post_div_m = DIV_ROUND_UP(frac_rate, rate);
 454                 if (post_div_m && (post_div_m <= SYNTH_MAX_DIV_M))
 455                         post_rate = DIV_ROUND_UP(frac_rate, post_div_m);
 456                 if (!synth->freq && !post_rate)
 457                         return -EINVAL;
 458         }
 459
 460         /* Need to recalculate the fractional divider? */
 461         if ((post_rate != rate) && synth->freq)
 462                 post_div_m = ti_fapll_synth_set_frac_rate(synth,
 463                                                           rate,
 464                                                           parent_rate);
 465
 466         v = readl_relaxed(synth->div);
 467         v &= ~SYNTH_MAX_DIV_M;
 468         v |= post_div_m;
 469         v |= SYNTH_LDMDIV1;
 470         writel_relaxed(v, synth->div);
 471
 472         return 0;
 473 }
 474
 475 static const struct clk_ops ti_fapll_synt_ops = {
 476         .enable = ti_fapll_synth_enable,
 477         .disable = ti_fapll_synth_disable,
 478         .is_enabled = ti_fapll_synth_is_enabled,
 479         .recalc_rate = ti_fapll_synth_recalc_rate,
 480         .round_rate = ti_fapll_synth_round_rate,
 481         .set_rate = ti_fapll_synth_set_rate,
 482 };
 483
 484 static struct clk * __init ti_fapll_synth_setup(struct fapll_data *fd,
 485                                                 void __iomem *freq,
 486                                                 void __iomem *div,
 487                                                 int index,
 488                                                 const char *name,
 489                                                 const char *parent,
 490                                                 struct clk *pll_clk)
 491 {
 492         struct clk_init_data *init;
 493         struct fapll_synth *synth;
 494         struct clk *clk = ERR_PTR(-ENOMEM);
 495
 496         init = kzalloc(sizeof(*init), GFP_KERNEL);
 497         if (!init)
 498                 return ERR_PTR(-ENOMEM);
 499
 500         init->ops = &ti_fapll_synt_ops;
 501         init->name = name;
 502         init->parent_names = &parent;
 503         init->num_parents = 1;
 504
 505         synth = kzalloc(sizeof(*synth), GFP_KERNEL);
 506         if (!synth)
 507                 goto free;
 508
 509         synth->fd = fd;
 510         synth->index = index;
 511         synth->freq = freq;
 512         synth->div = div;
 513         synth->name = name;
 514         synth->hw.init = init;
 515         synth->clk_pll = pll_clk;
 516
 517         clk = clk_register(NULL, &synth->hw);
 518         if (IS_ERR(clk)) {
 519                 pr_err("failed to register clock\n");
 520                 goto free;
 521         }
 522
 523         return clk;
 524
 525 free:
 526         kfree(synth);
 527         kfree(init);
 528
 529         return clk;
 530 }
 531
 532 static void __init ti_fapll_setup(struct device_node *node)
 533 {
 534         struct fapll_data *fd;
 535         struct clk_init_data *init = NULL;
 536         const char *parent_name[2];
 537         struct clk *pll_clk;
 538         const char *name;
 539         int i;
 540
 541         fd = kzalloc(sizeof(*fd), GFP_KERNEL);
 542         if (!fd)
 543                 return;
 544
 545         fd->outputs.clks = kzalloc(sizeof(struct clk *) *
 546                                    MAX_FAPLL_OUTPUTS + 1,
 547                                    GFP_KERNEL);
 548         if (!fd->outputs.clks)
 549                 goto free;
 550
 551         init = kzalloc(sizeof(*init), GFP_KERNEL);
 552         if (!init)
 553                 goto free;
 554
 555         init->ops = &ti_fapll_ops;
 556         name = ti_dt_clk_name(node);
 557         init->name = name;
 558
 559         init->num_parents = of_clk_get_parent_count(node);
 560         if (init->num_parents != 2) {
 561                 pr_err("%pOFn must have two parents\n", node);
 562                 goto free;
 563         }
 564
 565         of_clk_parent_fill(node, parent_name, 2);
 566         init->parent_names = parent_name;
 567
 568         fd->clk_ref = of_clk_get(node, 0);
 569         if (IS_ERR(fd->clk_ref)) {
 570                 pr_err("%pOFn could not get clk_ref\n", node);
 571                 goto free;
 572         }
 573
 574         fd->clk_bypass = of_clk_get(node, 1);
 575         if (IS_ERR(fd->clk_bypass)) {
 576                 pr_err("%pOFn could not get clk_bypass\n", node);
 577                 goto free;
 578         }
 579
 580         fd->base = of_iomap(node, 0);
 581         if (!fd->base) {
 582                 pr_err("%pOFn could not get IO base\n", node);
 583                 goto free;
 584         }
 585
 586         if (fapll_is_ddr_pll(fd->base))
 587                 fd->bypass_bit_inverted = true;
 588
 589         fd->name = name;
 590         fd->hw.init = init;
 591
 592         /* Register the parent PLL */
 593         pll_clk = clk_register(NULL, &fd->hw);
 594         if (IS_ERR(pll_clk))
 595                 goto unmap;
 596
 597         fd->outputs.clks[0] = pll_clk;
 598         fd->outputs.clk_num++;
 599
 600         /*
 601          * Set up the child synthesizers starting at index 1 as the
 602          * PLL output is at index 0. We need to check the clock-indices
 603          * for numbering in case there are holes in the synth mapping,
 604          * and then probe the synth register to see if it has a FREQ
 605          * register available.
 606          */
 607         for (i = 0; i < MAX_FAPLL_OUTPUTS; i++) {
 608                 const char *output_name;
 609                 void __iomem *freq, *div;
 610                 struct clk *synth_clk;
 611                 int output_instance;
 612                 u32 v;
 613
 614                 if (of_property_read_string_index(node, "clock-output-names",
 615                                                   i, &output_name))
 616                         continue;
 617
 618                 if (of_property_read_u32_index(node, "clock-indices", i,
 619                                                &output_instance))
 620                         output_instance = i;
 621
 622                 freq = fd->base + (output_instance * 8);
 623                 div = freq + 4;
 624
 625                 /* Check for hardwired audio_pll_clk1 */
 626                 if (is_audio_pll_clk1(freq)) {
 627                         freq = NULL;
 628                         div = NULL;
 629                 } else {
 630                         /* Does the synthesizer have a FREQ register? */
 631                         v = readl_relaxed(freq);
 632                         if (!v)
 633                                 freq = NULL;
 634                 }
 635                 synth_clk = ti_fapll_synth_setup(fd, freq, div, output_instance,
 636                                                  output_name, name, pll_clk);
 637                 if (IS_ERR(synth_clk))
 638                         continue;
 639
 640                 fd->outputs.clks[output_instance] = synth_clk;
 641                 fd->outputs.clk_num++;
 642
 643                 clk_register_clkdev(synth_clk, output_name, NULL);
 644         }
 645
 646         /* Register the child synthesizers as the FAPLL outputs */
 647         of_clk_add_provider(node, of_clk_src_onecell_get, &fd->outputs);
 648         /* Add clock alias for the outputs */
 649
 650         kfree(init);
 651
 652         return;
 653
 654 unmap:
 655         iounmap(fd->base);
 656 free:
 657         if (fd->clk_bypass)
 658                 clk_put(fd->clk_bypass);
 659         if (fd->clk_ref)
 660                 clk_put(fd->clk_ref);
 661         kfree(fd->outputs.clks);
 662         kfree(fd);
 663         kfree(init);
 664 }
 665
 666 CLK_OF_DECLARE(ti_fapll_clock, "ti,dm816-fapll-clock", ti_fapll_setup);