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drm/tests: hdmi: Fix memory leaks in drm_display_mode_from_cea_vic()
[drm/drm-misc.git] / drivers / i2c / busses / i2c-ismt.c
blobc93c02aa6ac8cce5ae6a3898a8487ed5d2b0a9c8
1 /*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * Copyright(c) 2012 Intel Corporation. All rights reserved.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 * The full GNU General Public License is included in this distribution
18 * in the file called LICENSE.GPL.
19 *
20 * BSD LICENSE
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions
24 * are met:
25 *
26 * * Redistributions of source code must retain the above copyright
27 * notice, this list of conditions and the following disclaimer.
28 * * Redistributions in binary form must reproduce the above copyright
29 * notice, this list of conditions and the following disclaimer in
30 * the documentation and/or other materials provided with the
31 * distribution.
32 * * Neither the name of Intel Corporation nor the names of its
33 * contributors may be used to endorse or promote products derived
34 * from this software without specific prior written permission.
35 *
36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
37 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
39 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
40 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
41 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
42 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
43 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
44 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
45 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
47 */
48
49 /*
50 * Supports the SMBus Message Transport (SMT) in the Intel Atom Processor
51 * S12xx Product Family.
52 *
53 * Features supported by this driver:
54 * Hardware PEC yes
55 * Block buffer yes
56 * Block process call transaction yes
57 * Slave mode no
58 */
59
60 #include <linux/module.h>
61 #include <linux/pci.h>
62 #include <linux/kernel.h>
63 #include <linux/stddef.h>
64 #include <linux/completion.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/i2c.h>
67 #include <linux/acpi.h>
68 #include <linux/interrupt.h>
69
70 #include <linux/io-64-nonatomic-lo-hi.h>
71
72 /* PCI Address Constants */
73 #define SMBBAR 0
74
75 /* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */
76 #define PCI_DEVICE_ID_INTEL_S1200_SMT0 0x0c59
77 #define PCI_DEVICE_ID_INTEL_S1200_SMT1 0x0c5a
78 #define PCI_DEVICE_ID_INTEL_CDF_SMT 0x18ac
79 #define PCI_DEVICE_ID_INTEL_DNV_SMT 0x19ac
80 #define PCI_DEVICE_ID_INTEL_EBG_SMT 0x1bff
81 #define PCI_DEVICE_ID_INTEL_AVOTON_SMT 0x1f15
82
83 #define ISMT_DESC_ENTRIES 2 /* number of descriptor entries */
84 #define ISMT_MAX_RETRIES 3 /* number of SMBus retries to attempt */
85 #define ISMT_LOG_ENTRIES 3 /* number of interrupt cause log entries */
86
87 /* Hardware Descriptor Constants - Control Field */
88 #define ISMT_DESC_CWRL 0x01 /* Command/Write Length */
89 #define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */
90 #define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */
91 #define ISMT_DESC_PEC 0x10 /* Packet Error Code */
92 #define ISMT_DESC_I2C 0x20 /* I2C Enable */
93 #define ISMT_DESC_INT 0x40 /* Interrupt */
94 #define ISMT_DESC_SOE 0x80 /* Stop On Error */
95
96 /* Hardware Descriptor Constants - Status Field */
97 #define ISMT_DESC_SCS 0x01 /* Success */
98 #define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */
99 #define ISMT_DESC_NAK 0x08 /* NAK Received */
100 #define ISMT_DESC_CRC 0x10 /* CRC Error */
101 #define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */
102 #define ISMT_DESC_COL 0x40 /* Collisions */
103 #define ISMT_DESC_LPR 0x80 /* Large Packet Received */
104
105 /* Macros */
106 #define ISMT_DESC_ADDR_RW(addr, rw) (((addr) << 1) | (rw))
107
108 /* iSMT General Register address offsets (SMBBAR + <addr>) */
109 #define ISMT_GR_GCTRL 0x000 /* General Control */
110 #define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */
111 #define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */
112 #define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */
113 #define ISMT_GR_ERRSTS 0x018 /* Error Status */
114 #define ISMT_GR_ERRINFO 0x01c /* Error Information */
115
116 /* iSMT Master Registers */
117 #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */
118 #define ISMT_MSTR_MCTRL 0x108 /* Master Control */
119 #define ISMT_MSTR_MSTS 0x10c /* Master Status */
120 #define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */
121 #define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */
122
123 /* iSMT Miscellaneous Registers */
124 #define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */
125
126 /* General Control Register (GCTRL) bit definitions */
127 #define ISMT_GCTRL_TRST 0x04 /* Target Reset */
128 #define ISMT_GCTRL_KILL 0x08 /* Kill */
129 #define ISMT_GCTRL_SRST 0x40 /* Soft Reset */
130
131 /* Master Control Register (MCTRL) bit definitions */
132 #define ISMT_MCTRL_SS 0x01 /* Start/Stop */
133 #define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */
134 #define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */
135
136 /* Master Status Register (MSTS) bit definitions */
137 #define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */
138 #define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */
139 #define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */
140 #define ISMT_MSTS_IP 0x01 /* In Progress */
141
142 /* Master Descriptor Size (MDS) bit definitions */
143 #define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */
144
145 /* SMBus PHY Global Timing Register (SPGT) bit definitions */
146 #define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */
147 #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */
148 #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */
149 #define ISMT_SPGT_SPD_400K (0x2U << 30) /* 400 kHz */
150 #define ISMT_SPGT_SPD_1M (0x3U << 30) /* 1 MHz */
151
152
153 /* MSI Control Register (MSICTL) bit definitions */
154 #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */
155
156 /* iSMT Hardware Descriptor */
157 struct ismt_desc {
158 u8 tgtaddr_rw; /* target address & r/w bit */
159 u8 wr_len_cmd; /* write length in bytes or a command */
160 u8 rd_len; /* read length */
161 u8 control; /* control bits */
162 u8 status; /* status bits */
163 u8 retry; /* collision retry and retry count */
164 u8 rxbytes; /* received bytes */
165 u8 txbytes; /* transmitted bytes */
166 u32 dptr_low; /* lower 32 bit of the data pointer */
167 u32 dptr_high; /* upper 32 bit of the data pointer */
168 } __packed;
169
170 struct ismt_priv {
171 struct i2c_adapter adapter;
172 void __iomem *smba; /* PCI BAR */
173 struct pci_dev *pci_dev;
174 struct ismt_desc *hw; /* descriptor virt base addr */
175 dma_addr_t io_rng_dma; /* descriptor HW base addr */
176 u8 head; /* ring buffer head pointer */
177 struct completion cmp; /* interrupt completion */
178 u8 buffer[I2C_SMBUS_BLOCK_MAX + 16]; /* temp R/W data buffer */
179 dma_addr_t log_dma;
180 u32 *log;
181 };
182
183 static const struct pci_device_id ismt_ids[] = {
184 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) },
185 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) },
186 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMT) },
187 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMT) },
188 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG_SMT) },
189 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMT) },
190 { 0, }
191 };
192
193 MODULE_DEVICE_TABLE(pci, ismt_ids);
194
195 /* Bus speed control bits for slow debuggers - refer to the docs for usage */
196 static unsigned int bus_speed;
197 module_param(bus_speed, uint, S_IRUGO);
198 MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)");
199
200 /**
201 * __ismt_desc_dump() - dump the contents of a specific descriptor
202 * @dev: the iSMT device
203 * @desc: the iSMT hardware descriptor
204 */
205 static void __ismt_desc_dump(struct device *dev, const struct ismt_desc *desc)
206 {
207
208 dev_dbg(dev, "Descriptor struct: %p\n", desc);
209 dev_dbg(dev, "\ttgtaddr_rw=0x%02X\n", desc->tgtaddr_rw);
210 dev_dbg(dev, "\twr_len_cmd=0x%02X\n", desc->wr_len_cmd);
211 dev_dbg(dev, "\trd_len= 0x%02X\n", desc->rd_len);
212 dev_dbg(dev, "\tcontrol= 0x%02X\n", desc->control);
213 dev_dbg(dev, "\tstatus= 0x%02X\n", desc->status);
214 dev_dbg(dev, "\tretry= 0x%02X\n", desc->retry);
215 dev_dbg(dev, "\trxbytes= 0x%02X\n", desc->rxbytes);
216 dev_dbg(dev, "\ttxbytes= 0x%02X\n", desc->txbytes);
217 dev_dbg(dev, "\tdptr_low= 0x%08X\n", desc->dptr_low);
218 dev_dbg(dev, "\tdptr_high= 0x%08X\n", desc->dptr_high);
219 }
220 /**
221 * ismt_desc_dump() - dump the contents of a descriptor for debug purposes
222 * @priv: iSMT private data
223 */
224 static void ismt_desc_dump(struct ismt_priv *priv)
225 {
226 struct device *dev = &priv->pci_dev->dev;
227 struct ismt_desc *desc = &priv->hw[priv->head];
228
229 dev_dbg(dev, "Dump of the descriptor struct: 0x%X\n", priv->head);
230 __ismt_desc_dump(dev, desc);
231 }
232
233 /**
234 * ismt_gen_reg_dump() - dump the iSMT General Registers
235 * @priv: iSMT private data
236 */
237 static void ismt_gen_reg_dump(struct ismt_priv *priv)
238 {
239 struct device *dev = &priv->pci_dev->dev;
240
241 dev_dbg(dev, "Dump of the iSMT General Registers\n");
242 dev_dbg(dev, " GCTRL.... : (0x%p)=0x%X\n",
243 priv->smba + ISMT_GR_GCTRL,
244 readl(priv->smba + ISMT_GR_GCTRL));
245 dev_dbg(dev, " SMTICL... : (0x%p)=0x%016llX\n",
246 priv->smba + ISMT_GR_SMTICL,
247 (long long unsigned int)readq(priv->smba + ISMT_GR_SMTICL));
248 dev_dbg(dev, " ERRINTMSK : (0x%p)=0x%X\n",
249 priv->smba + ISMT_GR_ERRINTMSK,
250 readl(priv->smba + ISMT_GR_ERRINTMSK));
251 dev_dbg(dev, " ERRAERMSK : (0x%p)=0x%X\n",
252 priv->smba + ISMT_GR_ERRAERMSK,
253 readl(priv->smba + ISMT_GR_ERRAERMSK));
254 dev_dbg(dev, " ERRSTS... : (0x%p)=0x%X\n",
255 priv->smba + ISMT_GR_ERRSTS,
256 readl(priv->smba + ISMT_GR_ERRSTS));
257 dev_dbg(dev, " ERRINFO.. : (0x%p)=0x%X\n",
258 priv->smba + ISMT_GR_ERRINFO,
259 readl(priv->smba + ISMT_GR_ERRINFO));
260 }
261
262 /**
263 * ismt_mstr_reg_dump() - dump the iSMT Master Registers
264 * @priv: iSMT private data
265 */
266 static void ismt_mstr_reg_dump(struct ismt_priv *priv)
267 {
268 struct device *dev = &priv->pci_dev->dev;
269
270 dev_dbg(dev, "Dump of the iSMT Master Registers\n");
271 dev_dbg(dev, " MDBA..... : (0x%p)=0x%016llX\n",
272 priv->smba + ISMT_MSTR_MDBA,
273 (long long unsigned int)readq(priv->smba + ISMT_MSTR_MDBA));
274 dev_dbg(dev, " MCTRL.... : (0x%p)=0x%X\n",
275 priv->smba + ISMT_MSTR_MCTRL,
276 readl(priv->smba + ISMT_MSTR_MCTRL));
277 dev_dbg(dev, " MSTS..... : (0x%p)=0x%X\n",
278 priv->smba + ISMT_MSTR_MSTS,
279 readl(priv->smba + ISMT_MSTR_MSTS));
280 dev_dbg(dev, " MDS...... : (0x%p)=0x%X\n",
281 priv->smba + ISMT_MSTR_MDS,
282 readl(priv->smba + ISMT_MSTR_MDS));
283 dev_dbg(dev, " RPOLICY.. : (0x%p)=0x%X\n",
284 priv->smba + ISMT_MSTR_RPOLICY,
285 readl(priv->smba + ISMT_MSTR_RPOLICY));
286 dev_dbg(dev, " SPGT..... : (0x%p)=0x%X\n",
287 priv->smba + ISMT_SPGT,
288 readl(priv->smba + ISMT_SPGT));
289 }
290
291 /**
292 * ismt_submit_desc() - add a descriptor to the ring
293 * @priv: iSMT private data
294 */
295 static void ismt_submit_desc(struct ismt_priv *priv)
296 {
297 uint fmhp;
298 uint val;
299
300 ismt_desc_dump(priv);
301 ismt_gen_reg_dump(priv);
302 ismt_mstr_reg_dump(priv);
303
304 /* Set the FMHP (Firmware Master Head Pointer)*/
305 fmhp = ((priv->head + 1) % ISMT_DESC_ENTRIES) << 16;
306 val = readl(priv->smba + ISMT_MSTR_MCTRL);
307 writel((val & ~ISMT_MCTRL_FMHP) | fmhp,
308 priv->smba + ISMT_MSTR_MCTRL);
309
310 /* Set the start bit */
311 val = readl(priv->smba + ISMT_MSTR_MCTRL);
312 writel(val | ISMT_MCTRL_SS,
313 priv->smba + ISMT_MSTR_MCTRL);
314 }
315
316 /**
317 * ismt_process_desc() - handle the completion of the descriptor
318 * @desc: the iSMT hardware descriptor
319 * @data: data buffer from the upper layer
320 * @priv: ismt_priv struct holding our dma buffer
321 * @size: SMBus transaction type
322 * @read_write: flag to indicate if this is a read or write
323 */
324 static int ismt_process_desc(const struct ismt_desc *desc,
325 union i2c_smbus_data *data,
326 struct ismt_priv *priv, int size,
327 char read_write)
328 {
329 u8 *dma_buffer = PTR_ALIGN(&priv->buffer[0], 16);
330
331 dev_dbg(&priv->pci_dev->dev, "Processing completed descriptor\n");
332 __ismt_desc_dump(&priv->pci_dev->dev, desc);
333 ismt_gen_reg_dump(priv);
334 ismt_mstr_reg_dump(priv);
335
336 if (desc->status & ISMT_DESC_SCS) {
337 if (read_write == I2C_SMBUS_WRITE &&
338 size != I2C_SMBUS_PROC_CALL &&
339 size != I2C_SMBUS_BLOCK_PROC_CALL)
340 return 0;
341
342 switch (size) {
343 case I2C_SMBUS_BYTE:
344 case I2C_SMBUS_BYTE_DATA:
345 data->byte = dma_buffer[0];
346 break;
347 case I2C_SMBUS_WORD_DATA:
348 case I2C_SMBUS_PROC_CALL:
349 data->word = dma_buffer[0] | (dma_buffer[1] << 8);
350 break;
351 case I2C_SMBUS_BLOCK_DATA:
352 case I2C_SMBUS_BLOCK_PROC_CALL:
353 if (desc->rxbytes != dma_buffer[0] + 1)
354 return -EMSGSIZE;
355
356 memcpy(data->block, dma_buffer, desc->rxbytes);
357 break;
358 case I2C_SMBUS_I2C_BLOCK_DATA:
359 memcpy(&data->block[1], dma_buffer, desc->rxbytes);
360 data->block[0] = desc->rxbytes;
361 break;
362 }
363 return 0;
364 }
365
366 if (likely(desc->status & ISMT_DESC_NAK))
367 return -ENXIO;
368
369 if (desc->status & ISMT_DESC_CRC)
370 return -EBADMSG;
371
372 if (desc->status & ISMT_DESC_COL)
373 return -EAGAIN;
374
375 if (desc->status & ISMT_DESC_LPR)
376 return -EPROTO;
377
378 if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO))
379 return -ETIMEDOUT;
380
381 return -EIO;
382 }
383
384 /**
385 * ismt_kill_transaction() - kill current transaction
386 * @priv: iSMT private data
387 */
388 static void ismt_kill_transaction(struct ismt_priv *priv)
389 {
390 writel(ISMT_GCTRL_KILL, priv->smba + ISMT_GR_GCTRL);
391 }
392
393 /**
394 * ismt_access() - process an SMBus command
395 * @adap: the i2c host adapter
396 * @addr: address of the i2c/SMBus target
397 * @flags: command options
398 * @read_write: read from or write to device
399 * @command: the i2c/SMBus command to issue
400 * @size: SMBus transaction type
401 * @data: read/write data buffer
402 */
403 static int ismt_access(struct i2c_adapter *adap, u16 addr,
404 unsigned short flags, char read_write, u8 command,
405 int size, union i2c_smbus_data *data)
406 {
407 int ret;
408 unsigned long time_left;
409 dma_addr_t dma_addr = 0; /* address of the data buffer */
410 u8 dma_size = 0;
411 enum dma_data_direction dma_direction = 0;
412 struct ismt_desc *desc;
413 struct ismt_priv *priv = i2c_get_adapdata(adap);
414 struct device *dev = &priv->pci_dev->dev;
415 u8 *dma_buffer = PTR_ALIGN(&priv->buffer[0], 16);
416
417 desc = &priv->hw[priv->head];
418
419 /* Initialize the DMA buffer */
420 memset(priv->buffer, 0, sizeof(priv->buffer));
421
422 /* Initialize the descriptor */
423 memset(desc, 0, sizeof(struct ismt_desc));
424 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write);
425
426 /* Always clear the log entries */
427 memset(priv->log, 0, ISMT_LOG_ENTRIES * sizeof(u32));
428
429 /* Initialize common control bits */
430 if (likely(pci_dev_msi_enabled(priv->pci_dev)))
431 desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR;
432 else
433 desc->control = ISMT_DESC_FAIR;
434
435 if ((flags & I2C_CLIENT_PEC) && (size != I2C_SMBUS_QUICK)
436 && (size != I2C_SMBUS_I2C_BLOCK_DATA))
437 desc->control |= ISMT_DESC_PEC;
438
439 switch (size) {
440 case I2C_SMBUS_QUICK:
441 dev_dbg(dev, "I2C_SMBUS_QUICK\n");
442 break;
443
444 case I2C_SMBUS_BYTE:
445 if (read_write == I2C_SMBUS_WRITE) {
446 /*
447 * Send Byte
448 * The command field contains the write data
449 */
450 dev_dbg(dev, "I2C_SMBUS_BYTE: WRITE\n");
451 desc->control |= ISMT_DESC_CWRL;
452 desc->wr_len_cmd = command;
453 } else {
454 /* Receive Byte */
455 dev_dbg(dev, "I2C_SMBUS_BYTE: READ\n");
456 dma_size = 1;
457 dma_direction = DMA_FROM_DEVICE;
458 desc->rd_len = 1;
459 }
460 break;
461
462 case I2C_SMBUS_BYTE_DATA:
463 if (read_write == I2C_SMBUS_WRITE) {
464 /*
465 * Write Byte
466 * Command plus 1 data byte
467 */
468 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: WRITE\n");
469 desc->wr_len_cmd = 2;
470 dma_size = 2;
471 dma_direction = DMA_TO_DEVICE;
472 dma_buffer[0] = command;
473 dma_buffer[1] = data->byte;
474 } else {
475 /* Read Byte */
476 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: READ\n");
477 desc->control |= ISMT_DESC_CWRL;
478 desc->wr_len_cmd = command;
479 desc->rd_len = 1;
480 dma_size = 1;
481 dma_direction = DMA_FROM_DEVICE;
482 }
483 break;
484
485 case I2C_SMBUS_WORD_DATA:
486 if (read_write == I2C_SMBUS_WRITE) {
487 /* Write Word */
488 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: WRITE\n");
489 desc->wr_len_cmd = 3;
490 dma_size = 3;
491 dma_direction = DMA_TO_DEVICE;
492 dma_buffer[0] = command;
493 dma_buffer[1] = data->word & 0xff;
494 dma_buffer[2] = data->word >> 8;
495 } else {
496 /* Read Word */
497 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: READ\n");
498 desc->wr_len_cmd = command;
499 desc->control |= ISMT_DESC_CWRL;
500 desc->rd_len = 2;
501 dma_size = 2;
502 dma_direction = DMA_FROM_DEVICE;
503 }
504 break;
505
506 case I2C_SMBUS_PROC_CALL:
507 dev_dbg(dev, "I2C_SMBUS_PROC_CALL\n");
508 desc->wr_len_cmd = 3;
509 desc->rd_len = 2;
510 dma_size = 3;
511 dma_direction = DMA_BIDIRECTIONAL;
512 dma_buffer[0] = command;
513 dma_buffer[1] = data->word & 0xff;
514 dma_buffer[2] = data->word >> 8;
515 break;
516
517 case I2C_SMBUS_BLOCK_DATA:
518 if (read_write == I2C_SMBUS_WRITE) {
519 /* Block Write */
520 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: WRITE\n");
521 if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
522 return -EINVAL;
523
524 dma_size = data->block[0] + 1;
525 dma_direction = DMA_TO_DEVICE;
526 desc->wr_len_cmd = dma_size;
527 desc->control |= ISMT_DESC_BLK;
528 dma_buffer[0] = command;
529 memcpy(&dma_buffer[1], &data->block[1], dma_size - 1);
530 } else {
531 /* Block Read */
532 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: READ\n");
533 dma_size = I2C_SMBUS_BLOCK_MAX;
534 dma_direction = DMA_FROM_DEVICE;
535 desc->rd_len = dma_size;
536 desc->wr_len_cmd = command;
537 desc->control |= (ISMT_DESC_BLK | ISMT_DESC_CWRL);
538 }
539 break;
540
541 case I2C_SMBUS_BLOCK_PROC_CALL:
542 dev_dbg(dev, "I2C_SMBUS_BLOCK_PROC_CALL\n");
543 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
544 return -EINVAL;
545
546 dma_size = I2C_SMBUS_BLOCK_MAX;
547 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, 1);
548 desc->wr_len_cmd = data->block[0] + 1;
549 desc->rd_len = dma_size;
550 desc->control |= ISMT_DESC_BLK;
551 dma_direction = DMA_BIDIRECTIONAL;
552 dma_buffer[0] = command;
553 memcpy(&dma_buffer[1], &data->block[1], data->block[0]);
554 break;
555
556 case I2C_SMBUS_I2C_BLOCK_DATA:
557 /* Make sure the length is valid */
558 if (data->block[0] < 1)
559 data->block[0] = 1;
560
561 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
562 data->block[0] = I2C_SMBUS_BLOCK_MAX;
563
564 if (read_write == I2C_SMBUS_WRITE) {
565 /* i2c Block Write */
566 dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: WRITE\n");
567 dma_size = data->block[0] + 1;
568 dma_direction = DMA_TO_DEVICE;
569 desc->wr_len_cmd = dma_size;
570 desc->control |= ISMT_DESC_I2C;
571 dma_buffer[0] = command;
572 memcpy(&dma_buffer[1], &data->block[1], dma_size - 1);
573 } else {
574 /* i2c Block Read */
575 dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: READ\n");
576 dma_size = data->block[0];
577 dma_direction = DMA_FROM_DEVICE;
578 desc->rd_len = dma_size;
579 desc->wr_len_cmd = command;
580 desc->control |= (ISMT_DESC_I2C | ISMT_DESC_CWRL);
581 /*
582 * Per the "Table 15-15. I2C Commands",
583 * in the External Design Specification (EDS),
584 * (Document Number: 508084, Revision: 2.0),
585 * the _rw bit must be 0
586 */
587 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, 0);
588 }
589 break;
590
591 default:
592 dev_err(dev, "Unsupported transaction %d\n",
593 size);
594 return -EOPNOTSUPP;
595 }
596
597 /* map the data buffer */
598 if (dma_size != 0) {
599 dev_dbg(dev, " dev=%p\n", dev);
600 dev_dbg(dev, " data=%p\n", data);
601 dev_dbg(dev, " dma_buffer=%p\n", dma_buffer);
602 dev_dbg(dev, " dma_size=%d\n", dma_size);
603 dev_dbg(dev, " dma_direction=%d\n", dma_direction);
604
605 dma_addr = dma_map_single(dev,
606 dma_buffer,
607 dma_size,
608 dma_direction);
609
610 if (dma_mapping_error(dev, dma_addr)) {
611 dev_err(dev, "Error in mapping dma buffer %p\n",
612 dma_buffer);
613 return -EIO;
614 }
615
616 dev_dbg(dev, " dma_addr = %pad\n", &dma_addr);
617
618 desc->dptr_low = lower_32_bits(dma_addr);
619 desc->dptr_high = upper_32_bits(dma_addr);
620 }
621
622 reinit_completion(&priv->cmp);
623
624 /* Add the descriptor */
625 ismt_submit_desc(priv);
626
627 /* Now we wait for interrupt completion, 1s */
628 time_left = wait_for_completion_timeout(&priv->cmp, HZ*1);
629
630 /* unmap the data buffer */
631 if (dma_size != 0)
632 dma_unmap_single(dev, dma_addr, dma_size, dma_direction);
633
634 if (unlikely(!time_left)) {
635 ismt_kill_transaction(priv);
636 ret = -ETIMEDOUT;
637 goto out;
638 }
639
640 /* do any post processing of the descriptor here */
641 ret = ismt_process_desc(desc, data, priv, size, read_write);
642
643 out:
644 /* Update the ring pointer */
645 priv->head++;
646 priv->head %= ISMT_DESC_ENTRIES;
647
648 return ret;
649 }
650
651 /**
652 * ismt_func() - report which i2c commands are supported by this adapter
653 * @adap: the i2c host adapter
654 */
655 static u32 ismt_func(struct i2c_adapter *adap)
656 {
657 return I2C_FUNC_SMBUS_QUICK |
658 I2C_FUNC_SMBUS_BYTE |
659 I2C_FUNC_SMBUS_BYTE_DATA |
660 I2C_FUNC_SMBUS_WORD_DATA |
661 I2C_FUNC_SMBUS_PROC_CALL |
662 I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
663 I2C_FUNC_SMBUS_BLOCK_DATA |
664 I2C_FUNC_SMBUS_I2C_BLOCK |
665 I2C_FUNC_SMBUS_PEC;
666 }
667
668 static const struct i2c_algorithm smbus_algorithm = {
669 .smbus_xfer = ismt_access,
670 .functionality = ismt_func,
671 };
672
673 /**
674 * ismt_handle_isr() - interrupt handler bottom half
675 * @priv: iSMT private data
676 */
677 static irqreturn_t ismt_handle_isr(struct ismt_priv *priv)
678 {
679 complete(&priv->cmp);
680
681 return IRQ_HANDLED;
682 }
683
684
685 /**
686 * ismt_do_interrupt() - IRQ interrupt handler
687 * @vec: interrupt vector
688 * @data: iSMT private data
689 */
690 static irqreturn_t ismt_do_interrupt(int vec, void *data)
691 {
692 u32 val;
693 struct ismt_priv *priv = data;
694
695 /*
696 * check to see it's our interrupt, return IRQ_NONE if not ours
697 * since we are sharing interrupt
698 */
699 val = readl(priv->smba + ISMT_MSTR_MSTS);
700
701 if (!(val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS)))
702 return IRQ_NONE;
703 else
704 writel(val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS,
705 priv->smba + ISMT_MSTR_MSTS);
706
707 return ismt_handle_isr(priv);
708 }
709
710 /**
711 * ismt_do_msi_interrupt() - MSI interrupt handler
712 * @vec: interrupt vector
713 * @data: iSMT private data
714 */
715 static irqreturn_t ismt_do_msi_interrupt(int vec, void *data)
716 {
717 return ismt_handle_isr(data);
718 }
719
720 /**
721 * ismt_hw_init() - initialize the iSMT hardware
722 * @priv: iSMT private data
723 */
724 static void ismt_hw_init(struct ismt_priv *priv)
725 {
726 u32 val;
727 struct device *dev = &priv->pci_dev->dev;
728
729 /* initialize the Master Descriptor Base Address (MDBA) */
730 writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA);
731
732 writeq(priv->log_dma, priv->smba + ISMT_GR_SMTICL);
733
734 /* initialize the Master Control Register (MCTRL) */
735 writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL);
736
737 /* initialize the Master Status Register (MSTS) */
738 writel(0, priv->smba + ISMT_MSTR_MSTS);
739
740 /* initialize the Master Descriptor Size (MDS) */
741 val = readl(priv->smba + ISMT_MSTR_MDS);
742 writel((val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1),
743 priv->smba + ISMT_MSTR_MDS);
744
745 /*
746 * Set the SMBus speed (could use this for slow HW debuggers)
747 */
748
749 val = readl(priv->smba + ISMT_SPGT);
750
751 switch (bus_speed) {
752 case 0:
753 break;
754
755 case 80:
756 dev_dbg(dev, "Setting SMBus clock to 80 kHz\n");
757 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K),
758 priv->smba + ISMT_SPGT);
759 break;
760
761 case 100:
762 dev_dbg(dev, "Setting SMBus clock to 100 kHz\n");
763 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K),
764 priv->smba + ISMT_SPGT);
765 break;
766
767 case 400:
768 dev_dbg(dev, "Setting SMBus clock to 400 kHz\n");
769 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K),
770 priv->smba + ISMT_SPGT);
771 break;
772
773 case 1000:
774 dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n");
775 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M),
776 priv->smba + ISMT_SPGT);
777 break;
778
779 default:
780 dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n");
781 break;
782 }
783
784 val = readl(priv->smba + ISMT_SPGT);
785
786 switch (val & ISMT_SPGT_SPD_MASK) {
787 case ISMT_SPGT_SPD_80K:
788 bus_speed = 80;
789 break;
790 case ISMT_SPGT_SPD_100K:
791 bus_speed = 100;
792 break;
793 case ISMT_SPGT_SPD_400K:
794 bus_speed = 400;
795 break;
796 case ISMT_SPGT_SPD_1M:
797 bus_speed = 1000;
798 break;
799 }
800 dev_dbg(dev, "SMBus clock is running at %d kHz\n", bus_speed);
801 }
802
803 /**
804 * ismt_dev_init() - initialize the iSMT data structures
805 * @priv: iSMT private data
806 */
807 static int ismt_dev_init(struct ismt_priv *priv)
808 {
809 /* allocate memory for the descriptor */
810 priv->hw = dmam_alloc_coherent(&priv->pci_dev->dev,
811 (ISMT_DESC_ENTRIES
812 * sizeof(struct ismt_desc)),
813 &priv->io_rng_dma,
814 GFP_KERNEL);
815 if (!priv->hw)
816 return -ENOMEM;
817
818 priv->head = 0;
819 init_completion(&priv->cmp);
820
821 priv->log = dmam_alloc_coherent(&priv->pci_dev->dev,
822 ISMT_LOG_ENTRIES * sizeof(u32),
823 &priv->log_dma, GFP_KERNEL);
824 if (!priv->log)
825 return -ENOMEM;
826
827 return 0;
828 }
829
830 /**
831 * ismt_int_init() - initialize interrupts
832 * @priv: iSMT private data
833 */
834 static int ismt_int_init(struct ismt_priv *priv)
835 {
836 int err;
837
838 /* Try using MSI interrupts */
839 err = pci_enable_msi(priv->pci_dev);
840 if (err)
841 goto intx;
842
843 err = devm_request_irq(&priv->pci_dev->dev,
844 priv->pci_dev->irq,
845 ismt_do_msi_interrupt,
846 0,
847 "ismt-msi",
848 priv);
849 if (err) {
850 pci_disable_msi(priv->pci_dev);
851 goto intx;
852 }
853
854 return 0;
855
856 /* Try using legacy interrupts */
857 intx:
858 dev_warn(&priv->pci_dev->dev,
859 "Unable to use MSI interrupts, falling back to legacy\n");
860
861 err = devm_request_irq(&priv->pci_dev->dev,
862 priv->pci_dev->irq,
863 ismt_do_interrupt,
864 IRQF_SHARED,
865 "ismt-intx",
866 priv);
867 if (err) {
868 dev_err(&priv->pci_dev->dev, "no usable interrupts\n");
869 return err;
870 }
871
872 return 0;
873 }
874
875 static struct pci_driver ismt_driver;
876
877 /**
878 * ismt_probe() - probe for iSMT devices
879 * @pdev: PCI-Express device
880 * @id: PCI-Express device ID
881 */
882 static int
883 ismt_probe(struct pci_dev *pdev, const struct pci_device_id *id)
884 {
885 int err;
886 struct ismt_priv *priv;
887 unsigned long start, len;
888
889 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
890 if (!priv)
891 return -ENOMEM;
892
893 pci_set_drvdata(pdev, priv);
894
895 i2c_set_adapdata(&priv->adapter, priv);
896 priv->adapter.owner = THIS_MODULE;
897 priv->adapter.class = I2C_CLASS_HWMON;
898 priv->adapter.algo = &smbus_algorithm;
899 priv->adapter.dev.parent = &pdev->dev;
900 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev));
901 priv->adapter.retries = ISMT_MAX_RETRIES;
902
903 priv->pci_dev = pdev;
904
905 err = pcim_enable_device(pdev);
906 if (err) {
907 dev_err(&pdev->dev, "Failed to enable SMBus PCI device (%d)\n",
908 err);
909 return err;
910 }
911
912 /* enable bus mastering */
913 pci_set_master(pdev);
914
915 /* Determine the address of the SMBus area */
916 start = pci_resource_start(pdev, SMBBAR);
917 len = pci_resource_len(pdev, SMBBAR);
918 if (!start || !len) {
919 dev_err(&pdev->dev,
920 "SMBus base address uninitialized, upgrade BIOS\n");
921 return -ENODEV;
922 }
923
924 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
925 "SMBus iSMT adapter at %lx", start);
926
927 dev_dbg(&priv->pci_dev->dev, " start=0x%lX\n", start);
928 dev_dbg(&priv->pci_dev->dev, " len=0x%lX\n", len);
929
930 err = acpi_check_resource_conflict(&pdev->resource[SMBBAR]);
931 if (err) {
932 dev_err(&pdev->dev, "ACPI resource conflict!\n");
933 return err;
934 }
935
936 err = pci_request_region(pdev, SMBBAR, ismt_driver.name);
937 if (err) {
938 dev_err(&pdev->dev,
939 "Failed to request SMBus region 0x%lx-0x%lx\n",
940 start, start + len);
941 return err;
942 }
943
944 priv->smba = pcim_iomap(pdev, SMBBAR, len);
945 if (!priv->smba) {
946 dev_err(&pdev->dev, "Unable to ioremap SMBus BAR\n");
947 return -ENODEV;
948 }
949
950 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
951 if (err) {
952 dev_err(&pdev->dev, "dma_set_mask fail\n");
953 return -ENODEV;
954 }
955
956 err = ismt_dev_init(priv);
957 if (err)
958 return err;
959
960 ismt_hw_init(priv);
961
962 err = ismt_int_init(priv);
963 if (err)
964 return err;
965
966 err = i2c_add_adapter(&priv->adapter);
967 if (err)
968 return -ENODEV;
969 return 0;
970 }
971
972 /**
973 * ismt_remove() - release driver resources
974 * @pdev: PCI-Express device
975 */
976 static void ismt_remove(struct pci_dev *pdev)
977 {
978 struct ismt_priv *priv = pci_get_drvdata(pdev);
979
980 i2c_del_adapter(&priv->adapter);
981 }
982
983 static struct pci_driver ismt_driver = {
984 .name = "ismt_smbus",
985 .id_table = ismt_ids,
986 .probe = ismt_probe,
987 .remove = ismt_remove,
988 };
989
990 module_pci_driver(ismt_driver);
991
992 MODULE_LICENSE("Dual BSD/GPL");
993 MODULE_AUTHOR("Bill E. Brown <bill.e.brown@intel.com>");
994 MODULE_DESCRIPTION("Intel SMBus Message Transport (iSMT) driver");
Kernel DRM miscellaneous fixes and cross-tree changes