drivers/i2c/busses/i2c-mlxcpld.c

   1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
   2 /*
   3  * Mellanox i2c driver
   4  *
   5  * Copyright (C) 2016-2020 Mellanox Technologies
   6  */
   7
   8 #include <linux/delay.h>
   9 #include <linux/i2c.h>
  10 #include <linux/init.h>
  11 #include <linux/io.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/platform_data/mlxreg.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/regmap.h>
  17
  18 /* General defines */
  19 #define MLXPLAT_CPLD_LPC_I2C_BASE_ADDR  0x2000
  20 #define MLXCPLD_I2C_DEVICE_NAME         "i2c_mlxcpld"
  21 #define MLXCPLD_I2C_VALID_FLAG          (I2C_M_RECV_LEN | I2C_M_RD)
  22 #define MLXCPLD_I2C_BUS_NUM             1
  23 #define MLXCPLD_I2C_DATA_REG_SZ         36
  24 #define MLXCPLD_I2C_DATA_SZ_BIT         BIT(5)
  25 #define MLXCPLD_I2C_DATA_EXT2_SZ_BIT    BIT(6)
  26 #define MLXCPLD_I2C_DATA_SZ_MASK        GENMASK(6, 5)
  27 #define MLXCPLD_I2C_SMBUS_BLK_BIT       BIT(7)
  28 #define MLXCPLD_I2C_MAX_ADDR_LEN        4
  29 #define MLXCPLD_I2C_RETR_NUM            2
  30 #define MLXCPLD_I2C_XFER_TO             500000 /* usec */
  31 #define MLXCPLD_I2C_POLL_TIME           200   /* usec */
  32
  33 /* LPC I2C registers */
  34 #define MLXCPLD_LPCI2C_CPBLTY_REG       0x0
  35 #define MLXCPLD_LPCI2C_CTRL_REG         0x1
  36 #define MLXCPLD_LPCI2C_HALF_CYC_REG     0x4
  37 #define MLXCPLD_LPCI2C_I2C_HOLD_REG     0x5
  38 #define MLXCPLD_LPCI2C_CMD_REG          0x6
  39 #define MLXCPLD_LPCI2C_NUM_DAT_REG      0x7
  40 #define MLXCPLD_LPCI2C_NUM_ADDR_REG     0x8
  41 #define MLXCPLD_LPCI2C_STATUS_REG       0x9
  42 #define MLXCPLD_LPCI2C_DATA_REG         0xa
  43
  44 /* LPC I2C masks and parameters */
  45 #define MLXCPLD_LPCI2C_RST_SEL_MASK     0x1
  46 #define MLXCPLD_LPCI2C_TRANS_END        0x1
  47 #define MLXCPLD_LPCI2C_STATUS_NACK      0x10
  48 #define MLXCPLD_LPCI2C_NO_IND           0
  49 #define MLXCPLD_LPCI2C_ACK_IND          1
  50 #define MLXCPLD_LPCI2C_NACK_IND         2
  51
  52 #define MLXCPLD_I2C_FREQ_1000KHZ_SET    0x04
  53 #define MLXCPLD_I2C_FREQ_400KHZ_SET     0x0e
  54 #define MLXCPLD_I2C_FREQ_100KHZ_SET     0x42
  55
  56 enum mlxcpld_i2c_frequency {
  57         MLXCPLD_I2C_FREQ_1000KHZ = 1,
  58         MLXCPLD_I2C_FREQ_400KHZ = 2,
  59         MLXCPLD_I2C_FREQ_100KHZ = 3,
  60 };
  61
  62 struct  mlxcpld_i2c_curr_xfer {
  63         u8 cmd;
  64         u8 addr_width;
  65         u8 data_len;
  66         u8 msg_num;
  67         struct i2c_msg *msg;
  68 };
  69
  70 struct mlxcpld_i2c_priv {
  71         struct i2c_adapter adap;
  72         u32 base_addr;
  73         struct mutex lock;
  74         struct  mlxcpld_i2c_curr_xfer xfer;
  75         struct device *dev;
  76         bool smbus_block;
  77         int polling_time;
  78 };
  79
  80 static void mlxcpld_i2c_lpc_write_buf(u8 *data, u8 len, u32 addr)
  81 {
  82         int i;
  83
  84         for (i = 0; i < len - len % 4; i += 4)
  85                 outl(*(u32 *)(data + i), addr + i);
  86         for (; i < len; ++i)
  87                 outb(*(data + i), addr + i);
  88 }
  89
  90 static void mlxcpld_i2c_lpc_read_buf(u8 *data, u8 len, u32 addr)
  91 {
  92         int i;
  93
  94         for (i = 0; i < len - len % 4; i += 4)
  95                 *(u32 *)(data + i) = inl(addr + i);
  96         for (; i < len; ++i)
  97                 *(data + i) = inb(addr + i);
  98 }
  99
 100 static void mlxcpld_i2c_read_comm(struct mlxcpld_i2c_priv *priv, u8 offs,
 101                                   u8 *data, u8 datalen)
 102 {
 103         u32 addr = priv->base_addr + offs;
 104
 105         switch (datalen) {
 106         case 1:
 107                 *(data) = inb(addr);
 108                 break;
 109         case 2:
 110                 *((u16 *)data) = inw(addr);
 111                 break;
 112         case 3:
 113                 *((u16 *)data) = inw(addr);
 114                 *(data + 2) = inb(addr + 2);
 115                 break;
 116         case 4:
 117                 *((u32 *)data) = inl(addr);
 118                 break;
 119         default:
 120                 mlxcpld_i2c_lpc_read_buf(data, datalen, addr);
 121                 break;
 122         }
 123 }
 124
 125 static void mlxcpld_i2c_write_comm(struct mlxcpld_i2c_priv *priv, u8 offs,
 126                                    u8 *data, u8 datalen)
 127 {
 128         u32 addr = priv->base_addr + offs;
 129
 130         switch (datalen) {
 131         case 1:
 132                 outb(*(data), addr);
 133                 break;
 134         case 2:
 135                 outw(*((u16 *)data), addr);
 136                 break;
 137         case 3:
 138                 outw(*((u16 *)data), addr);
 139                 outb(*(data + 2), addr + 2);
 140                 break;
 141         case 4:
 142                 outl(*((u32 *)data), addr);
 143                 break;
 144         default:
 145                 mlxcpld_i2c_lpc_write_buf(data, datalen, addr);
 146                 break;
 147         }
 148 }
 149
 150 /*
 151  * Check validity of received i2c messages parameters.
 152  * Returns 0 if OK, other - in case of invalid parameters.
 153  */
 154 static int mlxcpld_i2c_check_msg_params(struct mlxcpld_i2c_priv *priv,
 155                                         struct i2c_msg *msgs, int num)
 156 {
 157         int i;
 158
 159         if (!num) {
 160                 dev_err(priv->dev, "Incorrect 0 num of messages\n");
 161                 return -EINVAL;
 162         }
 163
 164         if (unlikely(msgs[0].addr > 0x7f)) {
 165                 dev_err(priv->dev, "Invalid address 0x%03x\n",
 166                         msgs[0].addr);
 167                 return -EINVAL;
 168         }
 169
 170         for (i = 0; i < num; ++i) {
 171                 if (unlikely(!msgs[i].buf)) {
 172                         dev_err(priv->dev, "Invalid buf in msg[%d]\n",
 173                                 i);
 174                         return -EINVAL;
 175                 }
 176                 if (unlikely(msgs[0].addr != msgs[i].addr)) {
 177                         dev_err(priv->dev, "Invalid addr in msg[%d]\n",
 178                                 i);
 179                         return -EINVAL;
 180                 }
 181         }
 182
 183         return 0;
 184 }
 185
 186 /*
 187  * Check if transfer is completed and status of operation.
 188  * Returns 0 - transfer completed (both ACK or NACK),
 189  * negative - transfer isn't finished.
 190  */
 191 static int mlxcpld_i2c_check_status(struct mlxcpld_i2c_priv *priv, int *status)
 192 {
 193         u8 val;
 194
 195         mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_STATUS_REG, &val, 1);
 196
 197         if (val & MLXCPLD_LPCI2C_TRANS_END) {
 198                 if (val & MLXCPLD_LPCI2C_STATUS_NACK)
 199                         /*
 200                          * The target is unable to accept the data. No such
 201                          * target, command not understood, or unable to accept
 202                          * any more data.
 203                          */
 204                         *status = MLXCPLD_LPCI2C_NACK_IND;
 205                 else
 206                         *status = MLXCPLD_LPCI2C_ACK_IND;
 207                 return 0;
 208         }
 209         *status = MLXCPLD_LPCI2C_NO_IND;
 210
 211         return -EIO;
 212 }
 213
 214 static void mlxcpld_i2c_set_transf_data(struct mlxcpld_i2c_priv *priv,
 215                                         struct i2c_msg *msgs, int num,
 216                                         u8 comm_len)
 217 {
 218         priv->xfer.msg = msgs;
 219         priv->xfer.msg_num = num;
 220
 221         /*
 222          * All upper layers currently are never use transfer with more than
 223          * 2 messages. Actually, it's also not so relevant in Mellanox systems
 224          * because of HW limitation. Max size of transfer is not more than 32
 225          * or 68 bytes in the current x86 LPCI2C bridge.
 226          */
 227         priv->xfer.cmd = msgs[num - 1].flags & I2C_M_RD;
 228
 229         if (priv->xfer.cmd == I2C_M_RD && comm_len != msgs[0].len) {
 230                 priv->xfer.addr_width = msgs[0].len;
 231                 priv->xfer.data_len = comm_len - priv->xfer.addr_width;
 232         } else {
 233                 priv->xfer.addr_width = 0;
 234                 priv->xfer.data_len = comm_len;
 235         }
 236 }
 237
 238 /* Reset CPLD LPCI2C block */
 239 static void mlxcpld_i2c_reset(struct mlxcpld_i2c_priv *priv)
 240 {
 241         u8 val;
 242
 243         mutex_lock(&priv->lock);
 244
 245         mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_CTRL_REG, &val, 1);
 246         val &= ~MLXCPLD_LPCI2C_RST_SEL_MASK;
 247         mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_CTRL_REG, &val, 1);
 248
 249         mutex_unlock(&priv->lock);
 250 }
 251
 252 /* Make sure the CPLD is ready to start transmitting. */
 253 static int mlxcpld_i2c_check_busy(struct mlxcpld_i2c_priv *priv)
 254 {
 255         u8 val;
 256
 257         mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_STATUS_REG, &val, 1);
 258
 259         if (val & MLXCPLD_LPCI2C_TRANS_END)
 260                 return 0;
 261
 262         return -EIO;
 263 }
 264
 265 static int mlxcpld_i2c_wait_for_free(struct mlxcpld_i2c_priv *priv)
 266 {
 267         int timeout = 0;
 268
 269         do {
 270                 if (!mlxcpld_i2c_check_busy(priv))
 271                         break;
 272                 usleep_range(priv->polling_time / 2, priv->polling_time);
 273                 timeout += priv->polling_time;
 274         } while (timeout <= MLXCPLD_I2C_XFER_TO);
 275
 276         if (timeout > MLXCPLD_I2C_XFER_TO)
 277                 return -ETIMEDOUT;
 278
 279         return 0;
 280 }
 281
 282 /*
 283  * Wait for transfer to complete.
 284  * It puts current process to sleep until we get interrupt or timeout expires.
 285  * Returns the number of transferred or read bytes or error (<0).
 286  */
 287 static int mlxcpld_i2c_wait_for_tc(struct mlxcpld_i2c_priv *priv)
 288 {
 289         int status, i, timeout = 0;
 290         u8 datalen, val;
 291
 292         do {
 293                 usleep_range(priv->polling_time / 2, priv->polling_time);
 294                 if (!mlxcpld_i2c_check_status(priv, &status))
 295                         break;
 296                 timeout += priv->polling_time;
 297         } while (status == 0 && timeout < MLXCPLD_I2C_XFER_TO);
 298
 299         switch (status) {
 300         case MLXCPLD_LPCI2C_NO_IND:
 301                 return -ETIMEDOUT;
 302
 303         case MLXCPLD_LPCI2C_ACK_IND:
 304                 if (priv->xfer.cmd != I2C_M_RD)
 305                         return (priv->xfer.addr_width + priv->xfer.data_len);
 306
 307                 if (priv->xfer.msg_num == 1)
 308                         i = 0;
 309                 else
 310                         i = 1;
 311
 312                 if (!priv->xfer.msg[i].buf)
 313                         return -EINVAL;
 314
 315                 /*
 316                  * Actual read data len will be always the same as
 317                  * requested len. 0xff (line pull-up) will be returned
 318                  * if target has no data to return. Thus don't read
 319                  * MLXCPLD_LPCI2C_NUM_DAT_REG reg from CPLD.  Only in case of
 320                  * SMBus block read transaction data len can be different,
 321                  * check this case.
 322                  */
 323                 mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_NUM_ADDR_REG, &val,
 324                                       1);
 325                 if (priv->smbus_block && (val & MLXCPLD_I2C_SMBUS_BLK_BIT)) {
 326                         mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_NUM_DAT_REG,
 327                                               &datalen, 1);
 328                         if (unlikely(datalen > I2C_SMBUS_BLOCK_MAX)) {
 329                                 dev_err(priv->dev, "Incorrect smbus block read message len\n");
 330                                 return -EPROTO;
 331                         }
 332                 } else {
 333                         datalen = priv->xfer.data_len;
 334                 }
 335
 336                 mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_DATA_REG,
 337                                       priv->xfer.msg[i].buf, datalen);
 338
 339                 return datalen;
 340
 341         case MLXCPLD_LPCI2C_NACK_IND:
 342                 return -ENXIO;
 343
 344         default:
 345                 return -EINVAL;
 346         }
 347 }
 348
 349 static void mlxcpld_i2c_xfer_msg(struct mlxcpld_i2c_priv *priv)
 350 {
 351         int i, len = 0;
 352         u8 cmd, val;
 353
 354         mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_NUM_DAT_REG,
 355                                &priv->xfer.data_len, 1);
 356
 357         val = priv->xfer.addr_width;
 358         /* Notify HW about SMBus block read transaction */
 359         if (priv->smbus_block && priv->xfer.msg_num >= 2 &&
 360             priv->xfer.msg[1].len == 1 &&
 361             (priv->xfer.msg[1].flags & I2C_M_RECV_LEN) &&
 362             (priv->xfer.msg[1].flags & I2C_M_RD))
 363                 val |= MLXCPLD_I2C_SMBUS_BLK_BIT;
 364
 365         mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_NUM_ADDR_REG, &val, 1);
 366
 367         for (i = 0; i < priv->xfer.msg_num; i++) {
 368                 if ((priv->xfer.msg[i].flags & I2C_M_RD) != I2C_M_RD) {
 369                         /* Don't write to CPLD buffer in read transaction */
 370                         mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_DATA_REG +
 371                                                len, priv->xfer.msg[i].buf,
 372                                                priv->xfer.msg[i].len);
 373                         len += priv->xfer.msg[i].len;
 374                 }
 375         }
 376
 377         /*
 378          * Set target address with command for transfer.
 379          * It should be latest executed function before CPLD transaction.
 380          */
 381         cmd = (priv->xfer.msg[0].addr << 1) | priv->xfer.cmd;
 382         mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_CMD_REG, &cmd, 1);
 383 }
 384
 385 /*
 386  * Generic lpc-i2c transfer.
 387  * Returns the number of processed messages or error (<0).
 388  */
 389 static int mlxcpld_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
 390                             int num)
 391 {
 392         struct mlxcpld_i2c_priv *priv = i2c_get_adapdata(adap);
 393         u8 comm_len = 0;
 394         int i, err;
 395
 396         err = mlxcpld_i2c_check_msg_params(priv, msgs, num);
 397         if (err) {
 398                 dev_err(priv->dev, "Incorrect message\n");
 399                 return err;
 400         }
 401
 402         for (i = 0; i < num; ++i)
 403                 comm_len += msgs[i].len;
 404
 405         /* Check bus state */
 406         if (mlxcpld_i2c_wait_for_free(priv)) {
 407                 dev_err(priv->dev, "LPCI2C bridge is busy\n");
 408
 409                 /*
 410                  * Usually it means something serious has happened.
 411                  * We can not have unfinished previous transfer
 412                  * so it doesn't make any sense to try to stop it.
 413                  * Probably we were not able to recover from the
 414                  * previous error.
 415                  * The only reasonable thing - is soft reset.
 416                  */
 417                 mlxcpld_i2c_reset(priv);
 418                 if (mlxcpld_i2c_check_busy(priv)) {
 419                         dev_err(priv->dev, "LPCI2C bridge is busy after reset\n");
 420                         return -EIO;
 421                 }
 422         }
 423
 424         mlxcpld_i2c_set_transf_data(priv, msgs, num, comm_len);
 425
 426         mutex_lock(&priv->lock);
 427
 428         /* Do real transfer. Can't fail */
 429         mlxcpld_i2c_xfer_msg(priv);
 430
 431         /* Wait for transaction complete */
 432         err = mlxcpld_i2c_wait_for_tc(priv);
 433
 434         mutex_unlock(&priv->lock);
 435
 436         return err < 0 ? err : num;
 437 }
 438
 439 static u32 mlxcpld_i2c_func(struct i2c_adapter *adap)
 440 {
 441         struct mlxcpld_i2c_priv *priv = i2c_get_adapdata(adap);
 442
 443         if (priv->smbus_block)
 444                 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
 445                         I2C_FUNC_SMBUS_I2C_BLOCK | I2C_FUNC_SMBUS_BLOCK_DATA;
 446         else
 447                 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
 448                         I2C_FUNC_SMBUS_I2C_BLOCK;
 449 }
 450
 451 static const struct i2c_algorithm mlxcpld_i2c_algo = {
 452         .xfer = mlxcpld_i2c_xfer,
 453         .functionality = mlxcpld_i2c_func
 454 };
 455
 456 static const struct i2c_adapter_quirks mlxcpld_i2c_quirks = {
 457         .flags = I2C_AQ_COMB_WRITE_THEN_READ,
 458         .max_read_len = MLXCPLD_I2C_DATA_REG_SZ - MLXCPLD_I2C_MAX_ADDR_LEN,
 459         .max_write_len = MLXCPLD_I2C_DATA_REG_SZ,
 460         .max_comb_1st_msg_len = 4,
 461 };
 462
 463 static const struct i2c_adapter_quirks mlxcpld_i2c_quirks_ext = {
 464         .flags = I2C_AQ_COMB_WRITE_THEN_READ,
 465         .max_read_len = MLXCPLD_I2C_DATA_REG_SZ * 2 - MLXCPLD_I2C_MAX_ADDR_LEN,
 466         .max_write_len = MLXCPLD_I2C_DATA_REG_SZ * 2,
 467         .max_comb_1st_msg_len = 4,
 468 };
 469
 470 static const struct i2c_adapter_quirks mlxcpld_i2c_quirks_ext2 = {
 471         .flags = I2C_AQ_COMB_WRITE_THEN_READ,
 472         .max_read_len = (MLXCPLD_I2C_DATA_REG_SZ - 4) * 4,
 473         .max_write_len = (MLXCPLD_I2C_DATA_REG_SZ - 4) * 4 + MLXCPLD_I2C_MAX_ADDR_LEN,
 474         .max_comb_1st_msg_len = 4,
 475 };
 476
 477 static struct i2c_adapter mlxcpld_i2c_adapter = {
 478         .owner          = THIS_MODULE,
 479         .name           = "i2c-mlxcpld",
 480         .class          = I2C_CLASS_HWMON,
 481         .algo           = &mlxcpld_i2c_algo,
 482         .quirks         = &mlxcpld_i2c_quirks,
 483         .retries        = MLXCPLD_I2C_RETR_NUM,
 484         .nr             = MLXCPLD_I2C_BUS_NUM,
 485 };
 486
 487 static int
 488 mlxcpld_i2c_set_frequency(struct mlxcpld_i2c_priv *priv,
 489                           struct mlxreg_core_hotplug_platform_data *pdata)
 490 {
 491         struct mlxreg_core_item *item = pdata->items;
 492         struct mlxreg_core_data *data;
 493         u32 regval;
 494         u8 freq;
 495         int err;
 496
 497         if (!item)
 498                 return 0;
 499
 500         /* Read frequency setting. */
 501         data = item->data;
 502         err = regmap_read(pdata->regmap, data->reg, &regval);
 503         if (err)
 504                 return err;
 505
 506         /* Set frequency only if it is not 100KHz, which is default. */
 507         switch ((regval & data->mask) >> data->bit) {
 508         case MLXCPLD_I2C_FREQ_1000KHZ:
 509                 freq = MLXCPLD_I2C_FREQ_1000KHZ_SET;
 510                 priv->polling_time /= 4;
 511                 break;
 512         case MLXCPLD_I2C_FREQ_400KHZ:
 513                 freq = MLXCPLD_I2C_FREQ_400KHZ_SET;
 514                 priv->polling_time /= 4;
 515                 break;
 516         default:
 517                 return 0;
 518         }
 519
 520         mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_HALF_CYC_REG, &freq, 1);
 521
 522         return 0;
 523 }
 524
 525 static int mlxcpld_i2c_probe(struct platform_device *pdev)
 526 {
 527         struct mlxreg_core_hotplug_platform_data *pdata;
 528         struct mlxcpld_i2c_priv *priv;
 529         int err;
 530         u8 val;
 531
 532         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 533         if (!priv)
 534                 return -ENOMEM;
 535
 536         mutex_init(&priv->lock);
 537         platform_set_drvdata(pdev, priv);
 538
 539         priv->dev = &pdev->dev;
 540         priv->base_addr = MLXPLAT_CPLD_LPC_I2C_BASE_ADDR;
 541         priv->polling_time = MLXCPLD_I2C_POLL_TIME;
 542
 543         /* Set I2C bus frequency if platform data provides this info. */
 544         pdata = dev_get_platdata(&pdev->dev);
 545         if (pdata) {
 546                 err = mlxcpld_i2c_set_frequency(priv, pdata);
 547                 if (err)
 548                         goto mlxcpld_i2_probe_failed;
 549         }
 550
 551         /* Register with i2c layer */
 552         mlxcpld_i2c_adapter.timeout = usecs_to_jiffies(MLXCPLD_I2C_XFER_TO);
 553         /* Read capability register */
 554         mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_CPBLTY_REG, &val, 1);
 555         /* Check support for extended transaction length */
 556         if ((val & MLXCPLD_I2C_DATA_SZ_MASK) == MLXCPLD_I2C_DATA_SZ_BIT)
 557                 mlxcpld_i2c_adapter.quirks = &mlxcpld_i2c_quirks_ext;
 558         else if ((val & MLXCPLD_I2C_DATA_SZ_MASK) == MLXCPLD_I2C_DATA_EXT2_SZ_BIT)
 559                 mlxcpld_i2c_adapter.quirks = &mlxcpld_i2c_quirks_ext2;
 560         /* Check support for smbus block transaction */
 561         if (val & MLXCPLD_I2C_SMBUS_BLK_BIT)
 562                 priv->smbus_block = true;
 563         if (pdev->id >= -1)
 564                 mlxcpld_i2c_adapter.nr = pdev->id;
 565         priv->adap = mlxcpld_i2c_adapter;
 566         priv->adap.dev.parent = &pdev->dev;
 567         i2c_set_adapdata(&priv->adap, priv);
 568
 569         err = i2c_add_numbered_adapter(&priv->adap);
 570         if (err)
 571                 goto mlxcpld_i2_probe_failed;
 572
 573         /* Notify caller when adapter is added. */
 574         if (pdata && pdata->completion_notify)
 575                 pdata->completion_notify(pdata->handle, mlxcpld_i2c_adapter.nr);
 576
 577         return 0;
 578
 579 mlxcpld_i2_probe_failed:
 580         mutex_destroy(&priv->lock);
 581         return err;
 582 }
 583
 584 static void mlxcpld_i2c_remove(struct platform_device *pdev)
 585 {
 586         struct mlxcpld_i2c_priv *priv = platform_get_drvdata(pdev);
 587
 588         i2c_del_adapter(&priv->adap);
 589         mutex_destroy(&priv->lock);
 590 }
 591
 592 static struct platform_driver mlxcpld_i2c_driver = {
 593         .probe          = mlxcpld_i2c_probe,
 594         .remove_new     = mlxcpld_i2c_remove,
 595         .driver = {
 596                 .name = MLXCPLD_I2C_DEVICE_NAME,
 597         },
 598 };
 599
 600 module_platform_driver(mlxcpld_i2c_driver);
 601
 602 MODULE_AUTHOR("Michael Shych <michaels@mellanox.com>");
 603 MODULE_DESCRIPTION("Mellanox I2C-CPLD controller driver");
 604 MODULE_LICENSE("Dual BSD/GPL");
 605 MODULE_ALIAS("platform:i2c-mlxcpld");