1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Actions Semiconductor Owl SoC's I2C driver
5 * Copyright (c) 2014 Actions Semi Inc.
6 * Author: David Liu <liuwei@actions-semi.com>
8 * Copyright (c) 2018 Linaro Ltd.
9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/i2c.h>
15 #include <linux/interrupt.h>
17 #include <linux/iopoll.h>
18 #include <linux/module.h>
20 #include <linux/platform_device.h>
23 #define OWL_I2C_REG_CTL 0x0000
24 #define OWL_I2C_REG_CLKDIV 0x0004
25 #define OWL_I2C_REG_STAT 0x0008
26 #define OWL_I2C_REG_ADDR 0x000C
27 #define OWL_I2C_REG_TXDAT 0x0010
28 #define OWL_I2C_REG_RXDAT 0x0014
29 #define OWL_I2C_REG_CMD 0x0018
30 #define OWL_I2C_REG_FIFOCTL 0x001C
31 #define OWL_I2C_REG_FIFOSTAT 0x0020
32 #define OWL_I2C_REG_DATCNT 0x0024
33 #define OWL_I2C_REG_RCNT 0x0028
35 /* I2Cx_CTL Bit Mask */
36 #define OWL_I2C_CTL_RB BIT(1)
37 #define OWL_I2C_CTL_GBCC(x) (((x) & 0x3) << 2)
38 #define OWL_I2C_CTL_GBCC_NONE OWL_I2C_CTL_GBCC(0)
39 #define OWL_I2C_CTL_GBCC_START OWL_I2C_CTL_GBCC(1)
40 #define OWL_I2C_CTL_GBCC_STOP OWL_I2C_CTL_GBCC(2)
41 #define OWL_I2C_CTL_GBCC_RSTART OWL_I2C_CTL_GBCC(3)
42 #define OWL_I2C_CTL_IRQE BIT(5)
43 #define OWL_I2C_CTL_EN BIT(7)
44 #define OWL_I2C_CTL_AE BIT(8)
45 #define OWL_I2C_CTL_SHSM BIT(10)
47 #define OWL_I2C_DIV_FACTOR(x) ((x) & 0xff)
49 /* I2Cx_STAT Bit Mask */
50 #define OWL_I2C_STAT_RACK BIT(0)
51 #define OWL_I2C_STAT_BEB BIT(1)
52 #define OWL_I2C_STAT_IRQP BIT(2)
53 #define OWL_I2C_STAT_LAB BIT(3)
54 #define OWL_I2C_STAT_STPD BIT(4)
55 #define OWL_I2C_STAT_STAD BIT(5)
56 #define OWL_I2C_STAT_BBB BIT(6)
57 #define OWL_I2C_STAT_TCB BIT(7)
58 #define OWL_I2C_STAT_LBST BIT(8)
59 #define OWL_I2C_STAT_SAMB BIT(9)
60 #define OWL_I2C_STAT_SRGC BIT(10)
62 /* I2Cx_CMD Bit Mask */
63 #define OWL_I2C_CMD_SBE BIT(0)
64 #define OWL_I2C_CMD_RBE BIT(4)
65 #define OWL_I2C_CMD_DE BIT(8)
66 #define OWL_I2C_CMD_NS BIT(9)
67 #define OWL_I2C_CMD_SE BIT(10)
68 #define OWL_I2C_CMD_MSS BIT(11)
69 #define OWL_I2C_CMD_WRS BIT(12)
70 #define OWL_I2C_CMD_SECL BIT(15)
72 #define OWL_I2C_CMD_AS(x) (((x) & 0x7) << 1)
73 #define OWL_I2C_CMD_SAS(x) (((x) & 0x7) << 5)
75 /* I2Cx_FIFOCTL Bit Mask */
76 #define OWL_I2C_FIFOCTL_NIB BIT(0)
77 #define OWL_I2C_FIFOCTL_RFR BIT(1)
78 #define OWL_I2C_FIFOCTL_TFR BIT(2)
80 /* I2Cc_FIFOSTAT Bit Mask */
81 #define OWL_I2C_FIFOSTAT_CECB BIT(0)
82 #define OWL_I2C_FIFOSTAT_RNB BIT(1)
83 #define OWL_I2C_FIFOSTAT_RFE BIT(2)
84 #define OWL_I2C_FIFOSTAT_TFF BIT(5)
85 #define OWL_I2C_FIFOSTAT_TFD GENMASK(23, 16)
86 #define OWL_I2C_FIFOSTAT_RFD GENMASK(15, 8)
89 #define OWL_I2C_TIMEOUT_MS (4 * 1000)
90 #define OWL_I2C_TIMEOUT msecs_to_jiffies(OWL_I2C_TIMEOUT_MS)
92 #define OWL_I2C_MAX_RETRIES 50
95 struct i2c_adapter adap
;
97 struct completion msg_complete
;
101 unsigned long clk_rate
;
107 static void owl_i2c_update_reg(void __iomem
*reg
, unsigned int val
, bool state
)
121 static void owl_i2c_reset(struct owl_i2c_dev
*i2c_dev
)
123 owl_i2c_update_reg(i2c_dev
->base
+ OWL_I2C_REG_CTL
,
124 OWL_I2C_CTL_EN
, false);
126 owl_i2c_update_reg(i2c_dev
->base
+ OWL_I2C_REG_CTL
,
127 OWL_I2C_CTL_EN
, true);
129 /* Clear status registers */
130 writel(0, i2c_dev
->base
+ OWL_I2C_REG_STAT
);
133 static int owl_i2c_reset_fifo(struct owl_i2c_dev
*i2c_dev
)
135 unsigned int val
, timeout
= 0;
138 owl_i2c_update_reg(i2c_dev
->base
+ OWL_I2C_REG_FIFOCTL
,
139 OWL_I2C_FIFOCTL_RFR
| OWL_I2C_FIFOCTL_TFR
,
142 /* Wait 50ms for FIFO reset complete */
144 val
= readl(i2c_dev
->base
+ OWL_I2C_REG_FIFOCTL
);
145 if (!(val
& (OWL_I2C_FIFOCTL_RFR
| OWL_I2C_FIFOCTL_TFR
)))
147 usleep_range(500, 1000);
148 } while (timeout
++ < OWL_I2C_MAX_RETRIES
);
150 if (timeout
> OWL_I2C_MAX_RETRIES
) {
151 dev_err(&i2c_dev
->adap
.dev
, "FIFO reset timeout\n");
158 static void owl_i2c_set_freq(struct owl_i2c_dev
*i2c_dev
)
162 val
= DIV_ROUND_UP(i2c_dev
->clk_rate
, i2c_dev
->bus_freq
* 16);
164 /* Set clock divider factor */
165 writel(OWL_I2C_DIV_FACTOR(val
), i2c_dev
->base
+ OWL_I2C_REG_CLKDIV
);
168 static void owl_i2c_xfer_data(struct owl_i2c_dev
*i2c_dev
)
170 struct i2c_msg
*msg
= i2c_dev
->msg
;
171 unsigned int stat
, fifostat
;
175 /* Handle NACK from target */
176 fifostat
= readl(i2c_dev
->base
+ OWL_I2C_REG_FIFOSTAT
);
177 if (fifostat
& OWL_I2C_FIFOSTAT_RNB
) {
178 i2c_dev
->err
= -ENXIO
;
179 /* Clear NACK error bit by writing "1" */
180 owl_i2c_update_reg(i2c_dev
->base
+ OWL_I2C_REG_FIFOSTAT
,
181 OWL_I2C_FIFOSTAT_RNB
, true);
185 /* Handle bus error */
186 stat
= readl(i2c_dev
->base
+ OWL_I2C_REG_STAT
);
187 if (stat
& OWL_I2C_STAT_BEB
) {
189 /* Clear BUS error bit by writing "1" */
190 owl_i2c_update_reg(i2c_dev
->base
+ OWL_I2C_REG_STAT
,
191 OWL_I2C_STAT_BEB
, true);
195 /* Handle FIFO read */
196 if (msg
->flags
& I2C_M_RD
) {
197 while ((readl(i2c_dev
->base
+ OWL_I2C_REG_FIFOSTAT
) &
198 OWL_I2C_FIFOSTAT_RFE
) && i2c_dev
->msg_ptr
< msg
->len
) {
199 msg
->buf
[i2c_dev
->msg_ptr
++] = readl(i2c_dev
->base
+
203 /* Handle the remaining bytes which were not sent */
204 while (!(readl(i2c_dev
->base
+ OWL_I2C_REG_FIFOSTAT
) &
205 OWL_I2C_FIFOSTAT_TFF
) && i2c_dev
->msg_ptr
< msg
->len
) {
206 writel(msg
->buf
[i2c_dev
->msg_ptr
++],
207 i2c_dev
->base
+ OWL_I2C_REG_TXDAT
);
212 static irqreturn_t
owl_i2c_interrupt(int irq
, void *_dev
)
214 struct owl_i2c_dev
*i2c_dev
= _dev
;
216 spin_lock(&i2c_dev
->lock
);
218 owl_i2c_xfer_data(i2c_dev
);
220 /* Clear pending interrupts */
221 owl_i2c_update_reg(i2c_dev
->base
+ OWL_I2C_REG_STAT
,
222 OWL_I2C_STAT_IRQP
, true);
224 complete_all(&i2c_dev
->msg_complete
);
225 spin_unlock(&i2c_dev
->lock
);
230 static u32
owl_i2c_func(struct i2c_adapter
*adap
)
232 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
235 static int owl_i2c_check_bus_busy(struct i2c_adapter
*adap
)
237 struct owl_i2c_dev
*i2c_dev
= i2c_get_adapdata(adap
);
238 unsigned long timeout
;
240 /* Check for Bus busy */
241 timeout
= jiffies
+ OWL_I2C_TIMEOUT
;
242 while (readl(i2c_dev
->base
+ OWL_I2C_REG_STAT
) & OWL_I2C_STAT_BBB
) {
243 if (time_after(jiffies
, timeout
)) {
244 dev_err(&adap
->dev
, "Bus busy timeout\n");
252 static int owl_i2c_xfer_common(struct i2c_adapter
*adap
, struct i2c_msg
*msgs
,
253 int num
, bool atomic
)
255 struct owl_i2c_dev
*i2c_dev
= i2c_get_adapdata(adap
);
257 unsigned long time_left
, flags
;
258 unsigned int i2c_cmd
, val
;
262 spin_lock_irqsave(&i2c_dev
->lock
, flags
);
264 /* Reset I2C controller */
265 owl_i2c_reset(i2c_dev
);
267 /* Set bus frequency */
268 owl_i2c_set_freq(i2c_dev
);
271 * Spinlock should be released before calling reset FIFO and
272 * bus busy check since those functions may sleep
274 spin_unlock_irqrestore(&i2c_dev
->lock
, flags
);
277 ret
= owl_i2c_reset_fifo(i2c_dev
);
279 goto unlocked_err_exit
;
281 /* Check for bus busy */
282 ret
= owl_i2c_check_bus_busy(adap
);
284 goto unlocked_err_exit
;
286 spin_lock_irqsave(&i2c_dev
->lock
, flags
);
288 /* Check for Arbitration lost */
289 val
= readl(i2c_dev
->base
+ OWL_I2C_REG_STAT
);
290 if (val
& OWL_I2C_STAT_LAB
) {
291 val
&= ~OWL_I2C_STAT_LAB
;
292 writel(val
, i2c_dev
->base
+ OWL_I2C_REG_STAT
);
298 reinit_completion(&i2c_dev
->msg_complete
);
300 /* Enable/disable I2C controller interrupt */
301 owl_i2c_update_reg(i2c_dev
->base
+ OWL_I2C_REG_CTL
,
302 OWL_I2C_CTL_IRQE
, !atomic
);
305 * Select: FIFO enable, controller mode, Stop enable, Data count enable,
308 i2c_cmd
= OWL_I2C_CMD_SECL
| OWL_I2C_CMD_MSS
| OWL_I2C_CMD_SE
|
309 OWL_I2C_CMD_NS
| OWL_I2C_CMD_DE
| OWL_I2C_CMD_SBE
;
311 /* Handle repeated start condition */
313 /* Set internal address length and enable repeated start */
314 i2c_cmd
|= OWL_I2C_CMD_AS(msgs
[0].len
+ 1) |
315 OWL_I2C_CMD_SAS(1) | OWL_I2C_CMD_RBE
;
317 /* Write target address */
318 addr
= i2c_8bit_addr_from_msg(&msgs
[0]);
319 writel(addr
, i2c_dev
->base
+ OWL_I2C_REG_TXDAT
);
321 /* Write internal register address */
322 for (idx
= 0; idx
< msgs
[0].len
; idx
++)
323 writel(msgs
[0].buf
[idx
],
324 i2c_dev
->base
+ OWL_I2C_REG_TXDAT
);
328 /* Set address length */
329 i2c_cmd
|= OWL_I2C_CMD_AS(1);
334 i2c_dev
->msg_ptr
= 0;
336 /* Set data count for the message */
337 writel(msg
->len
, i2c_dev
->base
+ OWL_I2C_REG_DATCNT
);
339 addr
= i2c_8bit_addr_from_msg(msg
);
340 writel(addr
, i2c_dev
->base
+ OWL_I2C_REG_TXDAT
);
342 if (!(msg
->flags
& I2C_M_RD
)) {
343 /* Write data to FIFO */
344 for (idx
= 0; idx
< msg
->len
; idx
++) {
345 /* Check for FIFO full */
346 if (readl(i2c_dev
->base
+ OWL_I2C_REG_FIFOSTAT
) &
347 OWL_I2C_FIFOSTAT_TFF
)
350 writel(msg
->buf
[idx
],
351 i2c_dev
->base
+ OWL_I2C_REG_TXDAT
);
354 i2c_dev
->msg_ptr
= idx
;
357 /* Ignore the NACK if needed */
358 if (msg
->flags
& I2C_M_IGNORE_NAK
)
359 owl_i2c_update_reg(i2c_dev
->base
+ OWL_I2C_REG_FIFOCTL
,
360 OWL_I2C_FIFOCTL_NIB
, true);
362 owl_i2c_update_reg(i2c_dev
->base
+ OWL_I2C_REG_FIFOCTL
,
363 OWL_I2C_FIFOCTL_NIB
, false);
365 /* Start the transfer */
366 writel(i2c_cmd
, i2c_dev
->base
+ OWL_I2C_REG_CMD
);
368 spin_unlock_irqrestore(&i2c_dev
->lock
, flags
);
371 /* Wait for Command Execute Completed or NACK Error bits */
372 ret
= readl_poll_timeout_atomic(i2c_dev
->base
+ OWL_I2C_REG_FIFOSTAT
,
373 val
, val
& (OWL_I2C_FIFOSTAT_CECB
|
374 OWL_I2C_FIFOSTAT_RNB
),
375 10, OWL_I2C_TIMEOUT_MS
* 1000);
377 time_left
= wait_for_completion_timeout(&i2c_dev
->msg_complete
,
383 spin_lock_irqsave(&i2c_dev
->lock
, flags
);
386 dev_err(&adap
->dev
, "Transaction timed out\n");
387 /* Send stop condition and release the bus */
388 owl_i2c_update_reg(i2c_dev
->base
+ OWL_I2C_REG_CTL
,
389 OWL_I2C_CTL_GBCC_STOP
| OWL_I2C_CTL_RB
,
395 owl_i2c_xfer_data(i2c_dev
);
397 ret
= i2c_dev
->err
< 0 ? i2c_dev
->err
: num
;
400 spin_unlock_irqrestore(&i2c_dev
->lock
, flags
);
403 /* Disable I2C controller */
404 owl_i2c_update_reg(i2c_dev
->base
+ OWL_I2C_REG_CTL
,
405 OWL_I2C_CTL_EN
, false);
410 static int owl_i2c_xfer(struct i2c_adapter
*adap
, struct i2c_msg
*msgs
,
413 return owl_i2c_xfer_common(adap
, msgs
, num
, false);
416 static int owl_i2c_xfer_atomic(struct i2c_adapter
*adap
,
417 struct i2c_msg
*msgs
, int num
)
419 return owl_i2c_xfer_common(adap
, msgs
, num
, true);
422 static const struct i2c_algorithm owl_i2c_algorithm
= {
423 .xfer
= owl_i2c_xfer
,
424 .xfer_atomic
= owl_i2c_xfer_atomic
,
425 .functionality
= owl_i2c_func
,
428 static const struct i2c_adapter_quirks owl_i2c_quirks
= {
429 .flags
= I2C_AQ_COMB
| I2C_AQ_COMB_WRITE_FIRST
,
431 .max_write_len
= 240,
432 .max_comb_1st_msg_len
= 6,
433 .max_comb_2nd_msg_len
= 240,
436 static int owl_i2c_probe(struct platform_device
*pdev
)
438 struct device
*dev
= &pdev
->dev
;
439 struct owl_i2c_dev
*i2c_dev
;
442 i2c_dev
= devm_kzalloc(dev
, sizeof(*i2c_dev
), GFP_KERNEL
);
446 i2c_dev
->base
= devm_platform_ioremap_resource(pdev
, 0);
447 if (IS_ERR(i2c_dev
->base
))
448 return PTR_ERR(i2c_dev
->base
);
450 irq
= platform_get_irq(pdev
, 0);
454 if (of_property_read_u32(dev
->of_node
, "clock-frequency",
456 i2c_dev
->bus_freq
= I2C_MAX_STANDARD_MODE_FREQ
;
458 /* We support only frequencies of 100k and 400k for now */
459 if (i2c_dev
->bus_freq
!= I2C_MAX_STANDARD_MODE_FREQ
&&
460 i2c_dev
->bus_freq
!= I2C_MAX_FAST_MODE_FREQ
) {
461 dev_err(dev
, "invalid clock-frequency %d\n", i2c_dev
->bus_freq
);
465 i2c_dev
->clk
= devm_clk_get_enabled(dev
, NULL
);
466 if (IS_ERR(i2c_dev
->clk
)) {
467 dev_err(dev
, "failed to enable clock\n");
468 return PTR_ERR(i2c_dev
->clk
);
471 i2c_dev
->clk_rate
= clk_get_rate(i2c_dev
->clk
);
472 if (!i2c_dev
->clk_rate
) {
473 dev_err(dev
, "input clock rate should not be zero\n");
477 init_completion(&i2c_dev
->msg_complete
);
478 spin_lock_init(&i2c_dev
->lock
);
479 i2c_dev
->adap
.owner
= THIS_MODULE
;
480 i2c_dev
->adap
.algo
= &owl_i2c_algorithm
;
481 i2c_dev
->adap
.timeout
= OWL_I2C_TIMEOUT
;
482 i2c_dev
->adap
.quirks
= &owl_i2c_quirks
;
483 i2c_dev
->adap
.dev
.parent
= dev
;
484 i2c_dev
->adap
.dev
.of_node
= dev
->of_node
;
485 snprintf(i2c_dev
->adap
.name
, sizeof(i2c_dev
->adap
.name
),
486 "%s", "OWL I2C adapter");
487 i2c_set_adapdata(&i2c_dev
->adap
, i2c_dev
);
489 platform_set_drvdata(pdev
, i2c_dev
);
491 ret
= devm_request_irq(dev
, irq
, owl_i2c_interrupt
, 0, pdev
->name
,
494 dev_err(dev
, "failed to request irq %d\n", irq
);
498 return i2c_add_adapter(&i2c_dev
->adap
);
501 static const struct of_device_id owl_i2c_of_match
[] = {
502 { .compatible
= "actions,s500-i2c" },
503 { .compatible
= "actions,s700-i2c" },
504 { .compatible
= "actions,s900-i2c" },
507 MODULE_DEVICE_TABLE(of
, owl_i2c_of_match
);
509 static struct platform_driver owl_i2c_driver
= {
510 .probe
= owl_i2c_probe
,
513 .of_match_table
= owl_i2c_of_match
,
514 .probe_type
= PROBE_PREFER_ASYNCHRONOUS
,
517 module_platform_driver(owl_i2c_driver
);
519 MODULE_AUTHOR("David Liu <liuwei@actions-semi.com>");
520 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
521 MODULE_DESCRIPTION("Actions Semiconductor Owl SoC's I2C driver");
522 MODULE_LICENSE("GPL");