drm/tests: hdmi: Fix memory leaks in drm_display_mode_from_cea_vic()
[drm/drm-misc.git] / drivers / iio / accel / kionix-kx022a.h
blob7060438ad88c8282a2cbe0ace41f7118f7f856dc
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Copyright (C) 2022 ROHM Semiconductors
5 * ROHM/KIONIX KX022A accelerometer driver
6 */
8 #ifndef _KX022A_H_
9 #define _KX022A_H_
11 #include <linux/bits.h>
12 #include <linux/regmap.h>
14 #define KX022A_REG_WHO 0x0f
15 #define KX022A_ID 0xc8
16 #define KX132ACR_LBZ_ID 0xd8
18 #define KX022A_REG_CNTL2 0x19
19 #define KX022A_MASK_SRST BIT(7)
20 #define KX022A_REG_CNTL 0x18
21 #define KX022A_MASK_PC1 BIT(7)
22 #define KX022A_MASK_RES BIT(6)
23 #define KX022A_MASK_DRDY BIT(5)
24 #define KX022A_MASK_GSEL GENMASK(4, 3)
25 #define KX022A_GSEL_SHIFT 3
26 #define KX022A_GSEL_2 0x0
27 #define KX022A_GSEL_4 BIT(3)
28 #define KX022A_GSEL_8 BIT(4)
29 #define KX022A_GSEL_16 GENMASK(4, 3)
31 #define KX022A_REG_INS2 0x13
32 #define KX022A_MASK_INS2_DRDY BIT(4)
33 #define KX122_MASK_INS2_WMI BIT(5)
35 #define KX022A_REG_XHP_L 0x0
36 #define KX022A_REG_XOUT_L 0x06
37 #define KX022A_REG_YOUT_L 0x08
38 #define KX022A_REG_ZOUT_L 0x0a
39 #define KX022A_REG_COTR 0x0c
40 #define KX022A_REG_TSCP 0x10
41 #define KX022A_REG_INT_REL 0x17
43 #define KX022A_REG_ODCNTL 0x1b
45 #define KX022A_REG_BTS_WUF_TH 0x31
46 #define KX022A_REG_MAN_WAKE 0x2c
48 #define KX022A_REG_BUF_CNTL1 0x3a
49 #define KX022A_MASK_WM_TH GENMASK(6, 0)
50 #define KX022A_REG_BUF_CNTL2 0x3b
51 #define KX022A_MASK_BUF_EN BIT(7)
52 #define KX022A_MASK_BRES16 BIT(6)
53 #define KX022A_REG_BUF_STATUS_1 0x3c
54 #define KX022A_REG_BUF_STATUS_2 0x3d
55 #define KX022A_REG_BUF_CLEAR 0x3e
56 #define KX022A_REG_BUF_READ 0x3f
57 #define KX022A_MASK_ODR GENMASK(3, 0)
58 #define KX022A_ODR_SHIFT 3
59 #define KX022A_FIFO_MAX_WMI_TH 41
61 #define KX022A_REG_INC1 0x1c
62 #define KX022A_REG_INC5 0x20
63 #define KX022A_REG_INC6 0x21
64 #define KX022A_MASK_IEN BIT(5)
65 #define KX022A_MASK_IPOL BIT(4)
66 #define KX022A_IPOL_LOW 0
67 #define KX022A_IPOL_HIGH KX022A_MASK_IPOL1
68 #define KX022A_MASK_ITYP BIT(3)
69 #define KX022A_ITYP_PULSE KX022A_MASK_ITYP
70 #define KX022A_ITYP_LEVEL 0
72 #define KX022A_REG_INC4 0x1f
73 #define KX022A_MASK_WMI BIT(5)
75 #define KX022A_REG_SELF_TEST 0x60
76 #define KX022A_MAX_REGISTER 0x60
78 #define KX132_REG_WHO 0x13
79 #define KX132_ID 0x3d
81 #define KX132_FIFO_LENGTH 86
83 #define KX132_REG_CNTL 0x1b
84 #define KX132_REG_CNTL2 0x1c
85 #define KX132_REG_CNTL5 0x1f
86 #define KX132_MASK_RES BIT(6)
87 #define KX132_GSEL_2 0x0
88 #define KX132_GSEL_4 BIT(3)
89 #define KX132_GSEL_8 BIT(4)
90 #define KX132_GSEL_16 GENMASK(4, 3)
92 #define KX132_REG_INS2 0x17
93 #define KX132_MASK_INS2_WMI BIT(5)
95 #define KX132_REG_XADP_L 0x02
96 #define KX132_REG_XOUT_L 0x08
97 #define KX132_REG_YOUT_L 0x0a
98 #define KX132_REG_ZOUT_L 0x0c
99 #define KX132_REG_COTR 0x12
100 #define KX132_REG_TSCP 0x14
101 #define KX132_REG_INT_REL 0x1a
103 #define KX132_REG_ODCNTL 0x21
105 #define KX132_REG_BTS_WUF_TH 0x4a
107 #define KX132_REG_BUF_CNTL1 0x5e
108 #define KX132_REG_BUF_CNTL2 0x5f
109 #define KX132_REG_BUF_STATUS_1 0x60
110 #define KX132_REG_BUF_STATUS_2 0x61
111 #define KX132_MASK_BUF_SMP_LVL GENMASK(9, 0)
112 #define KX132_REG_BUF_CLEAR 0x62
113 #define KX132_REG_BUF_READ 0x63
114 #define KX132_ODR_SHIFT 3
115 #define KX132_FIFO_MAX_WMI_TH 86
117 #define KX132_REG_INC1 0x22
118 #define KX132_REG_INC5 0x26
119 #define KX132_REG_INC6 0x27
120 #define KX132_IPOL_LOW 0
121 #define KX132_IPOL_HIGH KX022A_MASK_IPOL
122 #define KX132_ITYP_PULSE KX022A_MASK_ITYP
124 #define KX132_REG_INC4 0x25
126 #define KX132_REG_SELF_TEST 0x5d
127 #define KX132_MAX_REGISTER 0x76
129 struct device;
131 struct kx022a_data;
134 * struct kx022a_chip_info - Kionix accelerometer chip specific information
136 * @name: name of the device
137 * @regmap_config: pointer to register map configuration
138 * @channels: pointer to iio_chan_spec array
139 * @num_channels: number of iio_chan_spec channels
140 * @fifo_length: number of 16-bit samples in a full buffer
141 * @buf_smp_lvl_mask: buffer sample level mask
142 * @who: WHO_AM_I register
143 * @id: WHO_AM_I register value
144 * @cntl: control register 1
145 * @cntl2: control register 2
146 * @odcntl: output data control register
147 * @buf_cntl1: buffer control register 1
148 * @buf_cntl2: buffer control register 2
149 * @buf_clear: buffer clear register
150 * @buf_status1: buffer status register 1
151 * @buf_read: buffer read register
152 * @inc1: interrupt control register 1
153 * @inc4: interrupt control register 4
154 * @inc5: interrupt control register 5
155 * @inc6: interrupt control register 6
156 * @xout_l: x-axis output least significant byte
157 * @get_fifo_bytes_available: function pointer to get amount of acceleration
158 * data bytes currently stored in the sensor's FIFO
159 * buffer
161 struct kx022a_chip_info {
162 const char *name;
163 const struct regmap_config *regmap_config;
164 const struct iio_chan_spec *channels;
165 unsigned int num_channels;
166 unsigned int fifo_length;
167 u16 buf_smp_lvl_mask;
168 u8 who;
169 u8 id;
170 u8 cntl;
171 u8 cntl2;
172 u8 odcntl;
173 u8 buf_cntl1;
174 u8 buf_cntl2;
175 u8 buf_clear;
176 u8 buf_status1;
177 u8 buf_read;
178 u8 inc1;
179 u8 inc4;
180 u8 inc5;
181 u8 inc6;
182 u8 xout_l;
183 int (*get_fifo_bytes_available)(struct kx022a_data *);
186 int kx022a_probe_internal(struct device *dev, const struct kx022a_chip_info *chip_info);
188 extern const struct kx022a_chip_info kx022a_chip_info;
189 extern const struct kx022a_chip_info kx132_chip_info;
190 extern const struct kx022a_chip_info kx132acr_chip_info;
192 #endif