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drm/tests: hdmi: Fix memory leaks in drm_display_mode_from_cea_vic()
[drm/drm-misc.git] / drivers / iio / adc / ad7793.c
blobabebd519cafa30c8d4a2ef1a9887e430f7c217ca
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * AD7785/AD7792/AD7793/AD7794/AD7795 SPI ADC driver
4 *
5 * Copyright 2011-2012 Analog Devices Inc.
6 */
7
8 #include <linux/interrupt.h>
9 #include <linux/device.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/sysfs.h>
13 #include <linux/spi/spi.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/err.h>
16 #include <linux/sched.h>
17 #include <linux/delay.h>
18 #include <linux/module.h>
19
20 #include <linux/iio/iio.h>
21 #include <linux/iio/sysfs.h>
22 #include <linux/iio/buffer.h>
23 #include <linux/iio/trigger.h>
24 #include <linux/iio/trigger_consumer.h>
25 #include <linux/iio/triggered_buffer.h>
26 #include <linux/iio/adc/ad_sigma_delta.h>
27 #include <linux/platform_data/ad7793.h>
28
29 /* Registers */
30 #define AD7793_REG_COMM 0 /* Communications Register (WO, 8-bit) */
31 #define AD7793_REG_STAT 0 /* Status Register (RO, 8-bit) */
32 #define AD7793_REG_MODE 1 /* Mode Register (RW, 16-bit */
33 #define AD7793_REG_CONF 2 /* Configuration Register (RW, 16-bit) */
34 #define AD7793_REG_DATA 3 /* Data Register (RO, 16-/24-bit) */
35 #define AD7793_REG_ID 4 /* ID Register (RO, 8-bit) */
36 #define AD7793_REG_IO 5 /* IO Register (RO, 8-bit) */
37 #define AD7793_REG_OFFSET 6 /* Offset Register (RW, 16-bit
38 * (AD7792)/24-bit (AD7793)) */
39 #define AD7793_REG_FULLSALE 7 /* Full-Scale Register
40 * (RW, 16-bit (AD7792)/24-bit (AD7793)) */
41
42 /* Communications Register Bit Designations (AD7793_REG_COMM) */
43 #define AD7793_COMM_WEN (1 << 7) /* Write Enable */
44 #define AD7793_COMM_WRITE (0 << 6) /* Write Operation */
45 #define AD7793_COMM_READ (1 << 6) /* Read Operation */
46 #define AD7793_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
47 #define AD7793_COMM_CREAD (1 << 2) /* Continuous Read of Data Register */
48
49 /* Status Register Bit Designations (AD7793_REG_STAT) */
50 #define AD7793_STAT_RDY (1 << 7) /* Ready */
51 #define AD7793_STAT_ERR (1 << 6) /* Error (Overrange, Underrange) */
52 #define AD7793_STAT_CH3 (1 << 2) /* Channel 3 */
53 #define AD7793_STAT_CH2 (1 << 1) /* Channel 2 */
54 #define AD7793_STAT_CH1 (1 << 0) /* Channel 1 */
55
56 /* Mode Register Bit Designations (AD7793_REG_MODE) */
57 #define AD7793_MODE_SEL(x) (((x) & 0x7) << 13) /* Operation Mode Select */
58 #define AD7793_MODE_SEL_MASK (0x7 << 13) /* Operation Mode Select mask */
59 #define AD7793_MODE_CLKSRC(x) (((x) & 0x3) << 6) /* ADC Clock Source Select */
60 #define AD7793_MODE_RATE(x) ((x) & 0xF) /* Filter Update Rate Select */
61
62 #define AD7793_MODE_CONT 0 /* Continuous Conversion Mode */
63 #define AD7793_MODE_SINGLE 1 /* Single Conversion Mode */
64 #define AD7793_MODE_IDLE 2 /* Idle Mode */
65 #define AD7793_MODE_PWRDN 3 /* Power-Down Mode */
66 #define AD7793_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
67 #define AD7793_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
68 #define AD7793_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
69 #define AD7793_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
70
71 #define AD7793_CLK_INT 0 /* Internal 64 kHz Clock not
72 * available at the CLK pin */
73 #define AD7793_CLK_INT_CO 1 /* Internal 64 kHz Clock available
74 * at the CLK pin */
75 #define AD7793_CLK_EXT 2 /* External 64 kHz Clock */
76 #define AD7793_CLK_EXT_DIV2 3 /* External Clock divided by 2 */
77
78 /* Configuration Register Bit Designations (AD7793_REG_CONF) */
79 #define AD7793_CONF_VBIAS(x) (((x) & 0x3) << 14) /* Bias Voltage
80 * Generator Enable */
81 #define AD7793_CONF_BO_EN (1 << 13) /* Burnout Current Enable */
82 #define AD7793_CONF_UNIPOLAR (1 << 12) /* Unipolar/Bipolar Enable */
83 #define AD7793_CONF_BOOST (1 << 11) /* Boost Enable */
84 #define AD7793_CONF_GAIN(x) (((x) & 0x7) << 8) /* Gain Select */
85 #define AD7793_CONF_REFSEL(x) ((x) << 6) /* INT/EXT Reference Select */
86 #define AD7793_CONF_BUF (1 << 4) /* Buffered Mode Enable */
87 #define AD7793_CONF_CHAN(x) ((x) & 0xf) /* Channel select */
88 #define AD7793_CONF_CHAN_MASK 0xf /* Channel select mask */
89
90 #define AD7793_CH_AIN1P_AIN1M 0 /* AIN1(+) - AIN1(-) */
91 #define AD7793_CH_AIN2P_AIN2M 1 /* AIN2(+) - AIN2(-) */
92 #define AD7793_CH_AIN3P_AIN3M 2 /* AIN3(+) - AIN3(-) */
93 #define AD7793_CH_AIN1M_AIN1M 3 /* AIN1(-) - AIN1(-) */
94 #define AD7793_CH_TEMP 6 /* Temp Sensor */
95 #define AD7793_CH_AVDD_MONITOR 7 /* AVDD Monitor */
96
97 #define AD7795_CH_AIN4P_AIN4M 4 /* AIN4(+) - AIN4(-) */
98 #define AD7795_CH_AIN5P_AIN5M 5 /* AIN5(+) - AIN5(-) */
99 #define AD7795_CH_AIN6P_AIN6M 6 /* AIN6(+) - AIN6(-) */
100 #define AD7795_CH_AIN1M_AIN1M 8 /* AIN1(-) - AIN1(-) */
101
102 /* ID Register Bit Designations (AD7793_REG_ID) */
103 #define AD7785_ID 0x3
104 #define AD7792_ID 0xA
105 #define AD7793_ID 0xB
106 #define AD7794_ID 0xF
107 #define AD7795_ID 0xF
108 #define AD7796_ID 0xA
109 #define AD7797_ID 0xB
110 #define AD7798_ID 0x8
111 #define AD7799_ID 0x9
112 #define AD7793_ID_MASK 0xF
113
114 /* IO (Excitation Current Sources) Register Bit Designations (AD7793_REG_IO) */
115 #define AD7793_IO_IEXC1_IOUT1_IEXC2_IOUT2 0 /* IEXC1 connect to IOUT1,
116 * IEXC2 connect to IOUT2 */
117 #define AD7793_IO_IEXC1_IOUT2_IEXC2_IOUT1 1 /* IEXC1 connect to IOUT2,
118 * IEXC2 connect to IOUT1 */
119 #define AD7793_IO_IEXC1_IEXC2_IOUT1 2 /* Both current sources
120 * IEXC1,2 connect to IOUT1 */
121 #define AD7793_IO_IEXC1_IEXC2_IOUT2 3 /* Both current sources
122 * IEXC1,2 connect to IOUT2 */
123
124 #define AD7793_IO_IXCEN_10uA (1 << 0) /* Excitation Current 10uA */
125 #define AD7793_IO_IXCEN_210uA (2 << 0) /* Excitation Current 210uA */
126 #define AD7793_IO_IXCEN_1mA (3 << 0) /* Excitation Current 1mA */
127
128 /* NOTE:
129 * The AD7792/AD7793 features a dual use data out ready DOUT/RDY output.
130 * In order to avoid contentions on the SPI bus, it's therefore necessary
131 * to use spi bus locking.
132 *
133 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
134 */
135
136 #define AD7793_FLAG_HAS_CLKSEL BIT(0)
137 #define AD7793_FLAG_HAS_REFSEL BIT(1)
138 #define AD7793_FLAG_HAS_VBIAS BIT(2)
139 #define AD7793_HAS_EXITATION_CURRENT BIT(3)
140 #define AD7793_FLAG_HAS_GAIN BIT(4)
141 #define AD7793_FLAG_HAS_BUFFER BIT(5)
142
143 struct ad7793_chip_info {
144 unsigned int id;
145 const struct iio_chan_spec *channels;
146 unsigned int num_channels;
147 unsigned int flags;
148
149 const struct iio_info *iio_info;
150 const u16 *sample_freq_avail;
151 };
152
153 struct ad7793_state {
154 const struct ad7793_chip_info *chip_info;
155 u16 int_vref_mv;
156 u16 mode;
157 u16 conf;
158 u32 scale_avail[8][2];
159
160 struct ad_sigma_delta sd;
161
162 };
163
164 enum ad7793_supported_device_ids {
165 ID_AD7785,
166 ID_AD7792,
167 ID_AD7793,
168 ID_AD7794,
169 ID_AD7795,
170 ID_AD7796,
171 ID_AD7797,
172 ID_AD7798,
173 ID_AD7799,
174 };
175
176 static struct ad7793_state *ad_sigma_delta_to_ad7793(struct ad_sigma_delta *sd)
177 {
178 return container_of(sd, struct ad7793_state, sd);
179 }
180
181 static int ad7793_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
182 {
183 struct ad7793_state *st = ad_sigma_delta_to_ad7793(sd);
184
185 st->conf &= ~AD7793_CONF_CHAN_MASK;
186 st->conf |= AD7793_CONF_CHAN(channel);
187
188 return ad_sd_write_reg(&st->sd, AD7793_REG_CONF, 2, st->conf);
189 }
190
191 static int ad7793_set_mode(struct ad_sigma_delta *sd,
192 enum ad_sigma_delta_mode mode)
193 {
194 struct ad7793_state *st = ad_sigma_delta_to_ad7793(sd);
195
196 st->mode &= ~AD7793_MODE_SEL_MASK;
197 st->mode |= AD7793_MODE_SEL(mode);
198
199 return ad_sd_write_reg(&st->sd, AD7793_REG_MODE, 2, st->mode);
200 }
201
202 static const struct ad_sigma_delta_info ad7793_sigma_delta_info = {
203 .set_channel = ad7793_set_channel,
204 .set_mode = ad7793_set_mode,
205 .has_registers = true,
206 .addr_shift = 3,
207 .read_mask = BIT(6),
208 .irq_flags = IRQF_TRIGGER_FALLING,
209 };
210
211 static const struct ad_sd_calib_data ad7793_calib_arr[6] = {
212 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN1P_AIN1M},
213 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN1P_AIN1M},
214 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN2P_AIN2M},
215 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN2P_AIN2M},
216 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN3P_AIN3M},
217 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN3P_AIN3M}
218 };
219
220 static int ad7793_calibrate_all(struct ad7793_state *st)
221 {
222 return ad_sd_calibrate_all(&st->sd, ad7793_calib_arr,
223 ARRAY_SIZE(ad7793_calib_arr));
224 }
225
226 static int ad7793_check_platform_data(struct ad7793_state *st,
227 const struct ad7793_platform_data *pdata)
228 {
229 if ((pdata->current_source_direction == AD7793_IEXEC1_IEXEC2_IOUT1 ||
230 pdata->current_source_direction == AD7793_IEXEC1_IEXEC2_IOUT2) &&
231 ((pdata->exitation_current != AD7793_IX_10uA) &&
232 (pdata->exitation_current != AD7793_IX_210uA)))
233 return -EINVAL;
234
235 if (!(st->chip_info->flags & AD7793_FLAG_HAS_CLKSEL) &&
236 pdata->clock_src != AD7793_CLK_SRC_INT)
237 return -EINVAL;
238
239 if (!(st->chip_info->flags & AD7793_FLAG_HAS_REFSEL) &&
240 pdata->refsel != AD7793_REFSEL_REFIN1)
241 return -EINVAL;
242
243 if (!(st->chip_info->flags & AD7793_FLAG_HAS_VBIAS) &&
244 pdata->bias_voltage != AD7793_BIAS_VOLTAGE_DISABLED)
245 return -EINVAL;
246
247 if (!(st->chip_info->flags & AD7793_HAS_EXITATION_CURRENT) &&
248 pdata->exitation_current != AD7793_IX_DISABLED)
249 return -EINVAL;
250
251 return 0;
252 }
253
254 static int ad7793_setup(struct iio_dev *indio_dev,
255 const struct ad7793_platform_data *pdata,
256 unsigned int vref_mv)
257 {
258 struct ad7793_state *st = iio_priv(indio_dev);
259 int i, ret;
260 unsigned long long scale_uv;
261 u32 id;
262
263 ret = ad7793_check_platform_data(st, pdata);
264 if (ret)
265 return ret;
266
267 /* reset the serial interface */
268 ret = ad_sd_reset(&st->sd, 32);
269 if (ret < 0)
270 goto out;
271 usleep_range(500, 2000); /* Wait for at least 500us */
272
273 /* write/read test for device presence */
274 ret = ad_sd_read_reg(&st->sd, AD7793_REG_ID, 1, &id);
275 if (ret)
276 goto out;
277
278 id &= AD7793_ID_MASK;
279
280 if (id != st->chip_info->id) {
281 ret = -ENODEV;
282 dev_err(&st->sd.spi->dev, "device ID query failed\n");
283 goto out;
284 }
285
286 st->mode = AD7793_MODE_RATE(1);
287 st->conf = 0;
288
289 if (st->chip_info->flags & AD7793_FLAG_HAS_CLKSEL)
290 st->mode |= AD7793_MODE_CLKSRC(pdata->clock_src);
291 if (st->chip_info->flags & AD7793_FLAG_HAS_REFSEL)
292 st->conf |= AD7793_CONF_REFSEL(pdata->refsel);
293 if (st->chip_info->flags & AD7793_FLAG_HAS_VBIAS)
294 st->conf |= AD7793_CONF_VBIAS(pdata->bias_voltage);
295 if (pdata->buffered || !(st->chip_info->flags & AD7793_FLAG_HAS_BUFFER))
296 st->conf |= AD7793_CONF_BUF;
297 if (pdata->boost_enable &&
298 (st->chip_info->flags & AD7793_FLAG_HAS_VBIAS))
299 st->conf |= AD7793_CONF_BOOST;
300 if (pdata->burnout_current)
301 st->conf |= AD7793_CONF_BO_EN;
302 if (pdata->unipolar)
303 st->conf |= AD7793_CONF_UNIPOLAR;
304
305 if (!(st->chip_info->flags & AD7793_FLAG_HAS_GAIN))
306 st->conf |= AD7793_CONF_GAIN(7);
307
308 ret = ad7793_set_mode(&st->sd, AD_SD_MODE_IDLE);
309 if (ret)
310 goto out;
311
312 ret = ad7793_set_channel(&st->sd, 0);
313 if (ret)
314 goto out;
315
316 if (st->chip_info->flags & AD7793_HAS_EXITATION_CURRENT) {
317 ret = ad_sd_write_reg(&st->sd, AD7793_REG_IO, 1,
318 pdata->exitation_current |
319 (pdata->current_source_direction << 2));
320 if (ret)
321 goto out;
322 }
323
324 ret = ad7793_calibrate_all(st);
325 if (ret)
326 goto out;
327
328 /* Populate available ADC input ranges */
329 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
330 scale_uv = ((u64)vref_mv * 100000000)
331 >> (st->chip_info->channels[0].scan_type.realbits -
332 (!!(st->conf & AD7793_CONF_UNIPOLAR) ? 0 : 1));
333 scale_uv >>= i;
334
335 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
336 st->scale_avail[i][0] = scale_uv;
337 }
338
339 return 0;
340 out:
341 dev_err(&st->sd.spi->dev, "setup failed\n");
342 return ret;
343 }
344
345 static const u16 ad7793_sample_freq_avail[16] = {0, 470, 242, 123, 62, 50, 39,
346 33, 19, 17, 16, 12, 10, 8, 6, 4};
347
348 static const u16 ad7797_sample_freq_avail[16] = {0, 0, 0, 123, 62, 50, 0,
349 33, 0, 17, 16, 12, 10, 8, 6, 4};
350
351 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
352 "470 242 123 62 50 39 33 19 17 16 12 10 8 6 4");
353
354 static IIO_CONST_ATTR_NAMED(sampling_frequency_available_ad7797,
355 sampling_frequency_available, "123 62 50 33 17 16 12 10 8 6 4");
356
357 static int ad7793_read_avail(struct iio_dev *indio_dev,
358 struct iio_chan_spec const *chan,
359 const int **vals, int *type, int *length,
360 long mask)
361 {
362 struct ad7793_state *st = iio_priv(indio_dev);
363
364 switch (mask) {
365 case IIO_CHAN_INFO_SCALE:
366 *vals = (int *)st->scale_avail;
367 *type = IIO_VAL_INT_PLUS_NANO;
368 /* Values are stored in a 2D matrix */
369 *length = ARRAY_SIZE(st->scale_avail) * 2;
370
371 return IIO_AVAIL_LIST;
372 default:
373 return -EINVAL;
374 }
375 }
376
377 static struct attribute *ad7793_attributes[] = {
378 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
379 NULL
380 };
381
382 static const struct attribute_group ad7793_attribute_group = {
383 .attrs = ad7793_attributes,
384 };
385
386 static struct attribute *ad7797_attributes[] = {
387 &iio_const_attr_sampling_frequency_available_ad7797.dev_attr.attr,
388 NULL
389 };
390
391 static const struct attribute_group ad7797_attribute_group = {
392 .attrs = ad7797_attributes,
393 };
394
395 static int ad7793_read_raw(struct iio_dev *indio_dev,
396 struct iio_chan_spec const *chan,
397 int *val,
398 int *val2,
399 long m)
400 {
401 struct ad7793_state *st = iio_priv(indio_dev);
402 int ret;
403 unsigned long long scale_uv;
404 bool unipolar = !!(st->conf & AD7793_CONF_UNIPOLAR);
405
406 switch (m) {
407 case IIO_CHAN_INFO_RAW:
408 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
409 if (ret < 0)
410 return ret;
411
412 return IIO_VAL_INT;
413
414 case IIO_CHAN_INFO_SCALE:
415 switch (chan->type) {
416 case IIO_VOLTAGE:
417 if (chan->differential) {
418 *val = st->
419 scale_avail[(st->conf >> 8) & 0x7][0];
420 *val2 = st->
421 scale_avail[(st->conf >> 8) & 0x7][1];
422 return IIO_VAL_INT_PLUS_NANO;
423 }
424 /* 1170mV / 2^23 * 6 */
425 scale_uv = (1170ULL * 1000000000ULL * 6ULL);
426 break;
427 case IIO_TEMP:
428 /* 1170mV / 0.81 mV/C / 2^23 */
429 scale_uv = 1444444444444444ULL;
430 break;
431 default:
432 return -EINVAL;
433 }
434
435 scale_uv >>= (chan->scan_type.realbits - (unipolar ? 0 : 1));
436 *val = 0;
437 *val2 = scale_uv;
438 return IIO_VAL_INT_PLUS_NANO;
439 case IIO_CHAN_INFO_OFFSET:
440 if (!unipolar)
441 *val = -(1 << (chan->scan_type.realbits - 1));
442 else
443 *val = 0;
444
445 /* Kelvin to Celsius */
446 if (chan->type == IIO_TEMP) {
447 unsigned long long offset;
448 unsigned int shift;
449
450 shift = chan->scan_type.realbits - (unipolar ? 0 : 1);
451 offset = 273ULL << shift;
452 do_div(offset, 1444);
453 *val -= offset;
454 }
455 return IIO_VAL_INT;
456 case IIO_CHAN_INFO_SAMP_FREQ:
457 *val = st->chip_info
458 ->sample_freq_avail[AD7793_MODE_RATE(st->mode)];
459 return IIO_VAL_INT;
460 }
461 return -EINVAL;
462 }
463
464 static int ad7793_write_raw(struct iio_dev *indio_dev,
465 struct iio_chan_spec const *chan,
466 int val,
467 int val2,
468 long mask)
469 {
470 struct ad7793_state *st = iio_priv(indio_dev);
471 int ret, i;
472 unsigned int tmp;
473
474 ret = iio_device_claim_direct_mode(indio_dev);
475 if (ret)
476 return ret;
477
478 switch (mask) {
479 case IIO_CHAN_INFO_SCALE:
480 ret = -EINVAL;
481 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
482 if (val2 == st->scale_avail[i][1]) {
483 ret = 0;
484 tmp = st->conf;
485 st->conf &= ~AD7793_CONF_GAIN(-1);
486 st->conf |= AD7793_CONF_GAIN(i);
487
488 if (tmp == st->conf)
489 break;
490
491 ad_sd_write_reg(&st->sd, AD7793_REG_CONF,
492 sizeof(st->conf), st->conf);
493 ad7793_calibrate_all(st);
494 break;
495 }
496 break;
497 case IIO_CHAN_INFO_SAMP_FREQ:
498 if (!val) {
499 ret = -EINVAL;
500 break;
501 }
502
503 for (i = 0; i < 16; i++)
504 if (val == st->chip_info->sample_freq_avail[i])
505 break;
506
507 if (i == 16) {
508 ret = -EINVAL;
509 break;
510 }
511
512 st->mode &= ~AD7793_MODE_RATE(-1);
513 st->mode |= AD7793_MODE_RATE(i);
514 ad_sd_write_reg(&st->sd, AD7793_REG_MODE, sizeof(st->mode),
515 st->mode);
516 break;
517 default:
518 ret = -EINVAL;
519 }
520
521 iio_device_release_direct_mode(indio_dev);
522 return ret;
523 }
524
525 static int ad7793_write_raw_get_fmt(struct iio_dev *indio_dev,
526 struct iio_chan_spec const *chan,
527 long mask)
528 {
529 return IIO_VAL_INT_PLUS_NANO;
530 }
531
532 static const struct iio_info ad7793_info = {
533 .read_raw = &ad7793_read_raw,
534 .write_raw = &ad7793_write_raw,
535 .write_raw_get_fmt = &ad7793_write_raw_get_fmt,
536 .read_avail = ad7793_read_avail,
537 .attrs = &ad7793_attribute_group,
538 .validate_trigger = ad_sd_validate_trigger,
539 };
540
541 static const struct iio_info ad7797_info = {
542 .read_raw = &ad7793_read_raw,
543 .write_raw = &ad7793_write_raw,
544 .write_raw_get_fmt = &ad7793_write_raw_get_fmt,
545 .attrs = &ad7797_attribute_group,
546 .validate_trigger = ad_sd_validate_trigger,
547 };
548
549 #define __AD7793_CHANNEL(_si, _channel1, _channel2, _address, _bits, \
550 _storagebits, _shift, _extend_name, _type, _mask_type_av, _mask_all) \
551 { \
552 .type = (_type), \
553 .differential = (_channel2 == -1 ? 0 : 1), \
554 .indexed = 1, \
555 .channel = (_channel1), \
556 .channel2 = (_channel2), \
557 .address = (_address), \
558 .extend_name = (_extend_name), \
559 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
560 BIT(IIO_CHAN_INFO_OFFSET), \
561 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
562 .info_mask_shared_by_type_available = (_mask_type_av), \
563 .info_mask_shared_by_all = _mask_all, \
564 .scan_index = (_si), \
565 .scan_type = { \
566 .sign = 'u', \
567 .realbits = (_bits), \
568 .storagebits = (_storagebits), \
569 .shift = (_shift), \
570 .endianness = IIO_BE, \
571 }, \
572 }
573
574 #define AD7793_DIFF_CHANNEL(_si, _channel1, _channel2, _address, _bits, \
575 _storagebits, _shift) \
576 __AD7793_CHANNEL(_si, _channel1, _channel2, _address, _bits, \
577 _storagebits, _shift, NULL, IIO_VOLTAGE, \
578 BIT(IIO_CHAN_INFO_SCALE), \
579 BIT(IIO_CHAN_INFO_SAMP_FREQ))
580
581 #define AD7793_SHORTED_CHANNEL(_si, _channel, _address, _bits, \
582 _storagebits, _shift) \
583 __AD7793_CHANNEL(_si, _channel, _channel, _address, _bits, \
584 _storagebits, _shift, "shorted", IIO_VOLTAGE, \
585 BIT(IIO_CHAN_INFO_SCALE), \
586 BIT(IIO_CHAN_INFO_SAMP_FREQ))
587
588 #define AD7793_TEMP_CHANNEL(_si, _address, _bits, _storagebits, _shift) \
589 __AD7793_CHANNEL(_si, 0, -1, _address, _bits, \
590 _storagebits, _shift, NULL, IIO_TEMP, \
591 0, \
592 BIT(IIO_CHAN_INFO_SAMP_FREQ))
593
594 #define AD7793_SUPPLY_CHANNEL(_si, _channel, _address, _bits, _storagebits, \
595 _shift) \
596 __AD7793_CHANNEL(_si, _channel, -1, _address, _bits, \
597 _storagebits, _shift, "supply", IIO_VOLTAGE, \
598 0, \
599 BIT(IIO_CHAN_INFO_SAMP_FREQ))
600
601 #define AD7797_DIFF_CHANNEL(_si, _channel1, _channel2, _address, _bits, \
602 _storagebits, _shift) \
603 __AD7793_CHANNEL(_si, _channel1, _channel2, _address, _bits, \
604 _storagebits, _shift, NULL, IIO_VOLTAGE, \
605 0, \
606 BIT(IIO_CHAN_INFO_SAMP_FREQ))
607
608 #define AD7797_SHORTED_CHANNEL(_si, _channel, _address, _bits, \
609 _storagebits, _shift) \
610 __AD7793_CHANNEL(_si, _channel, _channel, _address, _bits, \
611 _storagebits, _shift, "shorted", IIO_VOLTAGE, \
612 0, \
613 BIT(IIO_CHAN_INFO_SAMP_FREQ))
614
615 #define DECLARE_AD7793_CHANNELS(_name, _b, _sb, _s) \
616 const struct iio_chan_spec _name##_channels[] = { \
617 AD7793_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), (_s)), \
618 AD7793_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), (_s)), \
619 AD7793_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), (_s)), \
620 AD7793_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), (_s)), \
621 AD7793_TEMP_CHANNEL(4, AD7793_CH_TEMP, (_b), (_sb), (_s)), \
622 AD7793_SUPPLY_CHANNEL(5, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), (_s)), \
623 IIO_CHAN_SOFT_TIMESTAMP(6), \
624 }
625
626 #define DECLARE_AD7795_CHANNELS(_name, _b, _sb) \
627 const struct iio_chan_spec _name##_channels[] = { \
628 AD7793_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \
629 AD7793_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), 0), \
630 AD7793_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), 0), \
631 AD7793_DIFF_CHANNEL(3, 3, 3, AD7795_CH_AIN4P_AIN4M, (_b), (_sb), 0), \
632 AD7793_DIFF_CHANNEL(4, 4, 4, AD7795_CH_AIN5P_AIN5M, (_b), (_sb), 0), \
633 AD7793_DIFF_CHANNEL(5, 5, 5, AD7795_CH_AIN6P_AIN6M, (_b), (_sb), 0), \
634 AD7793_SHORTED_CHANNEL(6, 0, AD7795_CH_AIN1M_AIN1M, (_b), (_sb), 0), \
635 AD7793_TEMP_CHANNEL(7, AD7793_CH_TEMP, (_b), (_sb), 0), \
636 AD7793_SUPPLY_CHANNEL(8, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \
637 IIO_CHAN_SOFT_TIMESTAMP(9), \
638 }
639
640 #define DECLARE_AD7797_CHANNELS(_name, _b, _sb) \
641 const struct iio_chan_spec _name##_channels[] = { \
642 AD7797_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \
643 AD7797_SHORTED_CHANNEL(1, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), 0), \
644 AD7793_TEMP_CHANNEL(2, AD7793_CH_TEMP, (_b), (_sb), 0), \
645 AD7793_SUPPLY_CHANNEL(3, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \
646 IIO_CHAN_SOFT_TIMESTAMP(4), \
647 }
648
649 #define DECLARE_AD7799_CHANNELS(_name, _b, _sb) \
650 const struct iio_chan_spec _name##_channels[] = { \
651 AD7793_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \
652 AD7793_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), 0), \
653 AD7793_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), 0), \
654 AD7793_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), 0), \
655 AD7793_SUPPLY_CHANNEL(4, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \
656 IIO_CHAN_SOFT_TIMESTAMP(5), \
657 }
658
659 static DECLARE_AD7793_CHANNELS(ad7785, 20, 32, 4);
660 static DECLARE_AD7793_CHANNELS(ad7792, 16, 32, 0);
661 static DECLARE_AD7793_CHANNELS(ad7793, 24, 32, 0);
662 static DECLARE_AD7795_CHANNELS(ad7794, 16, 32);
663 static DECLARE_AD7795_CHANNELS(ad7795, 24, 32);
664 static DECLARE_AD7797_CHANNELS(ad7796, 16, 16);
665 static DECLARE_AD7797_CHANNELS(ad7797, 24, 32);
666 static DECLARE_AD7799_CHANNELS(ad7798, 16, 16);
667 static DECLARE_AD7799_CHANNELS(ad7799, 24, 32);
668
669 static const struct ad7793_chip_info ad7793_chip_info_tbl[] = {
670 [ID_AD7785] = {
671 .id = AD7785_ID,
672 .channels = ad7785_channels,
673 .num_channels = ARRAY_SIZE(ad7785_channels),
674 .iio_info = &ad7793_info,
675 .sample_freq_avail = ad7793_sample_freq_avail,
676 .flags = AD7793_FLAG_HAS_CLKSEL |
677 AD7793_FLAG_HAS_REFSEL |
678 AD7793_FLAG_HAS_VBIAS |
679 AD7793_HAS_EXITATION_CURRENT |
680 AD7793_FLAG_HAS_GAIN |
681 AD7793_FLAG_HAS_BUFFER,
682 },
683 [ID_AD7792] = {
684 .id = AD7792_ID,
685 .channels = ad7792_channels,
686 .num_channels = ARRAY_SIZE(ad7792_channels),
687 .iio_info = &ad7793_info,
688 .sample_freq_avail = ad7793_sample_freq_avail,
689 .flags = AD7793_FLAG_HAS_CLKSEL |
690 AD7793_FLAG_HAS_REFSEL |
691 AD7793_FLAG_HAS_VBIAS |
692 AD7793_HAS_EXITATION_CURRENT |
693 AD7793_FLAG_HAS_GAIN |
694 AD7793_FLAG_HAS_BUFFER,
695 },
696 [ID_AD7793] = {
697 .id = AD7793_ID,
698 .channels = ad7793_channels,
699 .num_channels = ARRAY_SIZE(ad7793_channels),
700 .iio_info = &ad7793_info,
701 .sample_freq_avail = ad7793_sample_freq_avail,
702 .flags = AD7793_FLAG_HAS_CLKSEL |
703 AD7793_FLAG_HAS_REFSEL |
704 AD7793_FLAG_HAS_VBIAS |
705 AD7793_HAS_EXITATION_CURRENT |
706 AD7793_FLAG_HAS_GAIN |
707 AD7793_FLAG_HAS_BUFFER,
708 },
709 [ID_AD7794] = {
710 .id = AD7794_ID,
711 .channels = ad7794_channels,
712 .num_channels = ARRAY_SIZE(ad7794_channels),
713 .iio_info = &ad7793_info,
714 .sample_freq_avail = ad7793_sample_freq_avail,
715 .flags = AD7793_FLAG_HAS_CLKSEL |
716 AD7793_FLAG_HAS_REFSEL |
717 AD7793_FLAG_HAS_VBIAS |
718 AD7793_HAS_EXITATION_CURRENT |
719 AD7793_FLAG_HAS_GAIN |
720 AD7793_FLAG_HAS_BUFFER,
721 },
722 [ID_AD7795] = {
723 .id = AD7795_ID,
724 .channels = ad7795_channels,
725 .num_channels = ARRAY_SIZE(ad7795_channels),
726 .iio_info = &ad7793_info,
727 .sample_freq_avail = ad7793_sample_freq_avail,
728 .flags = AD7793_FLAG_HAS_CLKSEL |
729 AD7793_FLAG_HAS_REFSEL |
730 AD7793_FLAG_HAS_VBIAS |
731 AD7793_HAS_EXITATION_CURRENT |
732 AD7793_FLAG_HAS_GAIN |
733 AD7793_FLAG_HAS_BUFFER,
734 },
735 [ID_AD7796] = {
736 .id = AD7796_ID,
737 .channels = ad7796_channels,
738 .num_channels = ARRAY_SIZE(ad7796_channels),
739 .iio_info = &ad7797_info,
740 .sample_freq_avail = ad7797_sample_freq_avail,
741 .flags = AD7793_FLAG_HAS_CLKSEL,
742 },
743 [ID_AD7797] = {
744 .id = AD7797_ID,
745 .channels = ad7797_channels,
746 .num_channels = ARRAY_SIZE(ad7797_channels),
747 .iio_info = &ad7797_info,
748 .sample_freq_avail = ad7797_sample_freq_avail,
749 .flags = AD7793_FLAG_HAS_CLKSEL,
750 },
751 [ID_AD7798] = {
752 .id = AD7798_ID,
753 .channels = ad7798_channels,
754 .num_channels = ARRAY_SIZE(ad7798_channels),
755 .iio_info = &ad7793_info,
756 .sample_freq_avail = ad7793_sample_freq_avail,
757 .flags = AD7793_FLAG_HAS_GAIN |
758 AD7793_FLAG_HAS_BUFFER,
759 },
760 [ID_AD7799] = {
761 .id = AD7799_ID,
762 .channels = ad7799_channels,
763 .num_channels = ARRAY_SIZE(ad7799_channels),
764 .iio_info = &ad7793_info,
765 .sample_freq_avail = ad7793_sample_freq_avail,
766 .flags = AD7793_FLAG_HAS_GAIN |
767 AD7793_FLAG_HAS_BUFFER,
768 },
769 };
770
771 static int ad7793_probe(struct spi_device *spi)
772 {
773 const struct ad7793_platform_data *pdata = spi->dev.platform_data;
774 struct ad7793_state *st;
775 struct iio_dev *indio_dev;
776 int ret, vref_mv = 0;
777
778 if (!pdata) {
779 dev_err(&spi->dev, "no platform data?\n");
780 return -ENODEV;
781 }
782
783 if (!spi->irq) {
784 dev_err(&spi->dev, "no IRQ?\n");
785 return -ENODEV;
786 }
787
788 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
789 if (indio_dev == NULL)
790 return -ENOMEM;
791
792 st = iio_priv(indio_dev);
793
794 ad_sd_init(&st->sd, indio_dev, spi, &ad7793_sigma_delta_info);
795
796 if (pdata->refsel != AD7793_REFSEL_INTERNAL) {
797 ret = devm_regulator_get_enable_read_voltage(&spi->dev, "refin");
798 if (ret < 0)
799 return ret;
800
801 vref_mv = ret / 1000;
802 } else {
803 vref_mv = 1170; /* Build-in ref */
804 }
805
806 st->chip_info =
807 &ad7793_chip_info_tbl[spi_get_device_id(spi)->driver_data];
808
809 indio_dev->name = spi_get_device_id(spi)->name;
810 indio_dev->modes = INDIO_DIRECT_MODE;
811 indio_dev->channels = st->chip_info->channels;
812 indio_dev->num_channels = st->chip_info->num_channels;
813 indio_dev->info = st->chip_info->iio_info;
814
815 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev);
816 if (ret)
817 return ret;
818
819 ret = ad7793_setup(indio_dev, pdata, vref_mv);
820 if (ret)
821 return ret;
822
823 return devm_iio_device_register(&spi->dev, indio_dev);
824 }
825
826 static const struct spi_device_id ad7793_id[] = {
827 { "ad7785", ID_AD7785 },
828 { "ad7792", ID_AD7792 },
829 { "ad7793", ID_AD7793 },
830 { "ad7794", ID_AD7794 },
831 { "ad7795", ID_AD7795 },
832 { "ad7796", ID_AD7796 },
833 { "ad7797", ID_AD7797 },
834 { "ad7798", ID_AD7798 },
835 { "ad7799", ID_AD7799 },
836 { }
837 };
838 MODULE_DEVICE_TABLE(spi, ad7793_id);
839
840 static struct spi_driver ad7793_driver = {
841 .driver = {
842 .name = "ad7793",
843 },
844 .probe = ad7793_probe,
845 .id_table = ad7793_id,
846 };
847 module_spi_driver(ad7793_driver);
848
849 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
850 MODULE_DESCRIPTION("Analog Devices AD7793 and similar ADCs");
851 MODULE_LICENSE("GPL v2");
852 MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA);
Kernel DRM miscellaneous fixes and cross-tree changes