1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/bits.h>
4 #include <linux/delay.h>
6 #include <linux/kernel.h>
7 #include <linux/ktime.h>
8 #include <linux/mod_devicetable.h>
9 #include <linux/module.h>
10 #include <linux/mutex.h>
11 #include <linux/platform_device.h>
12 #include <linux/regmap.h>
14 #include <linux/iio/buffer.h>
15 #include <linux/iio/iio.h>
16 #include <linux/iio/trigger_consumer.h>
17 #include <linux/iio/triggered_buffer.h>
19 #include <linux/unaligned.h>
21 #define MT6360_REG_PMUCHGCTRL3 0x313
22 #define MT6360_REG_PMUADCCFG 0x356
23 #define MT6360_REG_PMUADCIDLET 0x358
24 #define MT6360_REG_PMUADCRPT1 0x35A
26 /* PMUCHGCTRL3 0x313 */
27 #define MT6360_AICR_MASK GENMASK(7, 2)
28 #define MT6360_AICR_SHFT 2
29 #define MT6360_AICR_400MA 0x6
31 #define MT6360_ADCEN_MASK BIT(15)
32 /* PMUADCRPT1 0x35A */
33 #define MT6360_PREFERCH_MASK GENMASK(7, 4)
34 #define MT6360_PREFERCH_SHFT 4
35 #define MT6360_RPTCH_MASK GENMASK(3, 0)
36 #define MT6360_NO_PREFER 15
39 #define ADC_WAIT_TIME_MS 25
40 #define ADC_CONV_TIMEOUT_MS 100
41 #define ADC_LOOP_TIME_US 2000
44 MT6360_CHAN_USBID
= 0,
58 struct mt6360_adc_data
{
60 struct regmap
*regmap
;
61 /* Due to only one set of ADC control, this lock is used to prevent the race condition */
62 struct mutex adc_lock
;
63 ktime_t last_off_timestamps
[MT6360_CHAN_MAX
];
66 static int mt6360_adc_read_channel(struct mt6360_adc_data
*mad
, int channel
, int *val
)
70 ktime_t predict_end_t
, timeout
;
71 unsigned int pre_wait_time
;
74 mutex_lock(&mad
->adc_lock
);
76 /* Select the preferred ADC channel */
77 ret
= regmap_update_bits(mad
->regmap
, MT6360_REG_PMUADCRPT1
, MT6360_PREFERCH_MASK
,
78 channel
<< MT6360_PREFERCH_SHFT
);
82 adc_enable
= cpu_to_be16(MT6360_ADCEN_MASK
| BIT(channel
));
83 ret
= regmap_raw_write(mad
->regmap
, MT6360_REG_PMUADCCFG
, &adc_enable
, sizeof(adc_enable
));
87 predict_end_t
= ktime_add_ms(mad
->last_off_timestamps
[channel
], 2 * ADC_WAIT_TIME_MS
);
89 if (ktime_after(ktime_get(), predict_end_t
))
90 pre_wait_time
= ADC_WAIT_TIME_MS
;
92 pre_wait_time
= 3 * ADC_WAIT_TIME_MS
;
94 if (msleep_interruptible(pre_wait_time
)) {
99 timeout
= ktime_add_ms(ktime_get(), ADC_CONV_TIMEOUT_MS
);
101 ret
= regmap_raw_read(mad
->regmap
, MT6360_REG_PMUADCRPT1
, rpt
, sizeof(rpt
));
106 * There are two functions, ZCV and TypeC OTP, running ADC VBAT and TS in
107 * background, and ADC samples are taken on a fixed frequency no matter read the
108 * previous one or not.
109 * To avoid conflict, We set minimum time threshold after enable ADC and
110 * check report channel is the same.
111 * The worst case is run the same ADC twice and background function is also running,
112 * ADC conversion sequence is desire channel before start ADC, background ADC,
113 * desire channel after start ADC.
114 * So the minimum correct data is three times of typical conversion time.
116 if ((rpt
[0] & MT6360_RPTCH_MASK
) == channel
)
119 if (ktime_compare(ktime_get(), timeout
) > 0) {
124 usleep_range(ADC_LOOP_TIME_US
/ 2, ADC_LOOP_TIME_US
);
127 *val
= rpt
[1] << 8 | rpt
[2];
131 /* Only keep ADC enable */
132 adc_enable
= cpu_to_be16(MT6360_ADCEN_MASK
);
133 regmap_raw_write(mad
->regmap
, MT6360_REG_PMUADCCFG
, &adc_enable
, sizeof(adc_enable
));
134 mad
->last_off_timestamps
[channel
] = ktime_get();
135 /* Config prefer channel to NO_PREFER */
136 regmap_update_bits(mad
->regmap
, MT6360_REG_PMUADCRPT1
, MT6360_PREFERCH_MASK
,
137 MT6360_NO_PREFER
<< MT6360_PREFERCH_SHFT
);
139 mutex_unlock(&mad
->adc_lock
);
144 static int mt6360_adc_read_scale(struct mt6360_adc_data
*mad
, int channel
, int *val
, int *val2
)
150 case MT6360_CHAN_USBID
:
151 case MT6360_CHAN_VSYS
:
152 case MT6360_CHAN_VBAT
:
153 case MT6360_CHAN_CHG_VDDP
:
154 case MT6360_CHAN_VREF_TS
:
158 case MT6360_CHAN_VBUSDIV5
:
161 case MT6360_CHAN_VBUSDIV2
:
162 case MT6360_CHAN_IBUS
:
163 case MT6360_CHAN_IBAT
:
166 if (channel
== MT6360_CHAN_IBUS
) {
167 /* IBUS will be affected by input current limit for the different Ron */
168 /* Check whether the config is <400mA or not */
169 ret
= regmap_read(mad
->regmap
, MT6360_REG_PMUCHGCTRL3
, ®val
);
173 regval
= (regval
& MT6360_AICR_MASK
) >> MT6360_AICR_SHFT
;
174 if (regval
< MT6360_AICR_400MA
)
179 case MT6360_CHAN_TEMP_JC
:
182 return IIO_VAL_FRACTIONAL
;
188 static int mt6360_adc_read_offset(struct mt6360_adc_data
*mad
, int channel
, int *val
)
190 *val
= (channel
== MT6360_CHAN_TEMP_JC
) ? -80 : 0;
194 static int mt6360_adc_read_raw(struct iio_dev
*iio_dev
, const struct iio_chan_spec
*chan
,
195 int *val
, int *val2
, long mask
)
197 struct mt6360_adc_data
*mad
= iio_priv(iio_dev
);
200 case IIO_CHAN_INFO_RAW
:
201 return mt6360_adc_read_channel(mad
, chan
->channel
, val
);
202 case IIO_CHAN_INFO_SCALE
:
203 return mt6360_adc_read_scale(mad
, chan
->channel
, val
, val2
);
204 case IIO_CHAN_INFO_OFFSET
:
205 return mt6360_adc_read_offset(mad
, chan
->channel
, val
);
211 static const char *mt6360_channel_labels
[MT6360_CHAN_MAX
] = {
212 "usbid", "vbusdiv5", "vbusdiv2", "vsys", "vbat", "ibus", "ibat", "chg_vddp",
213 "temp_jc", "vref_ts", "ts",
216 static int mt6360_adc_read_label(struct iio_dev
*iio_dev
, const struct iio_chan_spec
*chan
,
219 return snprintf(label
, PAGE_SIZE
, "%s\n", mt6360_channel_labels
[chan
->channel
]);
222 static const struct iio_info mt6360_adc_iio_info
= {
223 .read_raw
= mt6360_adc_read_raw
,
224 .read_label
= mt6360_adc_read_label
,
227 #define MT6360_ADC_CHAN(_idx, _type) { \
229 .channel = MT6360_CHAN_##_idx, \
230 .scan_index = MT6360_CHAN_##_idx, \
231 .datasheet_name = #_idx, \
236 .endianness = IIO_CPU, \
239 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
240 BIT(IIO_CHAN_INFO_SCALE) | \
241 BIT(IIO_CHAN_INFO_OFFSET), \
244 static const struct iio_chan_spec mt6360_adc_channels
[] = {
245 MT6360_ADC_CHAN(USBID
, IIO_VOLTAGE
),
246 MT6360_ADC_CHAN(VBUSDIV5
, IIO_VOLTAGE
),
247 MT6360_ADC_CHAN(VBUSDIV2
, IIO_VOLTAGE
),
248 MT6360_ADC_CHAN(VSYS
, IIO_VOLTAGE
),
249 MT6360_ADC_CHAN(VBAT
, IIO_VOLTAGE
),
250 MT6360_ADC_CHAN(IBUS
, IIO_CURRENT
),
251 MT6360_ADC_CHAN(IBAT
, IIO_CURRENT
),
252 MT6360_ADC_CHAN(CHG_VDDP
, IIO_VOLTAGE
),
253 MT6360_ADC_CHAN(TEMP_JC
, IIO_TEMP
),
254 MT6360_ADC_CHAN(VREF_TS
, IIO_VOLTAGE
),
255 MT6360_ADC_CHAN(TS
, IIO_VOLTAGE
),
256 IIO_CHAN_SOFT_TIMESTAMP(MT6360_CHAN_MAX
),
259 static irqreturn_t
mt6360_adc_trigger_handler(int irq
, void *p
)
261 struct iio_poll_func
*pf
= p
;
262 struct iio_dev
*indio_dev
= pf
->indio_dev
;
263 struct mt6360_adc_data
*mad
= iio_priv(indio_dev
);
265 u16 values
[MT6360_CHAN_MAX
];
268 int i
= 0, bit
, val
, ret
;
270 memset(&data
, 0, sizeof(data
));
271 iio_for_each_active_channel(indio_dev
, bit
) {
272 ret
= mt6360_adc_read_channel(mad
, bit
, &val
);
274 dev_warn(&indio_dev
->dev
, "Failed to get channel %d conversion val\n", bit
);
278 data
.values
[i
++] = val
;
280 iio_push_to_buffers_with_timestamp(indio_dev
, &data
, iio_get_time_ns(indio_dev
));
282 iio_trigger_notify_done(indio_dev
->trig
);
287 static inline int mt6360_adc_reset(struct mt6360_adc_data
*info
)
290 ktime_t all_off_time
;
293 /* Clear ADC idle wait time to 0 */
294 ret
= regmap_write(info
->regmap
, MT6360_REG_PMUADCIDLET
, 0);
298 /* Only keep ADC enable, but keep all channels off */
299 adc_enable
= cpu_to_be16(MT6360_ADCEN_MASK
);
300 ret
= regmap_raw_write(info
->regmap
, MT6360_REG_PMUADCCFG
, &adc_enable
, sizeof(adc_enable
));
304 /* Reset all channel off time to the current one */
305 all_off_time
= ktime_get();
306 for (i
= 0; i
< MT6360_CHAN_MAX
; i
++)
307 info
->last_off_timestamps
[i
] = all_off_time
;
312 static int mt6360_adc_probe(struct platform_device
*pdev
)
314 struct mt6360_adc_data
*mad
;
315 struct regmap
*regmap
;
316 struct iio_dev
*indio_dev
;
319 regmap
= dev_get_regmap(pdev
->dev
.parent
, NULL
);
321 dev_err(&pdev
->dev
, "Failed to get parent regmap\n");
325 indio_dev
= devm_iio_device_alloc(&pdev
->dev
, sizeof(*mad
));
329 mad
= iio_priv(indio_dev
);
330 mad
->dev
= &pdev
->dev
;
331 mad
->regmap
= regmap
;
332 mutex_init(&mad
->adc_lock
);
334 ret
= mt6360_adc_reset(mad
);
336 dev_err(&pdev
->dev
, "Failed to reset adc\n");
340 indio_dev
->name
= dev_name(&pdev
->dev
);
341 indio_dev
->info
= &mt6360_adc_iio_info
;
342 indio_dev
->modes
= INDIO_DIRECT_MODE
;
343 indio_dev
->channels
= mt6360_adc_channels
;
344 indio_dev
->num_channels
= ARRAY_SIZE(mt6360_adc_channels
);
346 ret
= devm_iio_triggered_buffer_setup(&pdev
->dev
, indio_dev
, NULL
,
347 mt6360_adc_trigger_handler
, NULL
);
349 dev_err(&pdev
->dev
, "Failed to allocate iio trigger buffer\n");
353 return devm_iio_device_register(&pdev
->dev
, indio_dev
);
356 static const struct of_device_id mt6360_adc_of_id
[] = {
357 { .compatible
= "mediatek,mt6360-adc", },
360 MODULE_DEVICE_TABLE(of
, mt6360_adc_of_id
);
362 static struct platform_driver mt6360_adc_driver
= {
364 .name
= "mt6360-adc",
365 .of_match_table
= mt6360_adc_of_id
,
367 .probe
= mt6360_adc_probe
,
369 module_platform_driver(mt6360_adc_driver
);
371 MODULE_AUTHOR("Gene Chen <gene_chen@richtek.com>");
372 MODULE_DESCRIPTION("MT6360 ADC Driver");
373 MODULE_LICENSE("GPL v2");