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drm/tests: hdmi: Fix memory leaks in drm_display_mode_from_cea_vic()
[drm/drm-misc.git] / drivers / media / platform / nxp / imx-mipi-csis.c
blob44e1402e8be198bb8d68aa172a9ebd6119fbcb7c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Samsung CSIS MIPI CSI-2 receiver driver.
4 *
5 * The Samsung CSIS IP is a MIPI CSI-2 receiver found in various NXP i.MX7 and
6 * i.MX8 SoCs. The i.MX7 features version 3.3 of the IP, while i.MX8 features
7 * version 3.6.3.
8 *
9 * Copyright (C) 2019 Linaro Ltd
10 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved.
11 * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd.
12 *
13 */
14
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/delay.h>
18 #include <linux/errno.h>
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/mutex.h>
24 #include <linux/of.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/reset.h>
29 #include <linux/spinlock.h>
30
31 #include <media/v4l2-common.h>
32 #include <media/v4l2-device.h>
33 #include <media/v4l2-event.h>
34 #include <media/v4l2-fwnode.h>
35 #include <media/v4l2-mc.h>
36 #include <media/v4l2-subdev.h>
37
38 #define CSIS_DRIVER_NAME "imx-mipi-csis"
39
40 #define CSIS_PAD_SINK 0
41 #define CSIS_PAD_SOURCE 1
42 #define CSIS_PADS_NUM 2
43
44 #define MIPI_CSIS_DEF_PIX_WIDTH 640
45 #define MIPI_CSIS_DEF_PIX_HEIGHT 480
46
47 /* Register map definition */
48
49 /* CSIS version */
50 #define MIPI_CSIS_VERSION 0x00
51 #define MIPI_CSIS_VERSION_IMX7D 0x03030505
52 #define MIPI_CSIS_VERSION_IMX8MP 0x03060301
53
54 /* CSIS common control */
55 #define MIPI_CSIS_CMN_CTRL 0x04
56 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW BIT(16)
57 #define MIPI_CSIS_CMN_CTRL_INTER_MODE BIT(10)
58 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL BIT(2)
59 #define MIPI_CSIS_CMN_CTRL_RESET BIT(1)
60 #define MIPI_CSIS_CMN_CTRL_ENABLE BIT(0)
61
62 #define MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET 8
63 #define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK (3 << 8)
64
65 /* CSIS clock control */
66 #define MIPI_CSIS_CLK_CTRL 0x08
67 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x) ((x) << 28)
68 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x) ((x) << 24)
69 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x) ((x) << 20)
70 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x) ((x) << 16)
71 #define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK (0xf << 4)
72 #define MIPI_CSIS_CLK_CTRL_WCLK_SRC BIT(0)
73
74 /* CSIS Interrupt mask */
75 #define MIPI_CSIS_INT_MSK 0x10
76 #define MIPI_CSIS_INT_MSK_EVEN_BEFORE BIT(31)
77 #define MIPI_CSIS_INT_MSK_EVEN_AFTER BIT(30)
78 #define MIPI_CSIS_INT_MSK_ODD_BEFORE BIT(29)
79 #define MIPI_CSIS_INT_MSK_ODD_AFTER BIT(28)
80 #define MIPI_CSIS_INT_MSK_FRAME_START BIT(24)
81 #define MIPI_CSIS_INT_MSK_FRAME_END BIT(20)
82 #define MIPI_CSIS_INT_MSK_ERR_SOT_HS BIT(16)
83 #define MIPI_CSIS_INT_MSK_ERR_LOST_FS BIT(12)
84 #define MIPI_CSIS_INT_MSK_ERR_LOST_FE BIT(8)
85 #define MIPI_CSIS_INT_MSK_ERR_OVER BIT(4)
86 #define MIPI_CSIS_INT_MSK_ERR_WRONG_CFG BIT(3)
87 #define MIPI_CSIS_INT_MSK_ERR_ECC BIT(2)
88 #define MIPI_CSIS_INT_MSK_ERR_CRC BIT(1)
89 #define MIPI_CSIS_INT_MSK_ERR_UNKNOWN BIT(0)
90
91 /* CSIS Interrupt source */
92 #define MIPI_CSIS_INT_SRC 0x14
93 #define MIPI_CSIS_INT_SRC_EVEN_BEFORE BIT(31)
94 #define MIPI_CSIS_INT_SRC_EVEN_AFTER BIT(30)
95 #define MIPI_CSIS_INT_SRC_EVEN BIT(30)
96 #define MIPI_CSIS_INT_SRC_ODD_BEFORE BIT(29)
97 #define MIPI_CSIS_INT_SRC_ODD_AFTER BIT(28)
98 #define MIPI_CSIS_INT_SRC_ODD (0x3 << 28)
99 #define MIPI_CSIS_INT_SRC_NON_IMAGE_DATA (0xf << 28)
100 #define MIPI_CSIS_INT_SRC_FRAME_START BIT(24)
101 #define MIPI_CSIS_INT_SRC_FRAME_END BIT(20)
102 #define MIPI_CSIS_INT_SRC_ERR_SOT_HS BIT(16)
103 #define MIPI_CSIS_INT_SRC_ERR_LOST_FS BIT(12)
104 #define MIPI_CSIS_INT_SRC_ERR_LOST_FE BIT(8)
105 #define MIPI_CSIS_INT_SRC_ERR_OVER BIT(4)
106 #define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG BIT(3)
107 #define MIPI_CSIS_INT_SRC_ERR_ECC BIT(2)
108 #define MIPI_CSIS_INT_SRC_ERR_CRC BIT(1)
109 #define MIPI_CSIS_INT_SRC_ERR_UNKNOWN BIT(0)
110 #define MIPI_CSIS_INT_SRC_ERRORS 0xfffff
111
112 /* D-PHY status control */
113 #define MIPI_CSIS_DPHY_STATUS 0x20
114 #define MIPI_CSIS_DPHY_STATUS_ULPS_DAT BIT(8)
115 #define MIPI_CSIS_DPHY_STATUS_STOPSTATE_DAT BIT(4)
116 #define MIPI_CSIS_DPHY_STATUS_ULPS_CLK BIT(1)
117 #define MIPI_CSIS_DPHY_STATUS_STOPSTATE_CLK BIT(0)
118
119 /* D-PHY common control */
120 #define MIPI_CSIS_DPHY_CMN_CTRL 0x24
121 #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(n) ((n) << 24)
122 #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE_MASK GENMASK(31, 24)
123 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(n) ((n) << 22)
124 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE_MASK GENMASK(23, 22)
125 #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_CLK BIT(6)
126 #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_DAT BIT(5)
127 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_DAT BIT(1)
128 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_CLK BIT(0)
129 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE (0x1f << 0)
130
131 /* D-PHY Master and Slave Control register Low */
132 #define MIPI_CSIS_DPHY_BCTRL_L 0x30
133 #define MIPI_CSIS_DPHY_BCTRL_L_USER_DATA_PATTERN_LOW(n) (((n) & 3U) << 30)
134 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV (0 << 28)
135 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_724MV (1 << 28)
136 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_733MV (2 << 28)
137 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_706MV (3 << 28)
138 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ (0 << 27)
139 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_1_5MHZ (1 << 27)
140 #define MIPI_CSIS_DPHY_BCTRL_L_VREG12_EXTPWR_EN_CTL BIT(26)
141 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V (0 << 24)
142 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_23V (1 << 24)
143 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_17V (2 << 24)
144 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_26V (3 << 24)
145 #define MIPI_CSIS_DPHY_BCTRL_L_REG_1P2_LVL_SEL BIT(23)
146 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV (0 << 21)
147 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_100MV (1 << 21)
148 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_120MV (2 << 21)
149 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_140MV (3 << 21)
150 #define MIPI_CSIS_DPHY_BCTRL_L_VREF_SRC_SEL BIT(20)
151 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV (0 << 18)
152 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_743MV (1 << 18)
153 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_650MV (2 << 18)
154 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_682MV (3 << 18)
155 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_PULSE_REJECT BIT(17)
156 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_0 (0 << 15)
157 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_15P (1 << 15)
158 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_30P (3 << 15)
159 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_UP BIT(14)
160 #define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV (0 << 13)
161 #define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_70MV (1 << 13)
162 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_EN BIT(12)
163 #define MIPI_CSIS_DPHY_BCTRL_L_ERRCONTENTION_LP_EN BIT(11)
164 #define MIPI_CSIS_DPHY_BCTRL_L_TXTRIGGER_CLK_EN BIT(10)
165 #define MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(n) (((n) * 25 / 1000000) << 0)
166
167 /* D-PHY Master and Slave Control register High */
168 #define MIPI_CSIS_DPHY_BCTRL_H 0x34
169 /* D-PHY Slave Control register Low */
170 #define MIPI_CSIS_DPHY_SCTRL_L 0x38
171 /* D-PHY Slave Control register High */
172 #define MIPI_CSIS_DPHY_SCTRL_H 0x3c
173
174 /* ISP Configuration register */
175 #define MIPI_CSIS_ISP_CONFIG_CH(n) (0x40 + (n) * 0x10)
176 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK (0xff << 24)
177 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x) ((x) << 24)
178 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_SINGLE (0 << 12)
179 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL (1 << 12)
180 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_QUAD (2 << 12) /* i.MX8M[MNP] only */
181 #define MIPI_CSIS_ISPCFG_PIXEL_MASK (3 << 12)
182 #define MIPI_CSIS_ISPCFG_ALIGN_32BIT BIT(11)
183 #define MIPI_CSIS_ISPCFG_FMT(fmt) ((fmt) << 2)
184 #define MIPI_CSIS_ISPCFG_FMT_MASK (0x3f << 2)
185
186 /* ISP Image Resolution register */
187 #define MIPI_CSIS_ISP_RESOL_CH(n) (0x44 + (n) * 0x10)
188 #define CSIS_MAX_PIX_WIDTH 0xffff
189 #define CSIS_MAX_PIX_HEIGHT 0xffff
190
191 /* ISP SYNC register */
192 #define MIPI_CSIS_ISP_SYNC_CH(n) (0x48 + (n) * 0x10)
193 #define MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET 18
194 #define MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET 12
195 #define MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET 0
196
197 /* ISP shadow registers */
198 #define MIPI_CSIS_SDW_CONFIG_CH(n) (0x80 + (n) * 0x10)
199 #define MIPI_CSIS_SDW_RESOL_CH(n) (0x84 + (n) * 0x10)
200 #define MIPI_CSIS_SDW_SYNC_CH(n) (0x88 + (n) * 0x10)
201
202 /* Debug control register */
203 #define MIPI_CSIS_DBG_CTRL 0xc0
204 #define MIPI_CSIS_DBG_INTR_MSK 0xc4
205 #define MIPI_CSIS_DBG_INTR_MSK_DT_NOT_SUPPORT BIT(25)
206 #define MIPI_CSIS_DBG_INTR_MSK_DT_IGNORE BIT(24)
207 #define MIPI_CSIS_DBG_INTR_MSK_ERR_FRAME_SIZE BIT(20)
208 #define MIPI_CSIS_DBG_INTR_MSK_TRUNCATED_FRAME BIT(16)
209 #define MIPI_CSIS_DBG_INTR_MSK_EARLY_FE BIT(12)
210 #define MIPI_CSIS_DBG_INTR_MSK_EARLY_FS BIT(8)
211 #define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_FALL BIT(4)
212 #define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_RISE BIT(0)
213 #define MIPI_CSIS_DBG_INTR_SRC 0xc8
214 #define MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT BIT(25)
215 #define MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE BIT(24)
216 #define MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE BIT(20)
217 #define MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME BIT(16)
218 #define MIPI_CSIS_DBG_INTR_SRC_EARLY_FE BIT(12)
219 #define MIPI_CSIS_DBG_INTR_SRC_EARLY_FS BIT(8)
220 #define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL BIT(4)
221 #define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE BIT(0)
222
223 #define MIPI_CSIS_FRAME_COUNTER_CH(n) (0x0100 + (n) * 4)
224
225 /* Non-image packet data buffers */
226 #define MIPI_CSIS_PKTDATA_ODD 0x2000
227 #define MIPI_CSIS_PKTDATA_EVEN 0x3000
228 #define MIPI_CSIS_PKTDATA_SIZE SZ_4K
229
230 #define DEFAULT_SCLK_CSIS_FREQ 166000000UL
231
232 /* MIPI CSI-2 Data Types */
233 #define MIPI_CSI2_DATA_TYPE_YUV420_8 0x18
234 #define MIPI_CSI2_DATA_TYPE_YUV420_10 0x19
235 #define MIPI_CSI2_DATA_TYPE_LE_YUV420_8 0x1a
236 #define MIPI_CSI2_DATA_TYPE_CS_YUV420_8 0x1c
237 #define MIPI_CSI2_DATA_TYPE_CS_YUV420_10 0x1d
238 #define MIPI_CSI2_DATA_TYPE_YUV422_8 0x1e
239 #define MIPI_CSI2_DATA_TYPE_YUV422_10 0x1f
240 #define MIPI_CSI2_DATA_TYPE_RGB565 0x22
241 #define MIPI_CSI2_DATA_TYPE_RGB666 0x23
242 #define MIPI_CSI2_DATA_TYPE_RGB888 0x24
243 #define MIPI_CSI2_DATA_TYPE_RAW6 0x28
244 #define MIPI_CSI2_DATA_TYPE_RAW7 0x29
245 #define MIPI_CSI2_DATA_TYPE_RAW8 0x2a
246 #define MIPI_CSI2_DATA_TYPE_RAW10 0x2b
247 #define MIPI_CSI2_DATA_TYPE_RAW12 0x2c
248 #define MIPI_CSI2_DATA_TYPE_RAW14 0x2d
249 #define MIPI_CSI2_DATA_TYPE_USER(x) (0x30 + (x))
250
251 struct mipi_csis_event {
252 bool debug;
253 u32 mask;
254 const char * const name;
255 unsigned int counter;
256 };
257
258 static const struct mipi_csis_event mipi_csis_events[] = {
259 /* Errors */
260 { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS, "SOT Error" },
261 { false, MIPI_CSIS_INT_SRC_ERR_LOST_FS, "Lost Frame Start Error" },
262 { false, MIPI_CSIS_INT_SRC_ERR_LOST_FE, "Lost Frame End Error" },
263 { false, MIPI_CSIS_INT_SRC_ERR_OVER, "FIFO Overflow Error" },
264 { false, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG, "Wrong Configuration Error" },
265 { false, MIPI_CSIS_INT_SRC_ERR_ECC, "ECC Error" },
266 { false, MIPI_CSIS_INT_SRC_ERR_CRC, "CRC Error" },
267 { false, MIPI_CSIS_INT_SRC_ERR_UNKNOWN, "Unknown Error" },
268 { true, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT, "Data Type Not Supported" },
269 { true, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE, "Data Type Ignored" },
270 { true, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE, "Frame Size Error" },
271 { true, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME, "Truncated Frame" },
272 { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE, "Early Frame End" },
273 { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS, "Early Frame Start" },
274 /* Non-image data receive events */
275 { false, MIPI_CSIS_INT_SRC_EVEN_BEFORE, "Non-image data before even frame" },
276 { false, MIPI_CSIS_INT_SRC_EVEN_AFTER, "Non-image data after even frame" },
277 { false, MIPI_CSIS_INT_SRC_ODD_BEFORE, "Non-image data before odd frame" },
278 { false, MIPI_CSIS_INT_SRC_ODD_AFTER, "Non-image data after odd frame" },
279 /* Frame start/end */
280 { false, MIPI_CSIS_INT_SRC_FRAME_START, "Frame Start" },
281 { false, MIPI_CSIS_INT_SRC_FRAME_END, "Frame End" },
282 { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL, "VSYNC Falling Edge" },
283 { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE, "VSYNC Rising Edge" },
284 };
285
286 #define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events)
287
288 enum mipi_csis_clk {
289 MIPI_CSIS_CLK_PCLK,
290 MIPI_CSIS_CLK_WRAP,
291 MIPI_CSIS_CLK_PHY,
292 MIPI_CSIS_CLK_AXI,
293 };
294
295 static const char * const mipi_csis_clk_id[] = {
296 "pclk",
297 "wrap",
298 "phy",
299 "axi",
300 };
301
302 enum mipi_csis_version {
303 MIPI_CSIS_V3_3,
304 MIPI_CSIS_V3_6_3,
305 };
306
307 struct mipi_csis_info {
308 enum mipi_csis_version version;
309 unsigned int num_clocks;
310 };
311
312 struct mipi_csis_device {
313 struct device *dev;
314 void __iomem *regs;
315 struct clk_bulk_data *clks;
316 struct reset_control *mrst;
317 struct regulator *mipi_phy_regulator;
318 const struct mipi_csis_info *info;
319
320 struct v4l2_subdev sd;
321 struct media_pad pads[CSIS_PADS_NUM];
322 struct v4l2_async_notifier notifier;
323
324 struct {
325 struct v4l2_subdev *sd;
326 const struct media_pad *pad;
327 } source;
328
329 struct v4l2_mbus_config_mipi_csi2 bus;
330 u32 clk_frequency;
331 u32 hs_settle;
332 u32 clk_settle;
333
334 spinlock_t slock; /* Protect events */
335 struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS];
336 struct dentry *debugfs_root;
337 struct {
338 bool enable;
339 u32 hs_settle;
340 u32 clk_settle;
341 } debug;
342 };
343
344 /* -----------------------------------------------------------------------------
345 * Format helpers
346 */
347
348 struct csis_pix_format {
349 u32 code;
350 u32 output;
351 u32 data_type;
352 u8 width;
353 };
354
355 static const struct csis_pix_format mipi_csis_formats[] = {
356 /* YUV formats. */
357 {
358 .code = MEDIA_BUS_FMT_UYVY8_1X16,
359 .output = MEDIA_BUS_FMT_UYVY8_1X16,
360 .data_type = MIPI_CSI2_DATA_TYPE_YUV422_8,
361 .width = 16,
362 },
363 /* RGB formats. */
364 {
365 .code = MEDIA_BUS_FMT_RGB565_1X16,
366 .output = MEDIA_BUS_FMT_RGB565_1X16,
367 .data_type = MIPI_CSI2_DATA_TYPE_RGB565,
368 .width = 16,
369 }, {
370 .code = MEDIA_BUS_FMT_BGR888_1X24,
371 .output = MEDIA_BUS_FMT_RGB888_1X24,
372 .data_type = MIPI_CSI2_DATA_TYPE_RGB888,
373 .width = 24,
374 },
375 /* RAW (Bayer and greyscale) formats. */
376 {
377 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
378 .output = MEDIA_BUS_FMT_SBGGR8_1X8,
379 .data_type = MIPI_CSI2_DATA_TYPE_RAW8,
380 .width = 8,
381 }, {
382 .code = MEDIA_BUS_FMT_SGBRG8_1X8,
383 .output = MEDIA_BUS_FMT_SGBRG8_1X8,
384 .data_type = MIPI_CSI2_DATA_TYPE_RAW8,
385 .width = 8,
386 }, {
387 .code = MEDIA_BUS_FMT_SGRBG8_1X8,
388 .output = MEDIA_BUS_FMT_SGRBG8_1X8,
389 .data_type = MIPI_CSI2_DATA_TYPE_RAW8,
390 .width = 8,
391 }, {
392 .code = MEDIA_BUS_FMT_SRGGB8_1X8,
393 .output = MEDIA_BUS_FMT_SRGGB8_1X8,
394 .data_type = MIPI_CSI2_DATA_TYPE_RAW8,
395 .width = 8,
396 }, {
397 .code = MEDIA_BUS_FMT_Y8_1X8,
398 .output = MEDIA_BUS_FMT_Y8_1X8,
399 .data_type = MIPI_CSI2_DATA_TYPE_RAW8,
400 .width = 8,
401 }, {
402 .code = MEDIA_BUS_FMT_SBGGR10_1X10,
403 .output = MEDIA_BUS_FMT_SBGGR10_1X10,
404 .data_type = MIPI_CSI2_DATA_TYPE_RAW10,
405 .width = 10,
406 }, {
407 .code = MEDIA_BUS_FMT_SGBRG10_1X10,
408 .output = MEDIA_BUS_FMT_SGBRG10_1X10,
409 .data_type = MIPI_CSI2_DATA_TYPE_RAW10,
410 .width = 10,
411 }, {
412 .code = MEDIA_BUS_FMT_SGRBG10_1X10,
413 .output = MEDIA_BUS_FMT_SGRBG10_1X10,
414 .data_type = MIPI_CSI2_DATA_TYPE_RAW10,
415 .width = 10,
416 }, {
417 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
418 .output = MEDIA_BUS_FMT_SRGGB10_1X10,
419 .data_type = MIPI_CSI2_DATA_TYPE_RAW10,
420 .width = 10,
421 }, {
422 .code = MEDIA_BUS_FMT_Y10_1X10,
423 .output = MEDIA_BUS_FMT_Y10_1X10,
424 .data_type = MIPI_CSI2_DATA_TYPE_RAW10,
425 .width = 10,
426 }, {
427 .code = MEDIA_BUS_FMT_SBGGR12_1X12,
428 .output = MEDIA_BUS_FMT_SBGGR12_1X12,
429 .data_type = MIPI_CSI2_DATA_TYPE_RAW12,
430 .width = 12,
431 }, {
432 .code = MEDIA_BUS_FMT_SGBRG12_1X12,
433 .output = MEDIA_BUS_FMT_SGBRG12_1X12,
434 .data_type = MIPI_CSI2_DATA_TYPE_RAW12,
435 .width = 12,
436 }, {
437 .code = MEDIA_BUS_FMT_SGRBG12_1X12,
438 .output = MEDIA_BUS_FMT_SGRBG12_1X12,
439 .data_type = MIPI_CSI2_DATA_TYPE_RAW12,
440 .width = 12,
441 }, {
442 .code = MEDIA_BUS_FMT_SRGGB12_1X12,
443 .output = MEDIA_BUS_FMT_SRGGB12_1X12,
444 .data_type = MIPI_CSI2_DATA_TYPE_RAW12,
445 .width = 12,
446 }, {
447 .code = MEDIA_BUS_FMT_Y12_1X12,
448 .output = MEDIA_BUS_FMT_Y12_1X12,
449 .data_type = MIPI_CSI2_DATA_TYPE_RAW12,
450 .width = 12,
451 }, {
452 .code = MEDIA_BUS_FMT_SBGGR14_1X14,
453 .output = MEDIA_BUS_FMT_SBGGR14_1X14,
454 .data_type = MIPI_CSI2_DATA_TYPE_RAW14,
455 .width = 14,
456 }, {
457 .code = MEDIA_BUS_FMT_SGBRG14_1X14,
458 .output = MEDIA_BUS_FMT_SGBRG14_1X14,
459 .data_type = MIPI_CSI2_DATA_TYPE_RAW14,
460 .width = 14,
461 }, {
462 .code = MEDIA_BUS_FMT_SGRBG14_1X14,
463 .output = MEDIA_BUS_FMT_SGRBG14_1X14,
464 .data_type = MIPI_CSI2_DATA_TYPE_RAW14,
465 .width = 14,
466 }, {
467 .code = MEDIA_BUS_FMT_SRGGB14_1X14,
468 .output = MEDIA_BUS_FMT_SRGGB14_1X14,
469 .data_type = MIPI_CSI2_DATA_TYPE_RAW14,
470 .width = 14,
471 },
472 /* JPEG */
473 {
474 .code = MEDIA_BUS_FMT_JPEG_1X8,
475 .output = MEDIA_BUS_FMT_JPEG_1X8,
476 /*
477 * Map JPEG_1X8 to the RAW8 datatype.
478 *
479 * The CSI-2 specification suggests in Annex A "JPEG8 Data
480 * Format (informative)" to transmit JPEG data using one of the
481 * Data Types aimed to represent arbitrary data, such as the
482 * "User Defined Data Type 1" (0x30).
483 *
484 * However, when configured with a User Defined Data Type, the
485 * CSIS outputs data in quad pixel mode regardless of the mode
486 * selected in the MIPI_CSIS_ISP_CONFIG_CH register. Neither of
487 * the IP cores connected to the CSIS in i.MX SoCs (CSI bridge
488 * or ISI) support quad pixel mode, so this will never work in
489 * practice.
490 *
491 * Some sensors (such as the OV5640) send JPEG data using the
492 * RAW8 data type. This is usable and works, so map the JPEG
493 * format to RAW8. If the CSIS ends up being integrated in an
494 * SoC that can support quad pixel mode, this will have to be
495 * revisited.
496 */
497 .data_type = MIPI_CSI2_DATA_TYPE_RAW8,
498 .width = 8,
499 }
500 };
501
502 static const struct csis_pix_format *find_csis_format(u32 code)
503 {
504 unsigned int i;
505
506 for (i = 0; i < ARRAY_SIZE(mipi_csis_formats); i++)
507 if (code == mipi_csis_formats[i].code)
508 return &mipi_csis_formats[i];
509 return NULL;
510 }
511
512 /* -----------------------------------------------------------------------------
513 * Hardware configuration
514 */
515
516 static inline u32 mipi_csis_read(struct mipi_csis_device *csis, u32 reg)
517 {
518 return readl(csis->regs + reg);
519 }
520
521 static inline void mipi_csis_write(struct mipi_csis_device *csis, u32 reg,
522 u32 val)
523 {
524 writel(val, csis->regs + reg);
525 }
526
527 static void mipi_csis_enable_interrupts(struct mipi_csis_device *csis, bool on)
528 {
529 mipi_csis_write(csis, MIPI_CSIS_INT_MSK, on ? 0xffffffff : 0);
530 mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_MSK, on ? 0xffffffff : 0);
531 }
532
533 static void mipi_csis_sw_reset(struct mipi_csis_device *csis)
534 {
535 u32 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
536
537 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL,
538 val | MIPI_CSIS_CMN_CTRL_RESET);
539 usleep_range(10, 20);
540 }
541
542 static void mipi_csis_system_enable(struct mipi_csis_device *csis, int on)
543 {
544 u32 val, mask;
545
546 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
547 if (on)
548 val |= MIPI_CSIS_CMN_CTRL_ENABLE;
549 else
550 val &= ~MIPI_CSIS_CMN_CTRL_ENABLE;
551 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val);
552
553 val = mipi_csis_read(csis, MIPI_CSIS_DPHY_CMN_CTRL);
554 val &= ~MIPI_CSIS_DPHY_CMN_CTRL_ENABLE;
555 if (on) {
556 mask = (1 << (csis->bus.num_data_lanes + 1)) - 1;
557 val |= (mask & MIPI_CSIS_DPHY_CMN_CTRL_ENABLE);
558 }
559 mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL, val);
560 }
561
562 static void __mipi_csis_set_format(struct mipi_csis_device *csis,
563 const struct v4l2_mbus_framefmt *format,
564 const struct csis_pix_format *csis_fmt)
565 {
566 u32 val;
567
568 /* Color format */
569 val = mipi_csis_read(csis, MIPI_CSIS_ISP_CONFIG_CH(0));
570 val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK
571 | MIPI_CSIS_ISPCFG_PIXEL_MASK);
572
573 /*
574 * YUV 4:2:2 can be transferred with 8 or 16 bits per clock sample
575 * (referred to in the documentation as single and dual pixel modes
576 * respectively, although the 8-bit mode transfers half a pixel per
577 * clock sample and the 16-bit mode one pixel). While both mode work
578 * when the CSIS is connected to a receiver that supports either option,
579 * single pixel mode requires clock rates twice as high. As all SoCs
580 * that integrate the CSIS can operate in 16-bit bit mode, and some do
581 * not support 8-bit mode (this is the case of the i.MX8MP), use dual
582 * pixel mode unconditionally.
583 *
584 * TODO: Verify which other formats require DUAL (or QUAD) modes.
585 */
586 if (csis_fmt->data_type == MIPI_CSI2_DATA_TYPE_YUV422_8)
587 val |= MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL;
588
589 val |= MIPI_CSIS_ISPCFG_FMT(csis_fmt->data_type);
590 mipi_csis_write(csis, MIPI_CSIS_ISP_CONFIG_CH(0), val);
591
592 /* Pixel resolution */
593 val = format->width | (format->height << 16);
594 mipi_csis_write(csis, MIPI_CSIS_ISP_RESOL_CH(0), val);
595 }
596
597 static int mipi_csis_calculate_params(struct mipi_csis_device *csis,
598 const struct csis_pix_format *csis_fmt)
599 {
600 s64 link_freq;
601 u32 lane_rate;
602
603 /* Calculate the line rate from the pixel rate. */
604 link_freq = v4l2_get_link_freq(csis->source.sd->ctrl_handler,
605 csis_fmt->width,
606 csis->bus.num_data_lanes * 2);
607 if (link_freq < 0) {
608 dev_err(csis->dev, "Unable to obtain link frequency: %d\n",
609 (int)link_freq);
610 return link_freq;
611 }
612
613 lane_rate = link_freq * 2;
614
615 if (lane_rate < 80000000 || lane_rate > 1500000000) {
616 dev_dbg(csis->dev, "Out-of-bound lane rate %u\n", lane_rate);
617 return -EINVAL;
618 }
619
620 /*
621 * The HSSETTLE counter value is document in a table, but can also
622 * easily be calculated. Hardcode the CLKSETTLE value to 0 for now
623 * (which is documented as corresponding to CSI-2 v0.87 to v1.00) until
624 * we figure out how to compute it correctly.
625 */
626 csis->hs_settle = (lane_rate - 5000000) / 45000000;
627 csis->clk_settle = 0;
628
629 dev_dbg(csis->dev, "lane rate %u, Tclk_settle %u, Ths_settle %u\n",
630 lane_rate, csis->clk_settle, csis->hs_settle);
631
632 if (csis->debug.hs_settle < 0xff) {
633 dev_dbg(csis->dev, "overriding Ths_settle with %u\n",
634 csis->debug.hs_settle);
635 csis->hs_settle = csis->debug.hs_settle;
636 }
637
638 if (csis->debug.clk_settle < 4) {
639 dev_dbg(csis->dev, "overriding Tclk_settle with %u\n",
640 csis->debug.clk_settle);
641 csis->clk_settle = csis->debug.clk_settle;
642 }
643
644 return 0;
645 }
646
647 static void mipi_csis_set_params(struct mipi_csis_device *csis,
648 const struct v4l2_mbus_framefmt *format,
649 const struct csis_pix_format *csis_fmt)
650 {
651 int lanes = csis->bus.num_data_lanes;
652 u32 val;
653
654 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
655 val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK;
656 val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET;
657 if (csis->info->version == MIPI_CSIS_V3_3)
658 val |= MIPI_CSIS_CMN_CTRL_INTER_MODE;
659 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val);
660
661 __mipi_csis_set_format(csis, format, csis_fmt);
662
663 mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL,
664 MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(csis->hs_settle) |
665 MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(csis->clk_settle));
666
667 val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET)
668 | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET)
669 | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET);
670 mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(0), val);
671
672 val = mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL);
673 val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
674 val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15);
675 val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK;
676 mipi_csis_write(csis, MIPI_CSIS_CLK_CTRL, val);
677
678 mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_L,
679 MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV |
680 MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ |
681 MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V |
682 MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV |
683 MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV |
684 MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV |
685 MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(20000000));
686 mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_H, 0);
687
688 /* Update the shadow register. */
689 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
690 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL,
691 val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW |
692 MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL);
693 }
694
695 static int mipi_csis_clk_enable(struct mipi_csis_device *csis)
696 {
697 return clk_bulk_prepare_enable(csis->info->num_clocks, csis->clks);
698 }
699
700 static void mipi_csis_clk_disable(struct mipi_csis_device *csis)
701 {
702 clk_bulk_disable_unprepare(csis->info->num_clocks, csis->clks);
703 }
704
705 static int mipi_csis_clk_get(struct mipi_csis_device *csis)
706 {
707 unsigned int i;
708 int ret;
709
710 csis->clks = devm_kcalloc(csis->dev, csis->info->num_clocks,
711 sizeof(*csis->clks), GFP_KERNEL);
712
713 if (!csis->clks)
714 return -ENOMEM;
715
716 for (i = 0; i < csis->info->num_clocks; i++)
717 csis->clks[i].id = mipi_csis_clk_id[i];
718
719 ret = devm_clk_bulk_get(csis->dev, csis->info->num_clocks,
720 csis->clks);
721 if (ret < 0)
722 return ret;
723
724 /* Set clock rate */
725 ret = clk_set_rate(csis->clks[MIPI_CSIS_CLK_WRAP].clk,
726 csis->clk_frequency);
727 if (ret < 0)
728 dev_err(csis->dev, "set rate=%d failed: %d\n",
729 csis->clk_frequency, ret);
730
731 return ret;
732 }
733
734 static void mipi_csis_start_stream(struct mipi_csis_device *csis,
735 const struct v4l2_mbus_framefmt *format,
736 const struct csis_pix_format *csis_fmt)
737 {
738 mipi_csis_sw_reset(csis);
739 mipi_csis_set_params(csis, format, csis_fmt);
740 mipi_csis_system_enable(csis, true);
741 mipi_csis_enable_interrupts(csis, true);
742 }
743
744 static void mipi_csis_stop_stream(struct mipi_csis_device *csis)
745 {
746 mipi_csis_enable_interrupts(csis, false);
747 mipi_csis_system_enable(csis, false);
748 }
749
750 static void mipi_csis_queue_event_sof(struct mipi_csis_device *csis)
751 {
752 struct v4l2_event event = {
753 .type = V4L2_EVENT_FRAME_SYNC,
754 };
755 u32 frame;
756
757 frame = mipi_csis_read(csis, MIPI_CSIS_FRAME_COUNTER_CH(0));
758 event.u.frame_sync.frame_sequence = frame;
759 v4l2_event_queue(csis->sd.devnode, &event);
760 }
761
762 static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id)
763 {
764 struct mipi_csis_device *csis = dev_id;
765 unsigned long flags;
766 unsigned int i;
767 u32 status;
768 u32 dbg_status;
769
770 status = mipi_csis_read(csis, MIPI_CSIS_INT_SRC);
771 dbg_status = mipi_csis_read(csis, MIPI_CSIS_DBG_INTR_SRC);
772
773 spin_lock_irqsave(&csis->slock, flags);
774
775 /* Update the event/error counters */
776 if ((status & MIPI_CSIS_INT_SRC_ERRORS) || csis->debug.enable) {
777 for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) {
778 struct mipi_csis_event *event = &csis->events[i];
779
780 if ((!event->debug && (status & event->mask)) ||
781 (event->debug && (dbg_status & event->mask)))
782 event->counter++;
783 }
784 }
785
786 if (status & MIPI_CSIS_INT_SRC_FRAME_START)
787 mipi_csis_queue_event_sof(csis);
788
789 spin_unlock_irqrestore(&csis->slock, flags);
790
791 mipi_csis_write(csis, MIPI_CSIS_INT_SRC, status);
792 mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_SRC, dbg_status);
793
794 return IRQ_HANDLED;
795 }
796
797 /* -----------------------------------------------------------------------------
798 * PHY regulator and reset
799 */
800
801 static int mipi_csis_phy_enable(struct mipi_csis_device *csis)
802 {
803 if (csis->info->version != MIPI_CSIS_V3_3)
804 return 0;
805
806 return regulator_enable(csis->mipi_phy_regulator);
807 }
808
809 static int mipi_csis_phy_disable(struct mipi_csis_device *csis)
810 {
811 if (csis->info->version != MIPI_CSIS_V3_3)
812 return 0;
813
814 return regulator_disable(csis->mipi_phy_regulator);
815 }
816
817 static void mipi_csis_phy_reset(struct mipi_csis_device *csis)
818 {
819 if (csis->info->version != MIPI_CSIS_V3_3)
820 return;
821
822 reset_control_assert(csis->mrst);
823 msleep(20);
824 reset_control_deassert(csis->mrst);
825 }
826
827 static int mipi_csis_phy_init(struct mipi_csis_device *csis)
828 {
829 if (csis->info->version != MIPI_CSIS_V3_3)
830 return 0;
831
832 /* Get MIPI PHY reset and regulator. */
833 csis->mrst = devm_reset_control_get_exclusive(csis->dev, NULL);
834 if (IS_ERR(csis->mrst))
835 return PTR_ERR(csis->mrst);
836
837 csis->mipi_phy_regulator = devm_regulator_get(csis->dev, "phy");
838 if (IS_ERR(csis->mipi_phy_regulator))
839 return PTR_ERR(csis->mipi_phy_regulator);
840
841 return regulator_set_voltage(csis->mipi_phy_regulator, 1000000,
842 1000000);
843 }
844
845 /* -----------------------------------------------------------------------------
846 * Debug
847 */
848
849 static void mipi_csis_clear_counters(struct mipi_csis_device *csis)
850 {
851 unsigned long flags;
852 unsigned int i;
853
854 spin_lock_irqsave(&csis->slock, flags);
855 for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++)
856 csis->events[i].counter = 0;
857 spin_unlock_irqrestore(&csis->slock, flags);
858 }
859
860 static void mipi_csis_log_counters(struct mipi_csis_device *csis, bool non_errors)
861 {
862 unsigned int num_events = non_errors ? MIPI_CSIS_NUM_EVENTS
863 : MIPI_CSIS_NUM_EVENTS - 8;
864 unsigned int counters[MIPI_CSIS_NUM_EVENTS];
865 unsigned long flags;
866 unsigned int i;
867
868 spin_lock_irqsave(&csis->slock, flags);
869 for (i = 0; i < num_events; ++i)
870 counters[i] = csis->events[i].counter;
871 spin_unlock_irqrestore(&csis->slock, flags);
872
873 for (i = 0; i < num_events; ++i) {
874 if (counters[i] > 0 || csis->debug.enable)
875 dev_info(csis->dev, "%s events: %d\n",
876 csis->events[i].name,
877 counters[i]);
878 }
879 }
880
881 static int mipi_csis_dump_regs(struct mipi_csis_device *csis)
882 {
883 static const struct {
884 u32 offset;
885 const char * const name;
886 } registers[] = {
887 { MIPI_CSIS_CMN_CTRL, "CMN_CTRL" },
888 { MIPI_CSIS_CLK_CTRL, "CLK_CTRL" },
889 { MIPI_CSIS_INT_MSK, "INT_MSK" },
890 { MIPI_CSIS_DPHY_STATUS, "DPHY_STATUS" },
891 { MIPI_CSIS_DPHY_CMN_CTRL, "DPHY_CMN_CTRL" },
892 { MIPI_CSIS_DPHY_SCTRL_L, "DPHY_SCTRL_L" },
893 { MIPI_CSIS_DPHY_SCTRL_H, "DPHY_SCTRL_H" },
894 { MIPI_CSIS_ISP_CONFIG_CH(0), "ISP_CONFIG_CH0" },
895 { MIPI_CSIS_ISP_RESOL_CH(0), "ISP_RESOL_CH0" },
896 { MIPI_CSIS_SDW_CONFIG_CH(0), "SDW_CONFIG_CH0" },
897 { MIPI_CSIS_SDW_RESOL_CH(0), "SDW_RESOL_CH0" },
898 { MIPI_CSIS_DBG_CTRL, "DBG_CTRL" },
899 { MIPI_CSIS_FRAME_COUNTER_CH(0), "FRAME_COUNTER_CH0" },
900 };
901
902 unsigned int i;
903 u32 cfg;
904
905 if (!pm_runtime_get_if_in_use(csis->dev))
906 return 0;
907
908 dev_info(csis->dev, "--- REGISTERS ---\n");
909
910 for (i = 0; i < ARRAY_SIZE(registers); i++) {
911 cfg = mipi_csis_read(csis, registers[i].offset);
912 dev_info(csis->dev, "%14s: 0x%08x\n", registers[i].name, cfg);
913 }
914
915 pm_runtime_put(csis->dev);
916
917 return 0;
918 }
919
920 static int mipi_csis_dump_regs_show(struct seq_file *m, void *private)
921 {
922 struct mipi_csis_device *csis = m->private;
923
924 return mipi_csis_dump_regs(csis);
925 }
926 DEFINE_SHOW_ATTRIBUTE(mipi_csis_dump_regs);
927
928 static void mipi_csis_debugfs_init(struct mipi_csis_device *csis)
929 {
930 csis->debug.hs_settle = UINT_MAX;
931 csis->debug.clk_settle = UINT_MAX;
932
933 csis->debugfs_root = debugfs_create_dir(dev_name(csis->dev), NULL);
934
935 debugfs_create_bool("debug_enable", 0600, csis->debugfs_root,
936 &csis->debug.enable);
937 debugfs_create_file("dump_regs", 0600, csis->debugfs_root, csis,
938 &mipi_csis_dump_regs_fops);
939 debugfs_create_u32("tclk_settle", 0600, csis->debugfs_root,
940 &csis->debug.clk_settle);
941 debugfs_create_u32("ths_settle", 0600, csis->debugfs_root,
942 &csis->debug.hs_settle);
943 }
944
945 static void mipi_csis_debugfs_exit(struct mipi_csis_device *csis)
946 {
947 debugfs_remove_recursive(csis->debugfs_root);
948 }
949
950 /* -----------------------------------------------------------------------------
951 * V4L2 subdev operations
952 */
953
954 static struct mipi_csis_device *sd_to_mipi_csis_device(struct v4l2_subdev *sdev)
955 {
956 return container_of(sdev, struct mipi_csis_device, sd);
957 }
958
959 static int mipi_csis_s_stream(struct v4l2_subdev *sd, int enable)
960 {
961 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
962 const struct v4l2_mbus_framefmt *format;
963 const struct csis_pix_format *csis_fmt;
964 struct v4l2_subdev_state *state;
965 int ret;
966
967 if (!enable) {
968 v4l2_subdev_disable_streams(csis->source.sd,
969 csis->source.pad->index, BIT(0));
970
971 mipi_csis_stop_stream(csis);
972 if (csis->debug.enable)
973 mipi_csis_log_counters(csis, true);
974
975 pm_runtime_put(csis->dev);
976
977 return 0;
978 }
979
980 state = v4l2_subdev_lock_and_get_active_state(sd);
981
982 format = v4l2_subdev_state_get_format(state, CSIS_PAD_SINK);
983 csis_fmt = find_csis_format(format->code);
984
985 ret = mipi_csis_calculate_params(csis, csis_fmt);
986 if (ret < 0)
987 goto err_unlock;
988
989 mipi_csis_clear_counters(csis);
990
991 ret = pm_runtime_resume_and_get(csis->dev);
992 if (ret < 0)
993 goto err_unlock;
994
995 mipi_csis_start_stream(csis, format, csis_fmt);
996
997 ret = v4l2_subdev_enable_streams(csis->source.sd,
998 csis->source.pad->index, BIT(0));
999 if (ret < 0)
1000 goto err_stop;
1001
1002 mipi_csis_log_counters(csis, true);
1003
1004 v4l2_subdev_unlock_state(state);
1005
1006 return 0;
1007
1008 err_stop:
1009 mipi_csis_stop_stream(csis);
1010 pm_runtime_put(csis->dev);
1011 err_unlock:
1012 v4l2_subdev_unlock_state(state);
1013
1014 return ret;
1015 }
1016
1017 static int mipi_csis_enum_mbus_code(struct v4l2_subdev *sd,
1018 struct v4l2_subdev_state *sd_state,
1019 struct v4l2_subdev_mbus_code_enum *code)
1020 {
1021 /*
1022 * The CSIS can't transcode in any way, the source format is identical
1023 * to the sink format.
1024 */
1025 if (code->pad == CSIS_PAD_SOURCE) {
1026 struct v4l2_mbus_framefmt *fmt;
1027
1028 if (code->index > 0)
1029 return -EINVAL;
1030
1031 fmt = v4l2_subdev_state_get_format(sd_state, code->pad);
1032 code->code = fmt->code;
1033 return 0;
1034 }
1035
1036 if (code->pad != CSIS_PAD_SINK)
1037 return -EINVAL;
1038
1039 if (code->index >= ARRAY_SIZE(mipi_csis_formats))
1040 return -EINVAL;
1041
1042 code->code = mipi_csis_formats[code->index].code;
1043
1044 return 0;
1045 }
1046
1047 static int mipi_csis_set_fmt(struct v4l2_subdev *sd,
1048 struct v4l2_subdev_state *sd_state,
1049 struct v4l2_subdev_format *sdformat)
1050 {
1051 struct csis_pix_format const *csis_fmt;
1052 struct v4l2_mbus_framefmt *fmt;
1053 unsigned int align;
1054
1055 /*
1056 * The CSIS can't transcode in any way, the source format can't be
1057 * modified.
1058 */
1059 if (sdformat->pad == CSIS_PAD_SOURCE)
1060 return v4l2_subdev_get_fmt(sd, sd_state, sdformat);
1061
1062 if (sdformat->pad != CSIS_PAD_SINK)
1063 return -EINVAL;
1064
1065 /*
1066 * Validate the media bus code and clamp and align the size.
1067 *
1068 * The total number of bits per line must be a multiple of 8. We thus
1069 * need to align the width for formats that are not multiples of 8
1070 * bits.
1071 */
1072 csis_fmt = find_csis_format(sdformat->format.code);
1073 if (!csis_fmt)
1074 csis_fmt = &mipi_csis_formats[0];
1075
1076 switch (csis_fmt->width % 8) {
1077 case 0:
1078 align = 0;
1079 break;
1080 case 4:
1081 align = 1;
1082 break;
1083 case 2:
1084 case 6:
1085 align = 2;
1086 break;
1087 default:
1088 /* 1, 3, 5, 7 */
1089 align = 3;
1090 break;
1091 }
1092
1093 v4l_bound_align_image(&sdformat->format.width, 1,
1094 CSIS_MAX_PIX_WIDTH, align,
1095 &sdformat->format.height, 1,
1096 CSIS_MAX_PIX_HEIGHT, 0, 0);
1097
1098 fmt = v4l2_subdev_state_get_format(sd_state, sdformat->pad);
1099
1100 fmt->code = csis_fmt->code;
1101 fmt->width = sdformat->format.width;
1102 fmt->height = sdformat->format.height;
1103 fmt->field = V4L2_FIELD_NONE;
1104 fmt->colorspace = sdformat->format.colorspace;
1105 fmt->quantization = sdformat->format.quantization;
1106 fmt->xfer_func = sdformat->format.xfer_func;
1107 fmt->ycbcr_enc = sdformat->format.ycbcr_enc;
1108
1109 sdformat->format = *fmt;
1110
1111 /* Propagate the format from sink to source. */
1112 fmt = v4l2_subdev_state_get_format(sd_state, CSIS_PAD_SOURCE);
1113 *fmt = sdformat->format;
1114
1115 /* The format on the source pad might change due to unpacking. */
1116 fmt->code = csis_fmt->output;
1117
1118 return 0;
1119 }
1120
1121 static int mipi_csis_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
1122 struct v4l2_mbus_frame_desc *fd)
1123 {
1124 struct v4l2_mbus_frame_desc_entry *entry = &fd->entry[0];
1125 const struct csis_pix_format *csis_fmt;
1126 const struct v4l2_mbus_framefmt *fmt;
1127 struct v4l2_subdev_state *state;
1128
1129 if (pad != CSIS_PAD_SOURCE)
1130 return -EINVAL;
1131
1132 state = v4l2_subdev_lock_and_get_active_state(sd);
1133 fmt = v4l2_subdev_state_get_format(state, CSIS_PAD_SOURCE);
1134 csis_fmt = find_csis_format(fmt->code);
1135 v4l2_subdev_unlock_state(state);
1136
1137 if (!csis_fmt)
1138 return -EPIPE;
1139
1140 fd->type = V4L2_MBUS_FRAME_DESC_TYPE_PARALLEL;
1141 fd->num_entries = 1;
1142
1143 entry->flags = 0;
1144 entry->pixelcode = csis_fmt->code;
1145 entry->bus.csi2.vc = 0;
1146 entry->bus.csi2.dt = csis_fmt->data_type;
1147
1148 return 0;
1149 }
1150
1151 static int mipi_csis_init_state(struct v4l2_subdev *sd,
1152 struct v4l2_subdev_state *sd_state)
1153 {
1154 struct v4l2_subdev_format fmt = {
1155 .pad = CSIS_PAD_SINK,
1156 };
1157
1158 fmt.format.code = mipi_csis_formats[0].code;
1159 fmt.format.width = MIPI_CSIS_DEF_PIX_WIDTH;
1160 fmt.format.height = MIPI_CSIS_DEF_PIX_HEIGHT;
1161
1162 fmt.format.colorspace = V4L2_COLORSPACE_SMPTE170M;
1163 fmt.format.xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt.format.colorspace);
1164 fmt.format.ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt.format.colorspace);
1165 fmt.format.quantization =
1166 V4L2_MAP_QUANTIZATION_DEFAULT(false, fmt.format.colorspace,
1167 fmt.format.ycbcr_enc);
1168
1169 return mipi_csis_set_fmt(sd, sd_state, &fmt);
1170 }
1171
1172 static int mipi_csis_log_status(struct v4l2_subdev *sd)
1173 {
1174 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
1175
1176 mipi_csis_log_counters(csis, true);
1177 if (csis->debug.enable)
1178 mipi_csis_dump_regs(csis);
1179
1180 return 0;
1181 }
1182
1183 static int mipi_csis_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
1184 struct v4l2_event_subscription *sub)
1185 {
1186 if (sub->type != V4L2_EVENT_FRAME_SYNC)
1187 return -EINVAL;
1188
1189 /* V4L2_EVENT_FRAME_SYNC doesn't require an id, so zero should be set */
1190 if (sub->id != 0)
1191 return -EINVAL;
1192
1193 return v4l2_event_subscribe(fh, sub, 0, NULL);
1194 }
1195
1196 static const struct v4l2_subdev_core_ops mipi_csis_core_ops = {
1197 .log_status = mipi_csis_log_status,
1198 .subscribe_event = mipi_csis_subscribe_event,
1199 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1200 };
1201
1202 static const struct v4l2_subdev_video_ops mipi_csis_video_ops = {
1203 .s_stream = mipi_csis_s_stream,
1204 };
1205
1206 static const struct v4l2_subdev_pad_ops mipi_csis_pad_ops = {
1207 .enum_mbus_code = mipi_csis_enum_mbus_code,
1208 .get_fmt = v4l2_subdev_get_fmt,
1209 .set_fmt = mipi_csis_set_fmt,
1210 .get_frame_desc = mipi_csis_get_frame_desc,
1211 };
1212
1213 static const struct v4l2_subdev_ops mipi_csis_subdev_ops = {
1214 .core = &mipi_csis_core_ops,
1215 .video = &mipi_csis_video_ops,
1216 .pad = &mipi_csis_pad_ops,
1217 };
1218
1219 static const struct v4l2_subdev_internal_ops mipi_csis_internal_ops = {
1220 .init_state = mipi_csis_init_state,
1221 };
1222
1223 /* -----------------------------------------------------------------------------
1224 * Media entity operations
1225 */
1226
1227 static int mipi_csis_link_setup(struct media_entity *entity,
1228 const struct media_pad *local_pad,
1229 const struct media_pad *remote_pad, u32 flags)
1230 {
1231 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
1232 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
1233 struct v4l2_subdev *remote_sd;
1234
1235 dev_dbg(csis->dev, "link setup %s -> %s", remote_pad->entity->name,
1236 local_pad->entity->name);
1237
1238 /* We only care about the link to the source. */
1239 if (!(local_pad->flags & MEDIA_PAD_FL_SINK))
1240 return 0;
1241
1242 remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity);
1243
1244 if (flags & MEDIA_LNK_FL_ENABLED) {
1245 if (csis->source.sd)
1246 return -EBUSY;
1247
1248 csis->source.sd = remote_sd;
1249 csis->source.pad = remote_pad;
1250 } else {
1251 csis->source.sd = NULL;
1252 csis->source.pad = NULL;
1253 }
1254
1255 return 0;
1256 }
1257
1258 static const struct media_entity_operations mipi_csis_entity_ops = {
1259 .link_setup = mipi_csis_link_setup,
1260 .link_validate = v4l2_subdev_link_validate,
1261 .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
1262 };
1263
1264 /* -----------------------------------------------------------------------------
1265 * Async subdev notifier
1266 */
1267
1268 static struct mipi_csis_device *
1269 mipi_notifier_to_csis_state(struct v4l2_async_notifier *n)
1270 {
1271 return container_of(n, struct mipi_csis_device, notifier);
1272 }
1273
1274 static int mipi_csis_notify_bound(struct v4l2_async_notifier *notifier,
1275 struct v4l2_subdev *sd,
1276 struct v4l2_async_connection *asd)
1277 {
1278 struct mipi_csis_device *csis = mipi_notifier_to_csis_state(notifier);
1279 struct media_pad *sink = &csis->sd.entity.pads[CSIS_PAD_SINK];
1280
1281 return v4l2_create_fwnode_links_to_pad(sd, sink, 0);
1282 }
1283
1284 static const struct v4l2_async_notifier_operations mipi_csis_notify_ops = {
1285 .bound = mipi_csis_notify_bound,
1286 };
1287
1288 static int mipi_csis_async_register(struct mipi_csis_device *csis)
1289 {
1290 struct v4l2_fwnode_endpoint vep = {
1291 .bus_type = V4L2_MBUS_CSI2_DPHY,
1292 };
1293 struct v4l2_async_connection *asd;
1294 struct fwnode_handle *ep;
1295 unsigned int i;
1296 int ret;
1297
1298 v4l2_async_subdev_nf_init(&csis->notifier, &csis->sd);
1299
1300 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csis->dev), 0, 0,
1301 FWNODE_GRAPH_ENDPOINT_NEXT);
1302 if (!ep)
1303 return -ENOTCONN;
1304
1305 ret = v4l2_fwnode_endpoint_parse(ep, &vep);
1306 if (ret)
1307 goto err_parse;
1308
1309 for (i = 0; i < vep.bus.mipi_csi2.num_data_lanes; ++i) {
1310 if (vep.bus.mipi_csi2.data_lanes[i] != i + 1) {
1311 dev_err(csis->dev,
1312 "data lanes reordering is not supported");
1313 ret = -EINVAL;
1314 goto err_parse;
1315 }
1316 }
1317
1318 csis->bus = vep.bus.mipi_csi2;
1319
1320 dev_dbg(csis->dev, "data lanes: %d\n", csis->bus.num_data_lanes);
1321 dev_dbg(csis->dev, "flags: 0x%08x\n", csis->bus.flags);
1322
1323 asd = v4l2_async_nf_add_fwnode_remote(&csis->notifier, ep,
1324 struct v4l2_async_connection);
1325 if (IS_ERR(asd)) {
1326 ret = PTR_ERR(asd);
1327 goto err_parse;
1328 }
1329
1330 fwnode_handle_put(ep);
1331
1332 csis->notifier.ops = &mipi_csis_notify_ops;
1333
1334 ret = v4l2_async_nf_register(&csis->notifier);
1335 if (ret)
1336 return ret;
1337
1338 return v4l2_async_register_subdev(&csis->sd);
1339
1340 err_parse:
1341 fwnode_handle_put(ep);
1342
1343 return ret;
1344 }
1345
1346 /* -----------------------------------------------------------------------------
1347 * Suspend/resume
1348 */
1349
1350 static int mipi_csis_runtime_suspend(struct device *dev)
1351 {
1352 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1353 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
1354 int ret;
1355
1356 ret = mipi_csis_phy_disable(csis);
1357 if (ret)
1358 return -EAGAIN;
1359
1360 mipi_csis_clk_disable(csis);
1361
1362 return 0;
1363 }
1364
1365 static int mipi_csis_runtime_resume(struct device *dev)
1366 {
1367 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1368 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
1369 int ret;
1370
1371 ret = mipi_csis_phy_enable(csis);
1372 if (ret)
1373 return -EAGAIN;
1374
1375 ret = mipi_csis_clk_enable(csis);
1376 if (ret) {
1377 mipi_csis_phy_disable(csis);
1378 return ret;
1379 }
1380
1381 return 0;
1382 }
1383
1384 static const struct dev_pm_ops mipi_csis_pm_ops = {
1385 RUNTIME_PM_OPS(mipi_csis_runtime_suspend, mipi_csis_runtime_resume,
1386 NULL)
1387 };
1388
1389 /* -----------------------------------------------------------------------------
1390 * Probe/remove & platform driver
1391 */
1392
1393 static int mipi_csis_subdev_init(struct mipi_csis_device *csis)
1394 {
1395 struct v4l2_subdev *sd = &csis->sd;
1396 int ret;
1397
1398 v4l2_subdev_init(sd, &mipi_csis_subdev_ops);
1399 sd->internal_ops = &mipi_csis_internal_ops;
1400 sd->owner = THIS_MODULE;
1401 snprintf(sd->name, sizeof(sd->name), "csis-%s",
1402 dev_name(csis->dev));
1403
1404 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1405 sd->ctrl_handler = NULL;
1406
1407 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
1408 sd->entity.ops = &mipi_csis_entity_ops;
1409
1410 sd->dev = csis->dev;
1411
1412 csis->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK
1413 | MEDIA_PAD_FL_MUST_CONNECT;
1414 csis->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE
1415 | MEDIA_PAD_FL_MUST_CONNECT;
1416 ret = media_entity_pads_init(&sd->entity, CSIS_PADS_NUM, csis->pads);
1417 if (ret)
1418 return ret;
1419
1420 ret = v4l2_subdev_init_finalize(sd);
1421 if (ret) {
1422 media_entity_cleanup(&sd->entity);
1423 return ret;
1424 }
1425
1426 return 0;
1427 }
1428
1429 static int mipi_csis_parse_dt(struct mipi_csis_device *csis)
1430 {
1431 struct device_node *node = csis->dev->of_node;
1432
1433 if (of_property_read_u32(node, "clock-frequency",
1434 &csis->clk_frequency))
1435 csis->clk_frequency = DEFAULT_SCLK_CSIS_FREQ;
1436
1437 return 0;
1438 }
1439
1440 static int mipi_csis_probe(struct platform_device *pdev)
1441 {
1442 struct device *dev = &pdev->dev;
1443 struct mipi_csis_device *csis;
1444 int irq;
1445 int ret;
1446
1447 csis = devm_kzalloc(dev, sizeof(*csis), GFP_KERNEL);
1448 if (!csis)
1449 return -ENOMEM;
1450
1451 spin_lock_init(&csis->slock);
1452
1453 csis->dev = dev;
1454 csis->info = of_device_get_match_data(dev);
1455
1456 memcpy(csis->events, mipi_csis_events, sizeof(csis->events));
1457
1458 /* Parse DT properties. */
1459 ret = mipi_csis_parse_dt(csis);
1460 if (ret < 0) {
1461 dev_err(dev, "Failed to parse device tree: %d\n", ret);
1462 return ret;
1463 }
1464
1465 /* Acquire resources. */
1466 csis->regs = devm_platform_ioremap_resource(pdev, 0);
1467 if (IS_ERR(csis->regs))
1468 return PTR_ERR(csis->regs);
1469
1470 irq = platform_get_irq(pdev, 0);
1471 if (irq < 0)
1472 return irq;
1473
1474 ret = mipi_csis_phy_init(csis);
1475 if (ret < 0)
1476 return ret;
1477
1478 ret = mipi_csis_clk_get(csis);
1479 if (ret < 0)
1480 return ret;
1481
1482 /* Reset PHY and enable the clocks. */
1483 mipi_csis_phy_reset(csis);
1484
1485 /* Now that the hardware is initialized, request the interrupt. */
1486 ret = devm_request_irq(dev, irq, mipi_csis_irq_handler, 0,
1487 dev_name(dev), csis);
1488 if (ret) {
1489 dev_err(dev, "Interrupt request failed\n");
1490 return ret;
1491 }
1492
1493 /* Initialize and register the subdev. */
1494 ret = mipi_csis_subdev_init(csis);
1495 if (ret < 0)
1496 return ret;
1497
1498 platform_set_drvdata(pdev, &csis->sd);
1499
1500 ret = mipi_csis_async_register(csis);
1501 if (ret < 0) {
1502 dev_err(dev, "async register failed: %d\n", ret);
1503 goto err_cleanup;
1504 }
1505
1506 /* Initialize debugfs. */
1507 mipi_csis_debugfs_init(csis);
1508
1509 /* Enable runtime PM. */
1510 pm_runtime_enable(dev);
1511 if (!pm_runtime_enabled(dev)) {
1512 ret = mipi_csis_runtime_resume(dev);
1513 if (ret < 0)
1514 goto err_unregister_all;
1515 }
1516
1517 dev_info(dev, "lanes: %d, freq: %u\n",
1518 csis->bus.num_data_lanes, csis->clk_frequency);
1519
1520 return 0;
1521
1522 err_unregister_all:
1523 mipi_csis_debugfs_exit(csis);
1524 err_cleanup:
1525 v4l2_subdev_cleanup(&csis->sd);
1526 media_entity_cleanup(&csis->sd.entity);
1527 v4l2_async_nf_unregister(&csis->notifier);
1528 v4l2_async_nf_cleanup(&csis->notifier);
1529 v4l2_async_unregister_subdev(&csis->sd);
1530
1531 return ret;
1532 }
1533
1534 static void mipi_csis_remove(struct platform_device *pdev)
1535 {
1536 struct v4l2_subdev *sd = platform_get_drvdata(pdev);
1537 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
1538
1539 mipi_csis_debugfs_exit(csis);
1540 v4l2_async_nf_unregister(&csis->notifier);
1541 v4l2_async_nf_cleanup(&csis->notifier);
1542 v4l2_async_unregister_subdev(&csis->sd);
1543
1544 if (!pm_runtime_enabled(&pdev->dev))
1545 mipi_csis_runtime_suspend(&pdev->dev);
1546
1547 pm_runtime_disable(&pdev->dev);
1548 v4l2_subdev_cleanup(&csis->sd);
1549 media_entity_cleanup(&csis->sd.entity);
1550 pm_runtime_set_suspended(&pdev->dev);
1551 }
1552
1553 static const struct of_device_id mipi_csis_of_match[] = {
1554 {
1555 .compatible = "fsl,imx7-mipi-csi2",
1556 .data = &(const struct mipi_csis_info){
1557 .version = MIPI_CSIS_V3_3,
1558 .num_clocks = 3,
1559 },
1560 }, {
1561 .compatible = "fsl,imx8mm-mipi-csi2",
1562 .data = &(const struct mipi_csis_info){
1563 .version = MIPI_CSIS_V3_6_3,
1564 .num_clocks = 4,
1565 },
1566 },
1567 { /* sentinel */ },
1568 };
1569 MODULE_DEVICE_TABLE(of, mipi_csis_of_match);
1570
1571 static struct platform_driver mipi_csis_driver = {
1572 .probe = mipi_csis_probe,
1573 .remove_new = mipi_csis_remove,
1574 .driver = {
1575 .of_match_table = mipi_csis_of_match,
1576 .name = CSIS_DRIVER_NAME,
1577 .pm = pm_ptr(&mipi_csis_pm_ops),
1578 },
1579 };
1580
1581 module_platform_driver(mipi_csis_driver);
1582
1583 MODULE_DESCRIPTION("i.MX7 & i.MX8 MIPI CSI-2 receiver driver");
1584 MODULE_LICENSE("GPL v2");
1585 MODULE_ALIAS("platform:imx-mipi-csi2");
Kernel DRM miscellaneous fixes and cross-tree changes