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drm/tests: hdmi: Fix memory leaks in drm_display_mode_from_cea_vic()
[drm/drm-misc.git] / drivers / scsi / aacraid / aacraid.h
blob1d09d3ac6aa45003c1fb825fc970457af0fb55a0
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Adaptec AAC series RAID controller driver
4 * (c) Copyright 2001 Red Hat Inc. <alan@redhat.com>
5 *
6 * based on the old aacraid driver that is..
7 * Adaptec aacraid device driver for Linux.
8 *
9 * Copyright (c) 2000-2010 Adaptec, Inc.
10 * 2010-2015 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
11 * 2016-2017 Microsemi Corp. (aacraid@microsemi.com)
12 *
13 * Module Name:
14 * aacraid.h
15 *
16 * Abstract: Contains all routines for control of the aacraid driver
17 */
18
19 #ifndef _AACRAID_H_
20 #define _AACRAID_H_
21 #ifndef dprintk
22 # define dprintk(x)
23 #endif
24 /* eg: if (nblank(dprintk(x))) */
25 #define _nblank(x) #x
26 #define nblank(x) _nblank(x)[0]
27
28 #include <linux/interrupt.h>
29 #include <linux/completion.h>
30 #include <linux/pci.h>
31 #include <scsi/scsi_host.h>
32 #include <scsi/scsi_cmnd.h>
33
34 /*------------------------------------------------------------------------------
35 * D E F I N E S
36 *----------------------------------------------------------------------------*/
37
38 #define AAC_MAX_MSIX 32 /* vectors */
39 #define AAC_PCI_MSI_ENABLE 0x8000
40
41 enum {
42 AAC_ENABLE_INTERRUPT = 0x0,
43 AAC_DISABLE_INTERRUPT,
44 AAC_ENABLE_MSIX,
45 AAC_DISABLE_MSIX,
46 AAC_CLEAR_AIF_BIT,
47 AAC_CLEAR_SYNC_BIT,
48 AAC_ENABLE_INTX
49 };
50
51 #define AAC_INT_MODE_INTX (1<<0)
52 #define AAC_INT_MODE_MSI (1<<1)
53 #define AAC_INT_MODE_AIF (1<<2)
54 #define AAC_INT_MODE_SYNC (1<<3)
55 #define AAC_INT_MODE_MSIX (1<<16)
56
57 #define AAC_INT_ENABLE_TYPE1_INTX 0xfffffffb
58 #define AAC_INT_ENABLE_TYPE1_MSIX 0xfffffffa
59 #define AAC_INT_DISABLE_ALL 0xffffffff
60
61 /* Bit definitions in IOA->Host Interrupt Register */
62 #define PMC_TRANSITION_TO_OPERATIONAL (1<<31)
63 #define PMC_IOARCB_TRANSFER_FAILED (1<<28)
64 #define PMC_IOA_UNIT_CHECK (1<<27)
65 #define PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE (1<<26)
66 #define PMC_CRITICAL_IOA_OP_IN_PROGRESS (1<<25)
67 #define PMC_IOARRIN_LOST (1<<4)
68 #define PMC_SYSTEM_BUS_MMIO_ERROR (1<<3)
69 #define PMC_IOA_PROCESSOR_IN_ERROR_STATE (1<<2)
70 #define PMC_HOST_RRQ_VALID (1<<1)
71 #define PMC_OPERATIONAL_STATUS (1<<31)
72 #define PMC_ALLOW_MSIX_VECTOR0 (1<<0)
73
74 #define PMC_IOA_ERROR_INTERRUPTS (PMC_IOARCB_TRANSFER_FAILED | \
75 PMC_IOA_UNIT_CHECK | \
76 PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE | \
77 PMC_IOARRIN_LOST | \
78 PMC_SYSTEM_BUS_MMIO_ERROR | \
79 PMC_IOA_PROCESSOR_IN_ERROR_STATE)
80
81 #define PMC_ALL_INTERRUPT_BITS (PMC_IOA_ERROR_INTERRUPTS | \
82 PMC_HOST_RRQ_VALID | \
83 PMC_TRANSITION_TO_OPERATIONAL | \
84 PMC_ALLOW_MSIX_VECTOR0)
85 #define PMC_GLOBAL_INT_BIT2 0x00000004
86 #define PMC_GLOBAL_INT_BIT0 0x00000001
87
88 #ifndef AAC_DRIVER_BUILD
89 # define AAC_DRIVER_BUILD 50983
90 # define AAC_DRIVER_BRANCH "-custom"
91 #endif
92 #define MAXIMUM_NUM_CONTAINERS 32
93
94 #define AAC_NUM_MGT_FIB 8
95 #define AAC_NUM_IO_FIB (1024 - AAC_NUM_MGT_FIB)
96 #define AAC_NUM_FIB (AAC_NUM_IO_FIB + AAC_NUM_MGT_FIB)
97
98 #define AAC_MAX_LUN 256
99
100 #define AAC_MAX_HOSTPHYSMEMPAGES (0xfffff)
101 #define AAC_MAX_32BIT_SGBCOUNT ((unsigned short)256)
102
103 #define AAC_DEBUG_INSTRUMENT_AIF_DELETE
104
105 #define AAC_MAX_NATIVE_TARGETS 1024
106 /* Thor: 5 phys. buses: #0: empty, 1-4: 256 targets each */
107 #define AAC_MAX_BUSES 5
108 #define AAC_MAX_TARGETS 256
109 #define AAC_BUS_TARGET_LOOP (AAC_MAX_BUSES * AAC_MAX_TARGETS)
110 #define AAC_MAX_NATIVE_SIZE 2048
111 #define FW_ERROR_BUFFER_SIZE 512
112 #define AAC_SA_TIMEOUT 180
113 #define AAC_ARC_TIMEOUT 60
114
115 #define get_bus_number(x) (x/AAC_MAX_TARGETS)
116 #define get_target_number(x) (x%AAC_MAX_TARGETS)
117
118 /* Thor AIF events */
119 #define SA_AIF_HOTPLUG (1<<1)
120 #define SA_AIF_HARDWARE (1<<2)
121 #define SA_AIF_PDEV_CHANGE (1<<4)
122 #define SA_AIF_LDEV_CHANGE (1<<5)
123 #define SA_AIF_BPSTAT_CHANGE (1<<30)
124 #define SA_AIF_BPCFG_CHANGE (1U<<31)
125
126 #define HBA_MAX_SG_EMBEDDED 28
127 #define HBA_MAX_SG_SEPARATE 90
128 #define HBA_SENSE_DATA_LEN_MAX 32
129 #define HBA_REQUEST_TAG_ERROR_FLAG 0x00000002
130 #define HBA_SGL_FLAGS_EXT 0x80000000UL
131
132 struct aac_hba_sgl {
133 u32 addr_lo; /* Lower 32-bits of SGL element address */
134 u32 addr_hi; /* Upper 32-bits of SGL element address */
135 u32 len; /* Length of SGL element in bytes */
136 u32 flags; /* SGL element flags */
137 };
138
139 enum {
140 HBA_IU_TYPE_SCSI_CMD_REQ = 0x40,
141 HBA_IU_TYPE_SCSI_TM_REQ = 0x41,
142 HBA_IU_TYPE_SATA_REQ = 0x42,
143 HBA_IU_TYPE_RESP = 0x60,
144 HBA_IU_TYPE_COALESCED_RESP = 0x61,
145 HBA_IU_TYPE_INT_COALESCING_CFG_REQ = 0x70
146 };
147
148 enum {
149 HBA_CMD_BYTE1_DATA_DIR_IN = 0x1,
150 HBA_CMD_BYTE1_DATA_DIR_OUT = 0x2,
151 HBA_CMD_BYTE1_DATA_TYPE_DDR = 0x4,
152 HBA_CMD_BYTE1_CRYPTO_ENABLE = 0x8
153 };
154
155 enum {
156 HBA_CMD_BYTE1_BITOFF_DATA_DIR_IN = 0x0,
157 HBA_CMD_BYTE1_BITOFF_DATA_DIR_OUT,
158 HBA_CMD_BYTE1_BITOFF_DATA_TYPE_DDR,
159 HBA_CMD_BYTE1_BITOFF_CRYPTO_ENABLE
160 };
161
162 enum {
163 HBA_RESP_DATAPRES_NO_DATA = 0x0,
164 HBA_RESP_DATAPRES_RESPONSE_DATA,
165 HBA_RESP_DATAPRES_SENSE_DATA
166 };
167
168 enum {
169 HBA_RESP_SVCRES_TASK_COMPLETE = 0x0,
170 HBA_RESP_SVCRES_FAILURE,
171 HBA_RESP_SVCRES_TMF_COMPLETE,
172 HBA_RESP_SVCRES_TMF_SUCCEEDED,
173 HBA_RESP_SVCRES_TMF_REJECTED,
174 HBA_RESP_SVCRES_TMF_LUN_INVALID
175 };
176
177 enum {
178 HBA_RESP_STAT_IO_ERROR = 0x1,
179 HBA_RESP_STAT_IO_ABORTED,
180 HBA_RESP_STAT_NO_PATH_TO_DEVICE,
181 HBA_RESP_STAT_INVALID_DEVICE,
182 HBA_RESP_STAT_HBAMODE_DISABLED = 0xE,
183 HBA_RESP_STAT_UNDERRUN = 0x51,
184 HBA_RESP_STAT_OVERRUN = 0x75
185 };
186
187 struct aac_hba_cmd_req {
188 u8 iu_type; /* HBA information unit type */
189 /*
190 * byte1:
191 * [1:0] DIR - 0=No data, 0x1 = IN, 0x2 = OUT
192 * [2] TYPE - 0=PCI, 1=DDR
193 * [3] CRYPTO_ENABLE - 0=Crypto disabled, 1=Crypto enabled
194 */
195 u8 byte1;
196 u8 reply_qid; /* Host reply queue to post response to */
197 u8 reserved1;
198 __le32 it_nexus; /* Device handle for the request */
199 __le32 request_id; /* Sender context */
200 /* Lower 32-bits of tweak value for crypto enabled IOs */
201 __le32 tweak_value_lo;
202 u8 cdb[16]; /* SCSI CDB of the command */
203 u8 lun[8]; /* SCSI LUN of the command */
204
205 /* Total data length in bytes to be read/written (if any) */
206 __le32 data_length;
207
208 /* [2:0] Task Attribute, [6:3] Command Priority */
209 u8 attr_prio;
210
211 /* Number of SGL elements embedded in the HBA req */
212 u8 emb_data_desc_count;
213
214 __le16 dek_index; /* DEK index for crypto enabled IOs */
215
216 /* Lower 32-bits of reserved error data target location on the host */
217 __le32 error_ptr_lo;
218
219 /* Upper 32-bits of reserved error data target location on the host */
220 __le32 error_ptr_hi;
221
222 /* Length of reserved error data area on the host in bytes */
223 __le32 error_length;
224
225 /* Upper 32-bits of tweak value for crypto enabled IOs */
226 __le32 tweak_value_hi;
227
228 struct aac_hba_sgl sge[HBA_MAX_SG_SEPARATE+2]; /* SG list space */
229
230 /*
231 * structure must not exceed
232 * AAC_MAX_NATIVE_SIZE-FW_ERROR_BUFFER_SIZE
233 */
234 };
235
236 /* Task Management Functions (TMF) */
237 #define HBA_TMF_ABORT_TASK 0x01
238 #define HBA_TMF_LUN_RESET 0x08
239
240 struct aac_hba_tm_req {
241 u8 iu_type; /* HBA information unit type */
242 u8 reply_qid; /* Host reply queue to post response to */
243 u8 tmf; /* Task management function */
244 u8 reserved1;
245
246 __le32 it_nexus; /* Device handle for the command */
247
248 u8 lun[8]; /* SCSI LUN */
249
250 /* Used to hold sender context. */
251 __le32 request_id; /* Sender context */
252 __le32 reserved2;
253
254 /* Request identifier of managed task */
255 __le32 managed_request_id; /* Sender context being managed */
256 __le32 reserved3;
257
258 /* Lower 32-bits of reserved error data target location on the host */
259 __le32 error_ptr_lo;
260 /* Upper 32-bits of reserved error data target location on the host */
261 __le32 error_ptr_hi;
262 /* Length of reserved error data area on the host in bytes */
263 __le32 error_length;
264 };
265
266 struct aac_hba_reset_req {
267 u8 iu_type; /* HBA information unit type */
268 /* 0 - reset specified device, 1 - reset all devices */
269 u8 reset_type;
270 u8 reply_qid; /* Host reply queue to post response to */
271 u8 reserved1;
272
273 __le32 it_nexus; /* Device handle for the command */
274 __le32 request_id; /* Sender context */
275 /* Lower 32-bits of reserved error data target location on the host */
276 __le32 error_ptr_lo;
277 /* Upper 32-bits of reserved error data target location on the host */
278 __le32 error_ptr_hi;
279 /* Length of reserved error data area on the host in bytes */
280 __le32 error_length;
281 };
282
283 struct aac_hba_resp {
284 u8 iu_type; /* HBA information unit type */
285 u8 reserved1[3];
286 __le32 request_identifier; /* sender context */
287 __le32 reserved2;
288 u8 service_response; /* SCSI service response */
289 u8 status; /* SCSI status */
290 u8 datapres; /* [1:0] - data present, [7:2] - reserved */
291 u8 sense_response_data_len; /* Sense/response data length */
292 __le32 residual_count; /* Residual data length in bytes */
293 /* Sense/response data */
294 u8 sense_response_buf[HBA_SENSE_DATA_LEN_MAX];
295 };
296
297 struct aac_native_hba {
298 union {
299 struct aac_hba_cmd_req cmd;
300 struct aac_hba_tm_req tmr;
301 u8 cmd_bytes[AAC_MAX_NATIVE_SIZE-FW_ERROR_BUFFER_SIZE];
302 } cmd;
303 union {
304 struct aac_hba_resp err;
305 u8 resp_bytes[FW_ERROR_BUFFER_SIZE];
306 } resp;
307 };
308
309 #define CISS_REPORT_PHYSICAL_LUNS 0xc3
310 #define WRITE_HOST_WELLNESS 0xa5
311 #define CISS_IDENTIFY_PHYSICAL_DEVICE 0x15
312 #define BMIC_IN 0x26
313 #define BMIC_OUT 0x27
314
315 struct aac_ciss_phys_luns_resp {
316 u8 list_length[4]; /* LUN list length (N-7, big endian) */
317 u8 resp_flag; /* extended response_flag */
318 u8 reserved[3];
319 struct _ciss_lun {
320 u8 tid[3]; /* Target ID */
321 u8 bus; /* Bus, flag (bits 6,7) */
322 u8 level3[2];
323 u8 level2[2];
324 u8 node_ident[16]; /* phys. node identifier */
325 } lun[]; /* List of phys. devices */
326 };
327
328 /*
329 * Interrupts
330 */
331 #define AAC_MAX_HRRQ 64
332
333 struct aac_ciss_identify_pd {
334 u8 scsi_bus; /* SCSI Bus number on controller */
335 u8 scsi_id; /* SCSI ID on this bus */
336 u16 block_size; /* sector size in bytes */
337 u32 total_blocks; /* number for sectors on drive */
338 u32 reserved_blocks; /* controller reserved (RIS) */
339 u8 model[40]; /* Physical Drive Model */
340 u8 serial_number[40]; /* Drive Serial Number */
341 u8 firmware_revision[8]; /* drive firmware revision */
342 u8 scsi_inquiry_bits; /* inquiry byte 7 bits */
343 u8 compaq_drive_stamp; /* 0 means drive not stamped */
344 u8 last_failure_reason;
345
346 u8 flags;
347 u8 more_flags;
348 u8 scsi_lun; /* SCSI LUN for phys drive */
349 u8 yet_more_flags;
350 u8 even_more_flags;
351 u32 spi_speed_rules; /* SPI Speed :Ultra disable diagnose */
352 u8 phys_connector[2]; /* connector number on controller */
353 u8 phys_box_on_bus; /* phys enclosure this drive resides */
354 u8 phys_bay_in_box; /* phys drv bay this drive resides */
355 u32 rpm; /* Drive rotational speed in rpm */
356 u8 device_type; /* type of drive */
357 u8 sata_version; /* only valid when drive_type is SATA */
358 u64 big_total_block_count;
359 u64 ris_starting_lba;
360 u32 ris_size;
361 u8 wwid[20];
362 u8 controller_phy_map[32];
363 u16 phy_count;
364 u8 phy_connected_dev_type[256];
365 u8 phy_to_drive_bay_num[256];
366 u16 phy_to_attached_dev_index[256];
367 u8 box_index;
368 u8 spitfire_support;
369 u16 extra_physical_drive_flags;
370 u8 negotiated_link_rate[256];
371 u8 phy_to_phy_map[256];
372 u8 redundant_path_present_map;
373 u8 redundant_path_failure_map;
374 u8 active_path_number;
375 u16 alternate_paths_phys_connector[8];
376 u8 alternate_paths_phys_box_on_port[8];
377 u8 multi_lun_device_lun_count;
378 u8 minimum_good_fw_revision[8];
379 u8 unique_inquiry_bytes[20];
380 u8 current_temperature_degreesC;
381 u8 temperature_threshold_degreesC;
382 u8 max_temperature_degreesC;
383 u8 logical_blocks_per_phys_block_exp; /* phyblocksize = 512 * 2^exp */
384 u16 current_queue_depth_limit;
385 u8 switch_name[10];
386 u16 switch_port;
387 u8 alternate_paths_switch_name[40];
388 u8 alternate_paths_switch_port[8];
389 u16 power_on_hours; /* valid only if gas gauge supported */
390 u16 percent_endurance_used; /* valid only if gas gauge supported. */
391 u8 drive_authentication;
392 u8 smart_carrier_authentication;
393 u8 smart_carrier_app_fw_version;
394 u8 smart_carrier_bootloader_fw_version;
395 u8 SanitizeSecureEraseSupport;
396 u8 DriveKeyFlags;
397 u8 encryption_key_name[64];
398 u32 misc_drive_flags;
399 u16 dek_index;
400 u16 drive_encryption_flags;
401 u8 sanitize_maximum_time[6];
402 u8 connector_info_mode;
403 u8 connector_info_number[4];
404 u8 long_connector_name[64];
405 u8 device_unique_identifier[16];
406 u8 padto_2K[17];
407 } __packed;
408
409 /*
410 * These macros convert from physical channels to virtual channels
411 */
412 #define CONTAINER_CHANNEL (0)
413 #define NATIVE_CHANNEL (1)
414 #define CONTAINER_TO_CHANNEL(cont) (CONTAINER_CHANNEL)
415 #define CONTAINER_TO_ID(cont) (cont)
416 #define CONTAINER_TO_LUN(cont) (0)
417 #define ENCLOSURE_CHANNEL (3)
418
419 #define PMC_DEVICE_S6 0x28b
420 #define PMC_DEVICE_S7 0x28c
421 #define PMC_DEVICE_S8 0x28d
422
423 #define aac_phys_to_logical(x) ((x)+1)
424 #define aac_logical_to_phys(x) ((x)?(x)-1:0)
425
426 /*
427 * These macros are for keeping track of
428 * character device state.
429 */
430 #define AAC_CHARDEV_UNREGISTERED (-1)
431 #define AAC_CHARDEV_NEEDS_REINIT (-2)
432
433 /* #define AAC_DETAILED_STATUS_INFO */
434
435 struct diskparm
436 {
437 int heads;
438 int sectors;
439 int cylinders;
440 };
441
442
443 /*
444 * Firmware constants
445 */
446
447 #define CT_NONE 0
448 #define CT_OK 218
449 #define FT_FILESYS 8 /* ADAPTEC's "FSA"(tm) filesystem */
450 #define FT_DRIVE 9 /* physical disk - addressable in scsi by bus/id/lun */
451
452 /*
453 * Host side memory scatter gather list
454 * Used by the adapter for read, write, and readdirplus operations
455 * We have separate 32 and 64 bit version because even
456 * on 64 bit systems not all cards support the 64 bit version
457 */
458 struct sgentry {
459 __le32 addr; /* 32-bit address. */
460 __le32 count; /* Length. */
461 };
462
463 struct user_sgentry {
464 u32 addr; /* 32-bit address. */
465 u32 count; /* Length. */
466 };
467
468 struct sgentry64 {
469 __le32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */
470 __le32 count; /* Length. */
471 };
472
473 struct user_sgentry64 {
474 u32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */
475 u32 count; /* Length. */
476 };
477
478 struct sgentryraw {
479 __le32 next; /* reserved for F/W use */
480 __le32 prev; /* reserved for F/W use */
481 __le32 addr[2];
482 __le32 count;
483 __le32 flags; /* reserved for F/W use */
484 };
485
486 struct user_sgentryraw {
487 u32 next; /* reserved for F/W use */
488 u32 prev; /* reserved for F/W use */
489 u32 addr[2];
490 u32 count;
491 u32 flags; /* reserved for F/W use */
492 };
493
494 struct sge_ieee1212 {
495 u32 addrLow;
496 u32 addrHigh;
497 u32 length;
498 u32 flags;
499 };
500
501 /*
502 * SGMAP
503 *
504 * This is the SGMAP structure for all commands that use
505 * 32-bit addressing.
506 */
507
508 struct sgmap {
509 __le32 count;
510 struct sgentry sg[];
511 };
512
513 struct user_sgmap {
514 u32 count;
515 struct user_sgentry sg[];
516 };
517
518 struct sgmap64 {
519 __le32 count;
520 struct sgentry64 sg[];
521 };
522
523 struct user_sgmap64 {
524 u32 count;
525 struct user_sgentry64 sg[];
526 };
527
528 struct sgmapraw {
529 __le32 count;
530 struct sgentryraw sg[];
531 };
532
533 struct creation_info
534 {
535 u8 buildnum; /* e.g., 588 */
536 u8 usec; /* e.g., 588 */
537 u8 via; /* e.g., 1 = FSU,
538 * 2 = API
539 */
540 u8 year; /* e.g., 1997 = 97 */
541 __le32 date; /*
542 * unsigned Month :4; // 1 - 12
543 * unsigned Day :6; // 1 - 32
544 * unsigned Hour :6; // 0 - 23
545 * unsigned Minute :6; // 0 - 60
546 * unsigned Second :6; // 0 - 60
547 */
548 __le32 serial[2]; /* e.g., 0x1DEADB0BFAFAF001 */
549 };
550
551
552 /*
553 * Define all the constants needed for the communication interface
554 */
555
556 /*
557 * Define how many queue entries each queue will have and the total
558 * number of entries for the entire communication interface. Also define
559 * how many queues we support.
560 *
561 * This has to match the controller
562 */
563
564 #define NUMBER_OF_COMM_QUEUES 8 // 4 command; 4 response
565 #define HOST_HIGH_CMD_ENTRIES 4
566 #define HOST_NORM_CMD_ENTRIES 8
567 #define ADAP_HIGH_CMD_ENTRIES 4
568 #define ADAP_NORM_CMD_ENTRIES 512
569 #define HOST_HIGH_RESP_ENTRIES 4
570 #define HOST_NORM_RESP_ENTRIES 512
571 #define ADAP_HIGH_RESP_ENTRIES 4
572 #define ADAP_NORM_RESP_ENTRIES 8
573
574 #define TOTAL_QUEUE_ENTRIES \
575 (HOST_NORM_CMD_ENTRIES + HOST_HIGH_CMD_ENTRIES + ADAP_NORM_CMD_ENTRIES + ADAP_HIGH_CMD_ENTRIES + \
576 HOST_NORM_RESP_ENTRIES + HOST_HIGH_RESP_ENTRIES + ADAP_NORM_RESP_ENTRIES + ADAP_HIGH_RESP_ENTRIES)
577
578
579 /*
580 * Set the queues on a 16 byte alignment
581 */
582
583 #define QUEUE_ALIGNMENT 16
584
585 /*
586 * The queue headers define the Communication Region queues. These
587 * are physically contiguous and accessible by both the adapter and the
588 * host. Even though all queue headers are in the same contiguous block
589 * they will be represented as individual units in the data structures.
590 */
591
592 struct aac_entry {
593 __le32 size; /* Size in bytes of Fib which this QE points to */
594 __le32 addr; /* Receiver address of the FIB */
595 };
596
597 /*
598 * The adapter assumes the ProducerIndex and ConsumerIndex are grouped
599 * adjacently and in that order.
600 */
601
602 struct aac_qhdr {
603 __le64 header_addr;/* Address to hand the adapter to access
604 to this queue head */
605 __le32 *producer; /* The producer index for this queue (host address) */
606 __le32 *consumer; /* The consumer index for this queue (host address) */
607 };
608
609 /*
610 * Define all the events which the adapter would like to notify
611 * the host of.
612 */
613
614 #define HostNormCmdQue 1 /* Change in host normal priority command queue */
615 #define HostHighCmdQue 2 /* Change in host high priority command queue */
616 #define HostNormRespQue 3 /* Change in host normal priority response queue */
617 #define HostHighRespQue 4 /* Change in host high priority response queue */
618 #define AdapNormRespNotFull 5
619 #define AdapHighRespNotFull 6
620 #define AdapNormCmdNotFull 7
621 #define AdapHighCmdNotFull 8
622 #define SynchCommandComplete 9
623 #define AdapInternalError 0xfe /* The adapter detected an internal error shutting down */
624
625 /*
626 * Define all the events the host wishes to notify the
627 * adapter of. The first four values much match the Qid the
628 * corresponding queue.
629 */
630
631 #define AdapNormCmdQue 2
632 #define AdapHighCmdQue 3
633 #define AdapNormRespQue 6
634 #define AdapHighRespQue 7
635 #define HostShutdown 8
636 #define HostPowerFail 9
637 #define FatalCommError 10
638 #define HostNormRespNotFull 11
639 #define HostHighRespNotFull 12
640 #define HostNormCmdNotFull 13
641 #define HostHighCmdNotFull 14
642 #define FastIo 15
643 #define AdapPrintfDone 16
644
645 /*
646 * Define all the queues that the adapter and host use to communicate
647 * Number them to match the physical queue layout.
648 */
649
650 enum aac_queue_types {
651 HostNormCmdQueue = 0, /* Adapter to host normal priority command traffic */
652 HostHighCmdQueue, /* Adapter to host high priority command traffic */
653 AdapNormCmdQueue, /* Host to adapter normal priority command traffic */
654 AdapHighCmdQueue, /* Host to adapter high priority command traffic */
655 HostNormRespQueue, /* Adapter to host normal priority response traffic */
656 HostHighRespQueue, /* Adapter to host high priority response traffic */
657 AdapNormRespQueue, /* Host to adapter normal priority response traffic */
658 AdapHighRespQueue /* Host to adapter high priority response traffic */
659 };
660
661 /*
662 * Assign type values to the FSA communication data structures
663 */
664
665 #define FIB_MAGIC 0x0001
666 #define FIB_MAGIC2 0x0004
667 #define FIB_MAGIC2_64 0x0005
668
669 /*
670 * Define the priority levels the FSA communication routines support.
671 */
672
673 #define FsaNormal 1
674
675 /* transport FIB header (PMC) */
676 struct aac_fib_xporthdr {
677 __le64 HostAddress; /* FIB host address w/o xport header */
678 __le32 Size; /* FIB size excluding xport header */
679 __le32 Handle; /* driver handle to reference the FIB */
680 __le64 Reserved[2];
681 };
682
683 #define ALIGN32 32
684
685 /*
686 * Define the FIB. The FIB is the where all the requested data and
687 * command information are put to the application on the FSA adapter.
688 */
689
690 struct aac_fibhdr {
691 __le32 XferState; /* Current transfer state for this CCB */
692 __le16 Command; /* Routing information for the destination */
693 u8 StructType; /* Type FIB */
694 u8 Unused; /* Unused */
695 __le16 Size; /* Size of this FIB in bytes */
696 __le16 SenderSize; /* Size of the FIB in the sender
697 (for response sizing) */
698 __le32 SenderFibAddress; /* Host defined data in the FIB */
699 union {
700 __le32 ReceiverFibAddress;/* Logical address of this FIB for
701 the adapter (old) */
702 __le32 SenderFibAddressHigh;/* upper 32bit of phys. FIB address */
703 __le32 TimeStamp; /* otherwise timestamp for FW internal use */
704 } u;
705 __le32 Handle; /* FIB handle used for MSGU commnunication */
706 u32 Previous; /* FW internal use */
707 u32 Next; /* FW internal use */
708 };
709
710 struct hw_fib {
711 struct aac_fibhdr header;
712 u8 data[512-sizeof(struct aac_fibhdr)]; // Command specific data
713 };
714
715 /*
716 * FIB commands
717 */
718
719 #define TestCommandResponse 1
720 #define TestAdapterCommand 2
721 /*
722 * Lowlevel and comm commands
723 */
724 #define LastTestCommand 100
725 #define ReinitHostNormCommandQueue 101
726 #define ReinitHostHighCommandQueue 102
727 #define ReinitHostHighRespQueue 103
728 #define ReinitHostNormRespQueue 104
729 #define ReinitAdapNormCommandQueue 105
730 #define ReinitAdapHighCommandQueue 107
731 #define ReinitAdapHighRespQueue 108
732 #define ReinitAdapNormRespQueue 109
733 #define InterfaceShutdown 110
734 #define DmaCommandFib 120
735 #define StartProfile 121
736 #define TermProfile 122
737 #define SpeedTest 123
738 #define TakeABreakPt 124
739 #define RequestPerfData 125
740 #define SetInterruptDefTimer 126
741 #define SetInterruptDefCount 127
742 #define GetInterruptDefStatus 128
743 #define LastCommCommand 129
744 /*
745 * Filesystem commands
746 */
747 #define NuFileSystem 300
748 #define UFS 301
749 #define HostFileSystem 302
750 #define LastFileSystemCommand 303
751 /*
752 * Container Commands
753 */
754 #define ContainerCommand 500
755 #define ContainerCommand64 501
756 #define ContainerRawIo 502
757 #define ContainerRawIo2 503
758 /*
759 * Scsi Port commands (scsi passthrough)
760 */
761 #define ScsiPortCommand 600
762 #define ScsiPortCommand64 601
763 /*
764 * Misc house keeping and generic adapter initiated commands
765 */
766 #define AifRequest 700
767 #define CheckRevision 701
768 #define FsaHostShutdown 702
769 #define RequestAdapterInfo 703
770 #define IsAdapterPaused 704
771 #define SendHostTime 705
772 #define RequestSupplementAdapterInfo 706
773 #define LastMiscCommand 707
774
775 /*
776 * Commands that will target the failover level on the FSA adapter
777 */
778
779 enum fib_xfer_state {
780 HostOwned = (1<<0),
781 AdapterOwned = (1<<1),
782 FibInitialized = (1<<2),
783 FibEmpty = (1<<3),
784 AllocatedFromPool = (1<<4),
785 SentFromHost = (1<<5),
786 SentFromAdapter = (1<<6),
787 ResponseExpected = (1<<7),
788 NoResponseExpected = (1<<8),
789 AdapterProcessed = (1<<9),
790 HostProcessed = (1<<10),
791 HighPriority = (1<<11),
792 NormalPriority = (1<<12),
793 Async = (1<<13),
794 AsyncIo = (1<<13), // rpbfix: remove with new regime
795 PageFileIo = (1<<14), // rpbfix: remove with new regime
796 ShutdownRequest = (1<<15),
797 LazyWrite = (1<<16), // rpbfix: remove with new regime
798 AdapterMicroFib = (1<<17),
799 BIOSFibPath = (1<<18),
800 FastResponseCapable = (1<<19),
801 ApiFib = (1<<20), /* Its an API Fib */
802 /* PMC NEW COMM: There is no more AIF data pending */
803 NoMoreAifDataAvailable = (1<<21)
804 };
805
806 /*
807 * The following defines needs to be updated any time there is an
808 * incompatible change made to the aac_init structure.
809 */
810
811 #define ADAPTER_INIT_STRUCT_REVISION 3
812 #define ADAPTER_INIT_STRUCT_REVISION_4 4 // rocket science
813 #define ADAPTER_INIT_STRUCT_REVISION_6 6 /* PMC src */
814 #define ADAPTER_INIT_STRUCT_REVISION_7 7 /* Denali */
815 #define ADAPTER_INIT_STRUCT_REVISION_8 8 // Thor
816
817 union aac_init
818 {
819 struct _r7 {
820 __le32 init_struct_revision;
821 __le32 no_of_msix_vectors;
822 __le32 fsrev;
823 __le32 comm_header_address;
824 __le32 fast_io_comm_area_address;
825 __le32 adapter_fibs_physical_address;
826 __le32 adapter_fibs_virtual_address;
827 __le32 adapter_fibs_size;
828 __le32 adapter_fib_align;
829 __le32 printfbuf;
830 __le32 printfbufsiz;
831 /* number of 4k pages of host phys. mem. */
832 __le32 host_phys_mem_pages;
833 /* number of seconds since 1970. */
834 __le32 host_elapsed_seconds;
835 /* ADAPTER_INIT_STRUCT_REVISION_4 begins here */
836 __le32 init_flags; /* flags for supported features */
837 #define INITFLAGS_NEW_COMM_SUPPORTED 0x00000001
838 #define INITFLAGS_DRIVER_USES_UTC_TIME 0x00000010
839 #define INITFLAGS_DRIVER_SUPPORTS_PM 0x00000020
840 #define INITFLAGS_NEW_COMM_TYPE1_SUPPORTED 0x00000040
841 #define INITFLAGS_FAST_JBOD_SUPPORTED 0x00000080
842 #define INITFLAGS_NEW_COMM_TYPE2_SUPPORTED 0x00000100
843 #define INITFLAGS_DRIVER_SUPPORTS_HBA_MODE 0x00000400
844 __le32 max_io_commands; /* max outstanding commands */
845 __le32 max_io_size; /* largest I/O command */
846 __le32 max_fib_size; /* largest FIB to adapter */
847 /* ADAPTER_INIT_STRUCT_REVISION_5 begins here */
848 __le32 max_num_aif; /* max number of aif */
849 /* ADAPTER_INIT_STRUCT_REVISION_6 begins here */
850 /* Host RRQ (response queue) for SRC */
851 __le32 host_rrq_addr_low;
852 __le32 host_rrq_addr_high;
853 } r7;
854 struct _r8 {
855 /* ADAPTER_INIT_STRUCT_REVISION_8 */
856 __le32 init_struct_revision;
857 __le32 rr_queue_count;
858 __le32 host_elapsed_seconds; /* number of secs since 1970. */
859 __le32 init_flags;
860 __le32 max_io_size; /* largest I/O command */
861 __le32 max_num_aif; /* max number of aif */
862 __le32 reserved1;
863 __le32 reserved2;
864 struct _rrq {
865 __le32 host_addr_low;
866 __le32 host_addr_high;
867 __le16 msix_id;
868 __le16 element_count;
869 __le16 comp_thresh;
870 __le16 unused;
871 } rrq[] __counted_by_le(rr_queue_count); /* up to 64 RRQ addresses */
872 } r8;
873 };
874
875 enum aac_log_level {
876 LOG_AAC_INIT = 10,
877 LOG_AAC_INFORMATIONAL = 20,
878 LOG_AAC_WARNING = 30,
879 LOG_AAC_LOW_ERROR = 40,
880 LOG_AAC_MEDIUM_ERROR = 50,
881 LOG_AAC_HIGH_ERROR = 60,
882 LOG_AAC_PANIC = 70,
883 LOG_AAC_DEBUG = 80,
884 LOG_AAC_WINDBG_PRINT = 90
885 };
886
887 #define FSAFS_NTC_GET_ADAPTER_FIB_CONTEXT 0x030b
888 #define FSAFS_NTC_FIB_CONTEXT 0x030c
889
890 struct aac_dev;
891 struct fib;
892 struct scsi_cmnd;
893
894 struct adapter_ops
895 {
896 /* Low level operations */
897 void (*adapter_interrupt)(struct aac_dev *dev);
898 void (*adapter_notify)(struct aac_dev *dev, u32 event);
899 void (*adapter_disable_int)(struct aac_dev *dev);
900 void (*adapter_enable_int)(struct aac_dev *dev);
901 int (*adapter_sync_cmd)(struct aac_dev *dev, u32 command, u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6, u32 *status, u32 *r1, u32 *r2, u32 *r3, u32 *r4);
902 int (*adapter_check_health)(struct aac_dev *dev);
903 int (*adapter_restart)(struct aac_dev *dev, int bled, u8 reset_type);
904 void (*adapter_start)(struct aac_dev *dev);
905 /* Transport operations */
906 int (*adapter_ioremap)(struct aac_dev * dev, u32 size);
907 irq_handler_t adapter_intr;
908 /* Packet operations */
909 int (*adapter_deliver)(struct fib * fib);
910 int (*adapter_bounds)(struct aac_dev * dev, struct scsi_cmnd * cmd, u64 lba);
911 int (*adapter_read)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count);
912 int (*adapter_write)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count, int fua);
913 int (*adapter_scsi)(struct fib * fib, struct scsi_cmnd * cmd);
914 /* Administrative operations */
915 int (*adapter_comm)(struct aac_dev * dev, int comm);
916 };
917
918 /*
919 * Define which interrupt handler needs to be installed
920 */
921
922 struct aac_driver_ident
923 {
924 int (*init)(struct aac_dev *dev);
925 char * name;
926 char * vname;
927 char * model;
928 u16 channels;
929 int quirks;
930 };
931 /*
932 * Some adapter firmware needs communication memory
933 * below 2gig. This tells the init function to set the
934 * dma mask such that fib memory will be allocated where the
935 * adapter firmware can get to it.
936 */
937 #define AAC_QUIRK_31BIT 0x0001
938
939 /*
940 * Some adapter firmware, when the raid card's cache is turned off, can not
941 * split up scatter gathers in order to deal with the limits of the
942 * underlying CHIM. This limit is 34 scatter gather elements.
943 */
944 #define AAC_QUIRK_34SG 0x0002
945
946 /*
947 * This adapter is a slave (no Firmware)
948 */
949 #define AAC_QUIRK_SLAVE 0x0004
950
951 /*
952 * This adapter is a master.
953 */
954 #define AAC_QUIRK_MASTER 0x0008
955
956 /*
957 * Some adapter firmware perform poorly when it must split up scatter gathers
958 * in order to deal with the limits of the underlying CHIM. This limit in this
959 * class of adapters is 17 scatter gather elements.
960 */
961 #define AAC_QUIRK_17SG 0x0010
962
963 /*
964 * Some adapter firmware does not support 64 bit scsi passthrough
965 * commands.
966 */
967 #define AAC_QUIRK_SCSI_32 0x0020
968
969 /*
970 * SRC based adapters support the AifReqEvent functions
971 */
972 #define AAC_QUIRK_SRC 0x0040
973
974 /*
975 * The adapter interface specs all queues to be located in the same
976 * physically contiguous block. The host structure that defines the
977 * commuication queues will assume they are each a separate physically
978 * contiguous memory region that will support them all being one big
979 * contiguous block.
980 * There is a command and response queue for each level and direction of
981 * commuication. These regions are accessed by both the host and adapter.
982 */
983
984 struct aac_queue {
985 u64 logical; /*address we give the adapter */
986 struct aac_entry *base; /*system virtual address */
987 struct aac_qhdr headers; /*producer,consumer q headers*/
988 u32 entries; /*Number of queue entries */
989 wait_queue_head_t qfull; /*Event to wait on if q full */
990 wait_queue_head_t cmdready; /*Cmd ready from the adapter */
991 /* This is only valid for adapter to host command queues. */
992 spinlock_t *lock; /* Spinlock for this queue must take this lock before accessing the lock */
993 spinlock_t lockdata; /* Actual lock (used only on one side of the lock) */
994 struct list_head cmdq; /* A queue of FIBs which need to be prcessed by the FS thread. This is */
995 /* only valid for command queues which receive entries from the adapter. */
996 /* Number of entries on outstanding queue. */
997 atomic_t numpending;
998 struct aac_dev * dev; /* Back pointer to adapter structure */
999 };
1000
1001 /*
1002 * Message queues. The order here is important, see also the
1003 * queue type ordering
1004 */
1005
1006 struct aac_queue_block
1007 {
1008 struct aac_queue queue[8];
1009 };
1010
1011 /*
1012 * SaP1 Message Unit Registers
1013 */
1014
1015 struct sa_drawbridge_CSR {
1016 /* Offset | Name */
1017 __le32 reserved[10]; /* 00h-27h | Reserved */
1018 u8 LUT_Offset; /* 28h | Lookup Table Offset */
1019 u8 reserved1[3]; /* 29h-2bh | Reserved */
1020 __le32 LUT_Data; /* 2ch | Looup Table Data */
1021 __le32 reserved2[26]; /* 30h-97h | Reserved */
1022 __le16 PRICLEARIRQ; /* 98h | Primary Clear Irq */
1023 __le16 SECCLEARIRQ; /* 9ah | Secondary Clear Irq */
1024 __le16 PRISETIRQ; /* 9ch | Primary Set Irq */
1025 __le16 SECSETIRQ; /* 9eh | Secondary Set Irq */
1026 __le16 PRICLEARIRQMASK;/* a0h | Primary Clear Irq Mask */
1027 __le16 SECCLEARIRQMASK;/* a2h | Secondary Clear Irq Mask */
1028 __le16 PRISETIRQMASK; /* a4h | Primary Set Irq Mask */
1029 __le16 SECSETIRQMASK; /* a6h | Secondary Set Irq Mask */
1030 __le32 MAILBOX0; /* a8h | Scratchpad 0 */
1031 __le32 MAILBOX1; /* ach | Scratchpad 1 */
1032 __le32 MAILBOX2; /* b0h | Scratchpad 2 */
1033 __le32 MAILBOX3; /* b4h | Scratchpad 3 */
1034 __le32 MAILBOX4; /* b8h | Scratchpad 4 */
1035 __le32 MAILBOX5; /* bch | Scratchpad 5 */
1036 __le32 MAILBOX6; /* c0h | Scratchpad 6 */
1037 __le32 MAILBOX7; /* c4h | Scratchpad 7 */
1038 __le32 ROM_Setup_Data; /* c8h | Rom Setup and Data */
1039 __le32 ROM_Control_Addr;/* cch | Rom Control and Address */
1040 __le32 reserved3[12]; /* d0h-ffh | reserved */
1041 __le32 LUT[64]; /* 100h-1ffh | Lookup Table Entries */
1042 };
1043
1044 #define Mailbox0 SaDbCSR.MAILBOX0
1045 #define Mailbox1 SaDbCSR.MAILBOX1
1046 #define Mailbox2 SaDbCSR.MAILBOX2
1047 #define Mailbox3 SaDbCSR.MAILBOX3
1048 #define Mailbox4 SaDbCSR.MAILBOX4
1049 #define Mailbox5 SaDbCSR.MAILBOX5
1050 #define Mailbox6 SaDbCSR.MAILBOX6
1051 #define Mailbox7 SaDbCSR.MAILBOX7
1052
1053 #define DoorbellReg_p SaDbCSR.PRISETIRQ
1054 #define DoorbellReg_s SaDbCSR.SECSETIRQ
1055 #define DoorbellClrReg_p SaDbCSR.PRICLEARIRQ
1056
1057
1058 #define DOORBELL_0 0x0001
1059 #define DOORBELL_1 0x0002
1060 #define DOORBELL_2 0x0004
1061 #define DOORBELL_3 0x0008
1062 #define DOORBELL_4 0x0010
1063 #define DOORBELL_5 0x0020
1064 #define DOORBELL_6 0x0040
1065
1066
1067 #define PrintfReady DOORBELL_5
1068 #define PrintfDone DOORBELL_5
1069
1070 struct sa_registers {
1071 struct sa_drawbridge_CSR SaDbCSR; /* 98h - c4h */
1072 };
1073
1074
1075 #define SA_INIT_NUM_MSIXVECTORS 1
1076 #define SA_MINIPORT_REVISION SA_INIT_NUM_MSIXVECTORS
1077
1078 #define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
1079 #define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
1080 #define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR))
1081 #define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR))
1082
1083 /*
1084 * Rx Message Unit Registers
1085 */
1086
1087 struct rx_mu_registers {
1088 /* Local | PCI*| Name */
1089 __le32 ARSR; /* 1300h | 00h | APIC Register Select Register */
1090 __le32 reserved0; /* 1304h | 04h | Reserved */
1091 __le32 AWR; /* 1308h | 08h | APIC Window Register */
1092 __le32 reserved1; /* 130Ch | 0Ch | Reserved */
1093 __le32 IMRx[2]; /* 1310h | 10h | Inbound Message Registers */
1094 __le32 OMRx[2]; /* 1318h | 18h | Outbound Message Registers */
1095 __le32 IDR; /* 1320h | 20h | Inbound Doorbell Register */
1096 __le32 IISR; /* 1324h | 24h | Inbound Interrupt
1097 Status Register */
1098 __le32 IIMR; /* 1328h | 28h | Inbound Interrupt
1099 Mask Register */
1100 __le32 ODR; /* 132Ch | 2Ch | Outbound Doorbell Register */
1101 __le32 OISR; /* 1330h | 30h | Outbound Interrupt
1102 Status Register */
1103 __le32 OIMR; /* 1334h | 34h | Outbound Interrupt
1104 Mask Register */
1105 __le32 reserved2; /* 1338h | 38h | Reserved */
1106 __le32 reserved3; /* 133Ch | 3Ch | Reserved */
1107 __le32 InboundQueue;/* 1340h | 40h | Inbound Queue Port relative to firmware */
1108 __le32 OutboundQueue;/*1344h | 44h | Outbound Queue Port relative to firmware */
1109 /* * Must access through ATU Inbound
1110 Translation Window */
1111 };
1112
1113 struct rx_inbound {
1114 __le32 Mailbox[8];
1115 };
1116
1117 #define INBOUNDDOORBELL_0 0x00000001
1118 #define INBOUNDDOORBELL_1 0x00000002
1119 #define INBOUNDDOORBELL_2 0x00000004
1120 #define INBOUNDDOORBELL_3 0x00000008
1121 #define INBOUNDDOORBELL_4 0x00000010
1122 #define INBOUNDDOORBELL_5 0x00000020
1123 #define INBOUNDDOORBELL_6 0x00000040
1124
1125 #define OUTBOUNDDOORBELL_0 0x00000001
1126 #define OUTBOUNDDOORBELL_1 0x00000002
1127 #define OUTBOUNDDOORBELL_2 0x00000004
1128 #define OUTBOUNDDOORBELL_3 0x00000008
1129 #define OUTBOUNDDOORBELL_4 0x00000010
1130
1131 #define InboundDoorbellReg MUnit.IDR
1132 #define OutboundDoorbellReg MUnit.ODR
1133
1134 struct rx_registers {
1135 struct rx_mu_registers MUnit; /* 1300h - 1347h */
1136 __le32 reserved1[2]; /* 1348h - 134ch */
1137 struct rx_inbound IndexRegs;
1138 };
1139
1140 #define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR))
1141 #define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR))
1142 #define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR))
1143 #define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR))
1144
1145 /*
1146 * Rkt Message Unit Registers (same as Rx, except a larger reserve region)
1147 */
1148
1149 #define rkt_mu_registers rx_mu_registers
1150 #define rkt_inbound rx_inbound
1151
1152 struct rkt_registers {
1153 struct rkt_mu_registers MUnit; /* 1300h - 1347h */
1154 __le32 reserved1[1006]; /* 1348h - 22fch */
1155 struct rkt_inbound IndexRegs; /* 2300h - */
1156 };
1157
1158 #define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR))
1159 #define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR))
1160 #define rkt_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rkt->CSR))
1161 #define rkt_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rkt->CSR))
1162
1163 /*
1164 * PMC SRC message unit registers
1165 */
1166
1167 #define src_inbound rx_inbound
1168
1169 struct src_mu_registers {
1170 /* PCI*| Name */
1171 __le32 reserved0[6]; /* 00h | Reserved */
1172 __le32 IOAR[2]; /* 18h | IOA->host interrupt register */
1173 __le32 IDR; /* 20h | Inbound Doorbell Register */
1174 __le32 IISR; /* 24h | Inbound Int. Status Register */
1175 __le32 reserved1[3]; /* 28h | Reserved */
1176 __le32 OIMR; /* 34h | Outbound Int. Mask Register */
1177 __le32 reserved2[25]; /* 38h | Reserved */
1178 __le32 ODR_R; /* 9ch | Outbound Doorbell Read */
1179 __le32 ODR_C; /* a0h | Outbound Doorbell Clear */
1180 __le32 reserved3[3]; /* a4h | Reserved */
1181 __le32 SCR0; /* b0h | Scratchpad 0 */
1182 __le32 reserved4[2]; /* b4h | Reserved */
1183 __le32 OMR; /* bch | Outbound Message Register */
1184 __le32 IQ_L; /* c0h | Inbound Queue (Low address) */
1185 __le32 IQ_H; /* c4h | Inbound Queue (High address) */
1186 __le32 ODR_MSI; /* c8h | MSI register for sync./AIF */
1187 __le32 reserved5; /* cch | Reserved */
1188 __le32 IQN_L; /* d0h | Inbound (native cmd) low */
1189 __le32 IQN_H; /* d4h | Inbound (native cmd) high */
1190 };
1191
1192 struct src_registers {
1193 struct src_mu_registers MUnit; /* 00h - cbh */
1194 union {
1195 struct {
1196 __le32 reserved1[130786]; /* d8h - 7fc5fh */
1197 struct src_inbound IndexRegs; /* 7fc60h */
1198 } tupelo;
1199 struct {
1200 __le32 reserved1[970]; /* d8h - fffh */
1201 struct src_inbound IndexRegs; /* 1000h */
1202 } denali;
1203 } u;
1204 };
1205
1206 #define src_readb(AEP, CSR) readb(&((AEP)->regs.src.bar0->CSR))
1207 #define src_readl(AEP, CSR) readl(&((AEP)->regs.src.bar0->CSR))
1208 #define src_writeb(AEP, CSR, value) writeb(value, \
1209 &((AEP)->regs.src.bar0->CSR))
1210 #define src_writel(AEP, CSR, value) writel(value, \
1211 &((AEP)->regs.src.bar0->CSR))
1212 #if defined(writeq)
1213 #define src_writeq(AEP, CSR, value) writeq(value, \
1214 &((AEP)->regs.src.bar0->CSR))
1215 #endif
1216
1217 #define SRC_ODR_SHIFT 12
1218 #define SRC_IDR_SHIFT 9
1219 #define SRC_MSI_READ_MASK 0x1000
1220
1221 typedef void (*fib_callback)(void *ctxt, struct fib *fibctx);
1222
1223 struct aac_fib_context {
1224 s16 type; // used for verification of structure
1225 s16 size;
1226 u32 unique; // unique value representing this context
1227 ulong jiffies; // used for cleanup - dmb changed to ulong
1228 struct list_head next; // used to link context's into a linked list
1229 struct completion completion; // this is used to wait for the next fib to arrive.
1230 int wait; // Set to true when thread is in WaitForSingleObject
1231 unsigned long count; // total number of FIBs on FibList
1232 struct list_head fib_list; // this holds fibs and their attachd hw_fibs
1233 };
1234
1235 struct sense_data {
1236 u8 error_code; /* 70h (current errors), 71h(deferred errors) */
1237 u8 valid:1; /* A valid bit of one indicates that the information */
1238 /* field contains valid information as defined in the
1239 * SCSI-2 Standard.
1240 */
1241 u8 segment_number; /* Only used for COPY, COMPARE, or COPY AND VERIFY Commands */
1242 u8 sense_key:4; /* Sense Key */
1243 u8 reserved:1;
1244 u8 ILI:1; /* Incorrect Length Indicator */
1245 u8 EOM:1; /* End Of Medium - reserved for random access devices */
1246 u8 filemark:1; /* Filemark - reserved for random access devices */
1247
1248 u8 information[4]; /* for direct-access devices, contains the unsigned
1249 * logical block address or residue associated with
1250 * the sense key
1251 */
1252 u8 add_sense_len; /* number of additional sense bytes to follow this field */
1253 u8 cmnd_info[4]; /* not used */
1254 u8 ASC; /* Additional Sense Code */
1255 u8 ASCQ; /* Additional Sense Code Qualifier */
1256 u8 FRUC; /* Field Replaceable Unit Code - not used */
1257 u8 bit_ptr:3; /* indicates which byte of the CDB or parameter data
1258 * was in error
1259 */
1260 u8 BPV:1; /* bit pointer valid (BPV): 1- indicates that
1261 * the bit_ptr field has valid value
1262 */
1263 u8 reserved2:2;
1264 u8 CD:1; /* command data bit: 1- illegal parameter in CDB.
1265 * 0- illegal parameter in data.
1266 */
1267 u8 SKSV:1;
1268 u8 field_ptr[2]; /* byte of the CDB or parameter data in error */
1269 };
1270
1271 struct fsa_dev_info {
1272 u64 last;
1273 u64 size;
1274 u32 type;
1275 u32 config_waiting_on;
1276 unsigned long config_waiting_stamp;
1277 u16 queue_depth;
1278 u8 config_needed;
1279 u8 valid;
1280 u8 ro;
1281 u8 locked;
1282 u8 deleted;
1283 char devname[8];
1284 struct sense_data sense_data;
1285 u32 block_size;
1286 u8 identifier[16];
1287 };
1288
1289 struct fib {
1290 void *next; /* this is used by the allocator */
1291 s16 type;
1292 s16 size;
1293 /*
1294 * The Adapter that this I/O is destined for.
1295 */
1296 struct aac_dev *dev;
1297 /*
1298 * This is the event the sendfib routine will wait on if the
1299 * caller did not pass one and this is synch io.
1300 */
1301 struct completion event_wait;
1302 spinlock_t event_lock;
1303
1304 u32 done; /* gets set to 1 when fib is complete */
1305 fib_callback callback;
1306 void *callback_data;
1307 u32 flags; // u32 dmb was ulong
1308 /*
1309 * And for the internal issue/reply queues (we may be able
1310 * to merge these two)
1311 */
1312 struct list_head fiblink;
1313 void *data;
1314 u32 vector_no;
1315 struct hw_fib *hw_fib_va; /* also used for native */
1316 dma_addr_t hw_fib_pa; /* physical address of hw_fib*/
1317 dma_addr_t hw_sgl_pa; /* extra sgl for native */
1318 dma_addr_t hw_error_pa; /* error buffer for native */
1319 u32 hbacmd_size; /* cmd size for native */
1320 };
1321
1322 #define AAC_INIT 0
1323 #define AAC_RESCAN 1
1324
1325 #define AAC_DEVTYPE_RAID_MEMBER 1
1326 #define AAC_DEVTYPE_ARC_RAW 2
1327 #define AAC_DEVTYPE_NATIVE_RAW 3
1328
1329 #define AAC_RESCAN_DELAY (10 * HZ)
1330
1331 struct aac_hba_map_info {
1332 __le32 rmw_nexus; /* nexus for native HBA devices */
1333 u8 devtype; /* device type */
1334 s8 reset_state; /* 0 - no reset, 1..x - */
1335 /* after xth TM LUN reset */
1336 u16 qd_limit;
1337 u32 scan_counter;
1338 struct aac_ciss_identify_pd *safw_identify_resp;
1339 };
1340
1341 /*
1342 * Adapter Information Block
1343 *
1344 * This is returned by the RequestAdapterInfo block
1345 */
1346
1347 struct aac_adapter_info
1348 {
1349 __le32 platform;
1350 __le32 cpu;
1351 __le32 subcpu;
1352 __le32 clock;
1353 __le32 execmem;
1354 __le32 buffermem;
1355 __le32 totalmem;
1356 __le32 kernelrev;
1357 __le32 kernelbuild;
1358 __le32 monitorrev;
1359 __le32 monitorbuild;
1360 __le32 hwrev;
1361 __le32 hwbuild;
1362 __le32 biosrev;
1363 __le32 biosbuild;
1364 __le32 cluster;
1365 __le32 clusterchannelmask;
1366 __le32 serial[2];
1367 __le32 battery;
1368 __le32 options;
1369 __le32 OEM;
1370 };
1371
1372 struct aac_supplement_adapter_info
1373 {
1374 u8 adapter_type_text[17+1];
1375 u8 pad[2];
1376 __le32 flash_memory_byte_size;
1377 __le32 flash_image_id;
1378 __le32 max_number_ports;
1379 __le32 version;
1380 __le32 feature_bits;
1381 u8 slot_number;
1382 u8 reserved_pad0[3];
1383 u8 build_date[12];
1384 __le32 current_number_ports;
1385 struct {
1386 u8 assembly_pn[8];
1387 u8 fru_pn[8];
1388 u8 battery_fru_pn[8];
1389 u8 ec_version_string[8];
1390 u8 tsid[12];
1391 } vpd_info;
1392 __le32 flash_firmware_revision;
1393 __le32 flash_firmware_build;
1394 __le32 raid_type_morph_options;
1395 __le32 flash_firmware_boot_revision;
1396 __le32 flash_firmware_boot_build;
1397 u8 mfg_pcba_serial_no[12];
1398 u8 mfg_wwn_name[8];
1399 __le32 supported_options2;
1400 __le32 struct_expansion;
1401 /* StructExpansion == 1 */
1402 __le32 feature_bits3;
1403 __le32 supported_performance_modes;
1404 u8 host_bus_type; /* uses HOST_BUS_TYPE_xxx defines */
1405 u8 host_bus_width; /* actual width in bits or links */
1406 u16 host_bus_speed; /* actual bus speed/link rate in MHz */
1407 u8 max_rrc_drives; /* max. number of ITP-RRC drives/pool */
1408 u8 max_disk_xtasks; /* max. possible num of DiskX Tasks */
1409
1410 u8 cpld_ver_loaded;
1411 u8 cpld_ver_in_flash;
1412
1413 __le64 max_rrc_capacity;
1414 __le32 compiled_max_hist_log_level;
1415 u8 custom_board_name[12];
1416 u16 supported_cntlr_mode; /* identify supported controller mode */
1417 u16 reserved_for_future16;
1418 __le32 supported_options3; /* reserved for future options */
1419
1420 __le16 virt_device_bus; /* virt. SCSI device for Thor */
1421 __le16 virt_device_target;
1422 __le16 virt_device_lun;
1423 __le16 unused;
1424 __le32 reserved_for_future_growth[68];
1425
1426 };
1427 #define AAC_FEATURE_FALCON cpu_to_le32(0x00000010)
1428 #define AAC_FEATURE_JBOD cpu_to_le32(0x08000000)
1429 /* SupportedOptions2 */
1430 #define AAC_OPTION_MU_RESET cpu_to_le32(0x00000001)
1431 #define AAC_OPTION_IGNORE_RESET cpu_to_le32(0x00000002)
1432 #define AAC_OPTION_POWER_MANAGEMENT cpu_to_le32(0x00000004)
1433 #define AAC_OPTION_DOORBELL_RESET cpu_to_le32(0x00004000)
1434 /* 4KB sector size */
1435 #define AAC_OPTION_VARIABLE_BLOCK_SIZE cpu_to_le32(0x00040000)
1436 /* 240 simple volume support */
1437 #define AAC_OPTION_SUPPORTED_240_VOLUMES cpu_to_le32(0x10000000)
1438 /*
1439 * Supports FIB dump sync command send prior to IOP_RESET
1440 */
1441 #define AAC_OPTION_SUPPORTED3_IOP_RESET_FIB_DUMP cpu_to_le32(0x00004000)
1442 #define AAC_SIS_VERSION_V3 3
1443 #define AAC_SIS_SLOT_UNKNOWN 0xFF
1444
1445 #define GetBusInfo 0x00000009
1446 struct aac_bus_info {
1447 __le32 Command; /* VM_Ioctl */
1448 __le32 ObjType; /* FT_DRIVE */
1449 __le32 MethodId; /* 1 = SCSI Layer */
1450 __le32 ObjectId; /* Handle */
1451 __le32 CtlCmd; /* GetBusInfo */
1452 };
1453
1454 struct aac_bus_info_response {
1455 __le32 Status; /* ST_OK */
1456 __le32 ObjType;
1457 __le32 MethodId; /* unused */
1458 __le32 ObjectId; /* unused */
1459 __le32 CtlCmd; /* unused */
1460 __le32 ProbeComplete;
1461 __le32 BusCount;
1462 __le32 TargetsPerBus;
1463 u8 InitiatorBusId[10];
1464 u8 BusValid[10];
1465 };
1466
1467 /*
1468 * Battery platforms
1469 */
1470 #define AAC_BAT_REQ_PRESENT (1)
1471 #define AAC_BAT_REQ_NOTPRESENT (2)
1472 #define AAC_BAT_OPT_PRESENT (3)
1473 #define AAC_BAT_OPT_NOTPRESENT (4)
1474 #define AAC_BAT_NOT_SUPPORTED (5)
1475 /*
1476 * cpu types
1477 */
1478 #define AAC_CPU_SIMULATOR (1)
1479 #define AAC_CPU_I960 (2)
1480 #define AAC_CPU_STRONGARM (3)
1481
1482 /*
1483 * Supported Options
1484 */
1485 #define AAC_OPT_SNAPSHOT cpu_to_le32(1)
1486 #define AAC_OPT_CLUSTERS cpu_to_le32(1<<1)
1487 #define AAC_OPT_WRITE_CACHE cpu_to_le32(1<<2)
1488 #define AAC_OPT_64BIT_DATA cpu_to_le32(1<<3)
1489 #define AAC_OPT_HOST_TIME_FIB cpu_to_le32(1<<4)
1490 #define AAC_OPT_RAID50 cpu_to_le32(1<<5)
1491 #define AAC_OPT_4GB_WINDOW cpu_to_le32(1<<6)
1492 #define AAC_OPT_SCSI_UPGRADEABLE cpu_to_le32(1<<7)
1493 #define AAC_OPT_SOFT_ERR_REPORT cpu_to_le32(1<<8)
1494 #define AAC_OPT_SUPPORTED_RECONDITION cpu_to_le32(1<<9)
1495 #define AAC_OPT_SGMAP_HOST64 cpu_to_le32(1<<10)
1496 #define AAC_OPT_ALARM cpu_to_le32(1<<11)
1497 #define AAC_OPT_NONDASD cpu_to_le32(1<<12)
1498 #define AAC_OPT_SCSI_MANAGED cpu_to_le32(1<<13)
1499 #define AAC_OPT_RAID_SCSI_MODE cpu_to_le32(1<<14)
1500 #define AAC_OPT_SUPPLEMENT_ADAPTER_INFO cpu_to_le32(1<<16)
1501 #define AAC_OPT_NEW_COMM cpu_to_le32(1<<17)
1502 #define AAC_OPT_NEW_COMM_64 cpu_to_le32(1<<18)
1503 #define AAC_OPT_EXTENDED cpu_to_le32(1<<23)
1504 #define AAC_OPT_NATIVE_HBA cpu_to_le32(1<<25)
1505 #define AAC_OPT_NEW_COMM_TYPE1 cpu_to_le32(1<<28)
1506 #define AAC_OPT_NEW_COMM_TYPE2 cpu_to_le32(1<<29)
1507 #define AAC_OPT_NEW_COMM_TYPE3 cpu_to_le32(1<<30)
1508 #define AAC_OPT_NEW_COMM_TYPE4 cpu_to_le32(1<<31)
1509
1510 #define AAC_COMM_PRODUCER 0
1511 #define AAC_COMM_MESSAGE 1
1512 #define AAC_COMM_MESSAGE_TYPE1 3
1513 #define AAC_COMM_MESSAGE_TYPE2 4
1514 #define AAC_COMM_MESSAGE_TYPE3 5
1515
1516 #define AAC_EXTOPT_SA_FIRMWARE cpu_to_le32(1<<1)
1517 #define AAC_EXTOPT_SOFT_RESET cpu_to_le32(1<<16)
1518
1519 /* MSIX context */
1520 struct aac_msix_ctx {
1521 int vector_no;
1522 struct aac_dev *dev;
1523 };
1524
1525 struct aac_dev
1526 {
1527 struct list_head entry;
1528 const char *name;
1529 int id;
1530
1531 /*
1532 * negotiated FIB settings
1533 */
1534 unsigned int max_fib_size;
1535 unsigned int sg_tablesize;
1536 unsigned int max_num_aif;
1537
1538 unsigned int max_cmd_size; /* max_fib_size or MAX_NATIVE */
1539
1540 /*
1541 * Map for 128 fib objects (64k)
1542 */
1543 dma_addr_t hw_fib_pa; /* also used for native cmd */
1544 struct hw_fib *hw_fib_va; /* also used for native cmd */
1545 struct hw_fib *aif_base_va;
1546 /*
1547 * Fib Headers
1548 */
1549 struct fib *fibs;
1550
1551 struct fib *free_fib;
1552 spinlock_t fib_lock;
1553
1554 struct mutex ioctl_mutex;
1555 struct mutex scan_mutex;
1556 struct aac_queue_block *queues;
1557 /*
1558 * The user API will use an IOCTL to register itself to receive
1559 * FIBs from the adapter. The following list is used to keep
1560 * track of all the threads that have requested these FIBs. The
1561 * mutex is used to synchronize access to all data associated
1562 * with the adapter fibs.
1563 */
1564 struct list_head fib_list;
1565
1566 struct adapter_ops a_ops;
1567 unsigned long fsrev; /* Main driver's revision number */
1568
1569 resource_size_t base_start; /* main IO base */
1570 resource_size_t dbg_base; /* address of UART
1571 * debug buffer */
1572
1573 resource_size_t base_size, dbg_size; /* Size of
1574 * mapped in region */
1575 /*
1576 * Holds initialization info
1577 * to communicate with adapter
1578 */
1579 union aac_init *init;
1580 dma_addr_t init_pa; /* Holds physical address of the init struct */
1581 /* response queue (if AAC_COMM_MESSAGE_TYPE1) */
1582 __le32 *host_rrq;
1583 dma_addr_t host_rrq_pa; /* phys. address */
1584 /* index into rrq buffer */
1585 u32 host_rrq_idx[AAC_MAX_MSIX];
1586 atomic_t rrq_outstanding[AAC_MAX_MSIX];
1587 u32 fibs_pushed_no;
1588 struct pci_dev *pdev; /* Our PCI interface */
1589 /* pointer to buffer used for printf's from the adapter */
1590 void *printfbuf;
1591 void *comm_addr; /* Base address of Comm area */
1592 dma_addr_t comm_phys; /* Physical Address of Comm area */
1593 size_t comm_size;
1594
1595 struct Scsi_Host *scsi_host_ptr;
1596 int maximum_num_containers;
1597 int maximum_num_physicals;
1598 int maximum_num_channels;
1599 struct fsa_dev_info *fsa_dev;
1600 struct task_struct *thread;
1601 struct delayed_work safw_rescan_work;
1602 struct delayed_work src_reinit_aif_worker;
1603 int cardtype;
1604 /*
1605 *This lock will protect the two 32-bit
1606 *writes to the Inbound Queue
1607 */
1608 spinlock_t iq_lock;
1609
1610 /*
1611 * The following is the device specific extension.
1612 */
1613 #ifndef AAC_MIN_FOOTPRINT_SIZE
1614 # define AAC_MIN_FOOTPRINT_SIZE 8192
1615 # define AAC_MIN_SRC_BAR0_SIZE 0x400000
1616 # define AAC_MIN_SRC_BAR1_SIZE 0x800
1617 # define AAC_MIN_SRCV_BAR0_SIZE 0x100000
1618 # define AAC_MIN_SRCV_BAR1_SIZE 0x400
1619 #endif
1620 union
1621 {
1622 struct sa_registers __iomem *sa;
1623 struct rx_registers __iomem *rx;
1624 struct rkt_registers __iomem *rkt;
1625 struct {
1626 struct src_registers __iomem *bar0;
1627 char __iomem *bar1;
1628 } src;
1629 } regs;
1630 volatile void __iomem *base, *dbg_base_mapped;
1631 volatile struct rx_inbound __iomem *IndexRegs;
1632 u32 OIMR; /* Mask Register Cache */
1633 /*
1634 * AIF thread states
1635 */
1636 u32 aif_thread;
1637 struct aac_adapter_info adapter_info;
1638 struct aac_supplement_adapter_info supplement_adapter_info;
1639 /* These are in adapter info but they are in the io flow so
1640 * lets break them out so we don't have to do an AND to check them
1641 */
1642 u8 nondasd_support;
1643 u8 jbod;
1644 u8 cache_protected;
1645 u8 dac_support;
1646 u8 needs_dac;
1647 u8 raid_scsi_mode;
1648 u8 comm_interface;
1649 u8 raw_io_interface;
1650 u8 raw_io_64;
1651 u8 printf_enabled;
1652 u8 in_reset;
1653 u8 in_soft_reset;
1654 u8 msi;
1655 u8 sa_firmware;
1656 int management_fib_count;
1657 spinlock_t manage_lock;
1658 spinlock_t sync_lock;
1659 int sync_mode;
1660 struct fib *sync_fib;
1661 struct list_head sync_fib_list;
1662 u32 doorbell_mask;
1663 u32 max_msix; /* max. MSI-X vectors */
1664 u32 vector_cap; /* MSI-X vector capab.*/
1665 int msi_enabled; /* MSI/MSI-X enabled */
1666 atomic_t msix_counter;
1667 u32 scan_counter;
1668 struct msix_entry msixentry[AAC_MAX_MSIX];
1669 struct aac_msix_ctx aac_msix[AAC_MAX_MSIX]; /* context */
1670 struct aac_hba_map_info hba_map[AAC_MAX_BUSES][AAC_MAX_TARGETS];
1671 struct aac_ciss_phys_luns_resp *safw_phys_luns;
1672 u8 adapter_shutdown;
1673 u32 handle_pci_error;
1674 bool init_reset;
1675 u8 soft_reset_support;
1676 };
1677
1678 #define aac_adapter_interrupt(dev) \
1679 (dev)->a_ops.adapter_interrupt(dev)
1680
1681 #define aac_adapter_notify(dev, event) \
1682 (dev)->a_ops.adapter_notify(dev, event)
1683
1684 #define aac_adapter_disable_int(dev) \
1685 (dev)->a_ops.adapter_disable_int(dev)
1686
1687 #define aac_adapter_enable_int(dev) \
1688 (dev)->a_ops.adapter_enable_int(dev)
1689
1690 #define aac_adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4) \
1691 (dev)->a_ops.adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4)
1692
1693 #define aac_adapter_restart(dev, bled, reset_type) \
1694 ((dev)->a_ops.adapter_restart(dev, bled, reset_type))
1695
1696 #define aac_adapter_start(dev) \
1697 ((dev)->a_ops.adapter_start(dev))
1698
1699 #define aac_adapter_ioremap(dev, size) \
1700 (dev)->a_ops.adapter_ioremap(dev, size)
1701
1702 #define aac_adapter_deliver(fib) \
1703 ((fib)->dev)->a_ops.adapter_deliver(fib)
1704
1705 #define aac_adapter_bounds(dev,cmd,lba) \
1706 dev->a_ops.adapter_bounds(dev,cmd,lba)
1707
1708 #define aac_adapter_read(fib,cmd,lba,count) \
1709 ((fib)->dev)->a_ops.adapter_read(fib,cmd,lba,count)
1710
1711 #define aac_adapter_write(fib,cmd,lba,count,fua) \
1712 ((fib)->dev)->a_ops.adapter_write(fib,cmd,lba,count,fua)
1713
1714 #define aac_adapter_scsi(fib,cmd) \
1715 ((fib)->dev)->a_ops.adapter_scsi(fib,cmd)
1716
1717 #define aac_adapter_comm(dev,comm) \
1718 (dev)->a_ops.adapter_comm(dev, comm)
1719
1720 #define FIB_CONTEXT_FLAG_TIMED_OUT (0x00000001)
1721 #define FIB_CONTEXT_FLAG (0x00000002)
1722 #define FIB_CONTEXT_FLAG_WAIT (0x00000004)
1723 #define FIB_CONTEXT_FLAG_FASTRESP (0x00000008)
1724 #define FIB_CONTEXT_FLAG_NATIVE_HBA (0x00000010)
1725 #define FIB_CONTEXT_FLAG_NATIVE_HBA_TMF (0x00000020)
1726 #define FIB_CONTEXT_FLAG_SCSI_CMD (0x00000040)
1727 #define FIB_CONTEXT_FLAG_EH_RESET (0x00000080)
1728
1729 /*
1730 * Define the command values
1731 */
1732
1733 #define Null 0
1734 #define GetAttributes 1
1735 #define SetAttributes 2
1736 #define Lookup 3
1737 #define ReadLink 4
1738 #define Read 5
1739 #define Write 6
1740 #define Create 7
1741 #define MakeDirectory 8
1742 #define SymbolicLink 9
1743 #define MakeNode 10
1744 #define Removex 11
1745 #define RemoveDirectoryx 12
1746 #define Rename 13
1747 #define Link 14
1748 #define ReadDirectory 15
1749 #define ReadDirectoryPlus 16
1750 #define FileSystemStatus 17
1751 #define FileSystemInfo 18
1752 #define PathConfigure 19
1753 #define Commit 20
1754 #define Mount 21
1755 #define UnMount 22
1756 #define Newfs 23
1757 #define FsCheck 24
1758 #define FsSync 25
1759 #define SimReadWrite 26
1760 #define SetFileSystemStatus 27
1761 #define BlockRead 28
1762 #define BlockWrite 29
1763 #define NvramIoctl 30
1764 #define FsSyncWait 31
1765 #define ClearArchiveBit 32
1766 #define SetAcl 33
1767 #define GetAcl 34
1768 #define AssignAcl 35
1769 #define FaultInsertion 36 /* Fault Insertion Command */
1770 #define CrazyCache 37 /* Crazycache */
1771
1772 #define MAX_FSACOMMAND_NUM 38
1773
1774
1775 /*
1776 * Define the status returns. These are very unixlike although
1777 * most are not in fact used
1778 */
1779
1780 #define ST_OK 0
1781 #define ST_PERM 1
1782 #define ST_NOENT 2
1783 #define ST_IO 5
1784 #define ST_NXIO 6
1785 #define ST_E2BIG 7
1786 #define ST_MEDERR 8
1787 #define ST_ACCES 13
1788 #define ST_EXIST 17
1789 #define ST_XDEV 18
1790 #define ST_NODEV 19
1791 #define ST_NOTDIR 20
1792 #define ST_ISDIR 21
1793 #define ST_INVAL 22
1794 #define ST_FBIG 27
1795 #define ST_NOSPC 28
1796 #define ST_ROFS 30
1797 #define ST_MLINK 31
1798 #define ST_WOULDBLOCK 35
1799 #define ST_NAMETOOLONG 63
1800 #define ST_NOTEMPTY 66
1801 #define ST_DQUOT 69
1802 #define ST_STALE 70
1803 #define ST_REMOTE 71
1804 #define ST_NOT_READY 72
1805 #define ST_BADHANDLE 10001
1806 #define ST_NOT_SYNC 10002
1807 #define ST_BAD_COOKIE 10003
1808 #define ST_NOTSUPP 10004
1809 #define ST_TOOSMALL 10005
1810 #define ST_SERVERFAULT 10006
1811 #define ST_BADTYPE 10007
1812 #define ST_JUKEBOX 10008
1813 #define ST_NOTMOUNTED 10009
1814 #define ST_MAINTMODE 10010
1815 #define ST_STALEACL 10011
1816
1817 /*
1818 * On writes how does the client want the data written.
1819 */
1820
1821 #define CACHE_CSTABLE 1
1822 #define CACHE_UNSTABLE 2
1823
1824 /*
1825 * Lets the client know at which level the data was committed on
1826 * a write request
1827 */
1828
1829 #define CMFILE_SYNCH_NVRAM 1
1830 #define CMDATA_SYNCH_NVRAM 2
1831 #define CMFILE_SYNCH 3
1832 #define CMDATA_SYNCH 4
1833 #define CMUNSTABLE 5
1834
1835 #define RIO_TYPE_WRITE 0x0000
1836 #define RIO_TYPE_READ 0x0001
1837 #define RIO_SUREWRITE 0x0008
1838
1839 #define RIO2_IO_TYPE 0x0003
1840 #define RIO2_IO_TYPE_WRITE 0x0000
1841 #define RIO2_IO_TYPE_READ 0x0001
1842 #define RIO2_IO_TYPE_VERIFY 0x0002
1843 #define RIO2_IO_ERROR 0x0004
1844 #define RIO2_IO_SUREWRITE 0x0008
1845 #define RIO2_SGL_CONFORMANT 0x0010
1846 #define RIO2_SG_FORMAT 0xF000
1847 #define RIO2_SG_FORMAT_ARC 0x0000
1848 #define RIO2_SG_FORMAT_SRL 0x1000
1849 #define RIO2_SG_FORMAT_IEEE1212 0x2000
1850
1851 struct aac_read
1852 {
1853 __le32 command;
1854 __le32 cid;
1855 __le32 block;
1856 __le32 count;
1857 struct sgmap sg; // Must be last in struct because it is variable
1858 };
1859
1860 struct aac_read64
1861 {
1862 __le32 command;
1863 __le16 cid;
1864 __le16 sector_count;
1865 __le32 block;
1866 __le16 pad;
1867 __le16 flags;
1868 struct sgmap64 sg; // Must be last in struct because it is variable
1869 };
1870
1871 struct aac_read_reply
1872 {
1873 __le32 status;
1874 __le32 count;
1875 };
1876
1877 struct aac_write
1878 {
1879 __le32 command;
1880 __le32 cid;
1881 __le32 block;
1882 __le32 count;
1883 __le32 stable; // Not used
1884 struct sgmap sg; // Must be last in struct because it is variable
1885 };
1886
1887 struct aac_write64
1888 {
1889 __le32 command;
1890 __le16 cid;
1891 __le16 sector_count;
1892 __le32 block;
1893 __le16 pad;
1894 __le16 flags;
1895 struct sgmap64 sg; // Must be last in struct because it is variable
1896 };
1897 struct aac_write_reply
1898 {
1899 __le32 status;
1900 __le32 count;
1901 __le32 committed;
1902 };
1903
1904 struct aac_raw_io
1905 {
1906 __le32 block[2];
1907 __le32 count;
1908 __le16 cid;
1909 __le16 flags; /* 00 W, 01 R */
1910 __le16 bpTotal; /* reserved for F/W use */
1911 __le16 bpComplete; /* reserved for F/W use */
1912 struct sgmapraw sg;
1913 };
1914
1915 struct aac_raw_io2 {
1916 __le32 blockLow;
1917 __le32 blockHigh;
1918 __le32 byteCount;
1919 __le16 cid;
1920 __le16 flags; /* RIO2 flags */
1921 __le32 sgeFirstSize; /* size of first sge el. */
1922 __le32 sgeNominalSize; /* size of 2nd sge el. (if conformant) */
1923 u8 sgeCnt; /* only 8 bits required */
1924 u8 bpTotal; /* reserved for F/W use */
1925 u8 bpComplete; /* reserved for F/W use */
1926 u8 sgeFirstIndex; /* reserved for F/W use */
1927 u8 unused[4];
1928 struct sge_ieee1212 sge[];
1929 };
1930
1931 #define CT_FLUSH_CACHE 129
1932 struct aac_synchronize {
1933 __le32 command; /* VM_ContainerConfig */
1934 __le32 type; /* CT_FLUSH_CACHE */
1935 __le32 cid;
1936 __le32 parm1;
1937 __le32 parm2;
1938 __le32 parm3;
1939 __le32 parm4;
1940 __le32 count; /* sizeof(((struct aac_synchronize_reply *)NULL)->data) */
1941 };
1942
1943 struct aac_synchronize_reply {
1944 __le32 dummy0;
1945 __le32 dummy1;
1946 __le32 status; /* CT_OK */
1947 __le32 parm1;
1948 __le32 parm2;
1949 __le32 parm3;
1950 __le32 parm4;
1951 __le32 parm5;
1952 u8 data[16];
1953 };
1954
1955 #define CT_POWER_MANAGEMENT 245
1956 #define CT_PM_START_UNIT 2
1957 #define CT_PM_STOP_UNIT 3
1958 #define CT_PM_UNIT_IMMEDIATE 1
1959 struct aac_power_management {
1960 __le32 command; /* VM_ContainerConfig */
1961 __le32 type; /* CT_POWER_MANAGEMENT */
1962 __le32 sub; /* CT_PM_* */
1963 __le32 cid;
1964 __le32 parm; /* CT_PM_sub_* */
1965 };
1966
1967 #define CT_PAUSE_IO 65
1968 #define CT_RELEASE_IO 66
1969 struct aac_pause {
1970 __le32 command; /* VM_ContainerConfig */
1971 __le32 type; /* CT_PAUSE_IO */
1972 __le32 timeout; /* 10ms ticks */
1973 __le32 min;
1974 __le32 noRescan;
1975 __le32 parm3;
1976 __le32 parm4;
1977 __le32 count; /* sizeof(((struct aac_pause_reply *)NULL)->data) */
1978 };
1979
1980 struct aac_srb
1981 {
1982 __le32 function;
1983 __le32 channel;
1984 __le32 id;
1985 __le32 lun;
1986 __le32 timeout;
1987 __le32 flags;
1988 __le32 count; // Data xfer size
1989 __le32 retry_limit;
1990 __le32 cdb_size;
1991 u8 cdb[16];
1992 struct sgmap sg;
1993 };
1994
1995 /*
1996 * This and associated data structs are used by the
1997 * ioctl caller and are in cpu order.
1998 */
1999 struct user_aac_srb
2000 {
2001 u32 function;
2002 u32 channel;
2003 u32 id;
2004 u32 lun;
2005 u32 timeout;
2006 u32 flags;
2007 u32 count; // Data xfer size
2008 u32 retry_limit;
2009 u32 cdb_size;
2010 u8 cdb[16];
2011 struct user_sgmap sg;
2012 };
2013
2014 #define AAC_SENSE_BUFFERSIZE 30
2015
2016 struct aac_srb_reply
2017 {
2018 __le32 status;
2019 __le32 srb_status;
2020 __le32 scsi_status;
2021 __le32 data_xfer_length;
2022 __le32 sense_data_size;
2023 u8 sense_data[AAC_SENSE_BUFFERSIZE]; // Can this be SCSI_SENSE_BUFFERSIZE
2024 };
2025
2026 struct aac_srb_unit {
2027 struct aac_srb_reply srb_reply;
2028 struct aac_srb srb;
2029 };
2030
2031 /*
2032 * SRB Flags
2033 */
2034 #define SRB_NoDataXfer 0x0000
2035 #define SRB_DisableDisconnect 0x0004
2036 #define SRB_DisableSynchTransfer 0x0008
2037 #define SRB_BypassFrozenQueue 0x0010
2038 #define SRB_DisableAutosense 0x0020
2039 #define SRB_DataIn 0x0040
2040 #define SRB_DataOut 0x0080
2041
2042 /*
2043 * SRB Functions - set in aac_srb->function
2044 */
2045 #define SRBF_ExecuteScsi 0x0000
2046 #define SRBF_ClaimDevice 0x0001
2047 #define SRBF_IO_Control 0x0002
2048 #define SRBF_ReceiveEvent 0x0003
2049 #define SRBF_ReleaseQueue 0x0004
2050 #define SRBF_AttachDevice 0x0005
2051 #define SRBF_ReleaseDevice 0x0006
2052 #define SRBF_Shutdown 0x0007
2053 #define SRBF_Flush 0x0008
2054 #define SRBF_AbortCommand 0x0010
2055 #define SRBF_ReleaseRecovery 0x0011
2056 #define SRBF_ResetBus 0x0012
2057 #define SRBF_ResetDevice 0x0013
2058 #define SRBF_TerminateIO 0x0014
2059 #define SRBF_FlushQueue 0x0015
2060 #define SRBF_RemoveDevice 0x0016
2061 #define SRBF_DomainValidation 0x0017
2062
2063 /*
2064 * SRB SCSI Status - set in aac_srb->scsi_status
2065 */
2066 #define SRB_STATUS_PENDING 0x00
2067 #define SRB_STATUS_SUCCESS 0x01
2068 #define SRB_STATUS_ABORTED 0x02
2069 #define SRB_STATUS_ABORT_FAILED 0x03
2070 #define SRB_STATUS_ERROR 0x04
2071 #define SRB_STATUS_BUSY 0x05
2072 #define SRB_STATUS_INVALID_REQUEST 0x06
2073 #define SRB_STATUS_INVALID_PATH_ID 0x07
2074 #define SRB_STATUS_NO_DEVICE 0x08
2075 #define SRB_STATUS_TIMEOUT 0x09
2076 #define SRB_STATUS_SELECTION_TIMEOUT 0x0A
2077 #define SRB_STATUS_COMMAND_TIMEOUT 0x0B
2078 #define SRB_STATUS_MESSAGE_REJECTED 0x0D
2079 #define SRB_STATUS_BUS_RESET 0x0E
2080 #define SRB_STATUS_PARITY_ERROR 0x0F
2081 #define SRB_STATUS_REQUEST_SENSE_FAILED 0x10
2082 #define SRB_STATUS_NO_HBA 0x11
2083 #define SRB_STATUS_DATA_OVERRUN 0x12
2084 #define SRB_STATUS_UNEXPECTED_BUS_FREE 0x13
2085 #define SRB_STATUS_PHASE_SEQUENCE_FAILURE 0x14
2086 #define SRB_STATUS_BAD_SRB_BLOCK_LENGTH 0x15
2087 #define SRB_STATUS_REQUEST_FLUSHED 0x16
2088 #define SRB_STATUS_DELAYED_RETRY 0x17
2089 #define SRB_STATUS_INVALID_LUN 0x20
2090 #define SRB_STATUS_INVALID_TARGET_ID 0x21
2091 #define SRB_STATUS_BAD_FUNCTION 0x22
2092 #define SRB_STATUS_ERROR_RECOVERY 0x23
2093 #define SRB_STATUS_NOT_STARTED 0x24
2094 #define SRB_STATUS_NOT_IN_USE 0x30
2095 #define SRB_STATUS_FORCE_ABORT 0x31
2096 #define SRB_STATUS_DOMAIN_VALIDATION_FAIL 0x32
2097
2098 /*
2099 * Object-Server / Volume-Manager Dispatch Classes
2100 */
2101
2102 #define VM_Null 0
2103 #define VM_NameServe 1
2104 #define VM_ContainerConfig 2
2105 #define VM_Ioctl 3
2106 #define VM_FilesystemIoctl 4
2107 #define VM_CloseAll 5
2108 #define VM_CtBlockRead 6
2109 #define VM_CtBlockWrite 7
2110 #define VM_SliceBlockRead 8 /* raw access to configured "storage objects" */
2111 #define VM_SliceBlockWrite 9
2112 #define VM_DriveBlockRead 10 /* raw access to physical devices */
2113 #define VM_DriveBlockWrite 11
2114 #define VM_EnclosureMgt 12 /* enclosure management */
2115 #define VM_Unused 13 /* used to be diskset management */
2116 #define VM_CtBlockVerify 14
2117 #define VM_CtPerf 15 /* performance test */
2118 #define VM_CtBlockRead64 16
2119 #define VM_CtBlockWrite64 17
2120 #define VM_CtBlockVerify64 18
2121 #define VM_CtHostRead64 19
2122 #define VM_CtHostWrite64 20
2123 #define VM_DrvErrTblLog 21
2124 #define VM_NameServe64 22
2125 #define VM_NameServeAllBlk 30
2126
2127 #define MAX_VMCOMMAND_NUM 23 /* used for sizing stats array - leave last */
2128
2129 /*
2130 * Descriptive information (eg, vital stats)
2131 * that a content manager might report. The
2132 * FileArray filesystem component is one example
2133 * of a content manager. Raw mode might be
2134 * another.
2135 */
2136
2137 struct aac_fsinfo {
2138 __le32 fsTotalSize; /* Consumed by fs, incl. metadata */
2139 __le32 fsBlockSize;
2140 __le32 fsFragSize;
2141 __le32 fsMaxExtendSize;
2142 __le32 fsSpaceUnits;
2143 __le32 fsMaxNumFiles;
2144 __le32 fsNumFreeFiles;
2145 __le32 fsInodeDensity;
2146 }; /* valid iff ObjType == FT_FILESYS && !(ContentState & FSCS_NOTCLEAN) */
2147
2148 struct aac_blockdevinfo {
2149 __le32 block_size;
2150 __le32 logical_phys_map;
2151 u8 identifier[16];
2152 };
2153
2154 union aac_contentinfo {
2155 struct aac_fsinfo filesys;
2156 struct aac_blockdevinfo bdevinfo;
2157 };
2158
2159 /*
2160 * Query for Container Configuration Status
2161 */
2162
2163 #define CT_GET_CONFIG_STATUS 147
2164 struct aac_get_config_status {
2165 __le32 command; /* VM_ContainerConfig */
2166 __le32 type; /* CT_GET_CONFIG_STATUS */
2167 __le32 parm1;
2168 __le32 parm2;
2169 __le32 parm3;
2170 __le32 parm4;
2171 __le32 parm5;
2172 __le32 count; /* sizeof(((struct aac_get_config_status_resp *)NULL)->data) */
2173 };
2174
2175 #define CFACT_CONTINUE 0
2176 #define CFACT_PAUSE 1
2177 #define CFACT_ABORT 2
2178 struct aac_get_config_status_resp {
2179 __le32 response; /* ST_OK */
2180 __le32 dummy0;
2181 __le32 status; /* CT_OK */
2182 __le32 parm1;
2183 __le32 parm2;
2184 __le32 parm3;
2185 __le32 parm4;
2186 __le32 parm5;
2187 struct {
2188 __le32 action; /* CFACT_CONTINUE, CFACT_PAUSE or CFACT_ABORT */
2189 __le16 flags;
2190 __le16 count;
2191 } data;
2192 };
2193
2194 /*
2195 * Accept the configuration as-is
2196 */
2197
2198 #define CT_COMMIT_CONFIG 152
2199
2200 struct aac_commit_config {
2201 __le32 command; /* VM_ContainerConfig */
2202 __le32 type; /* CT_COMMIT_CONFIG */
2203 };
2204
2205 /*
2206 * Query for Container Configuration Status
2207 */
2208
2209 #define CT_GET_CONTAINER_COUNT 4
2210 struct aac_get_container_count {
2211 __le32 command; /* VM_ContainerConfig */
2212 __le32 type; /* CT_GET_CONTAINER_COUNT */
2213 };
2214
2215 struct aac_get_container_count_resp {
2216 __le32 response; /* ST_OK */
2217 __le32 dummy0;
2218 __le32 MaxContainers;
2219 __le32 ContainerSwitchEntries;
2220 __le32 MaxPartitions;
2221 __le32 MaxSimpleVolumes;
2222 };
2223
2224
2225 /*
2226 * Query for "mountable" objects, ie, objects that are typically
2227 * associated with a drive letter on the client (host) side.
2228 */
2229
2230 struct aac_mntent {
2231 __le32 oid;
2232 u8 name[16]; /* if applicable */
2233 struct creation_info create_info; /* if applicable */
2234 __le32 capacity;
2235 __le32 vol; /* substrate structure */
2236 __le32 obj; /* FT_FILESYS, etc. */
2237 __le32 state; /* unready for mounting,
2238 readonly, etc. */
2239 union aac_contentinfo fileinfo; /* Info specific to content
2240 manager (eg, filesystem) */
2241 __le32 altoid; /* != oid <==> snapshot or
2242 broken mirror exists */
2243 __le32 capacityhigh;
2244 };
2245
2246 #define FSCS_NOTCLEAN 0x0001 /* fsck is necessary before mounting */
2247 #define FSCS_READONLY 0x0002 /* possible result of broken mirror */
2248 #define FSCS_HIDDEN 0x0004 /* should be ignored - set during a clear */
2249 #define FSCS_NOT_READY 0x0008 /* Array spinning up to fulfil request */
2250
2251 struct aac_query_mount {
2252 __le32 command;
2253 __le32 type;
2254 __le32 count;
2255 };
2256
2257 struct aac_mount {
2258 __le32 status;
2259 __le32 type; /* should be same as that requested */
2260 __le32 count;
2261 struct aac_mntent mnt[1];
2262 };
2263
2264 #define CT_READ_NAME 130
2265 struct aac_get_name {
2266 __le32 command; /* VM_ContainerConfig */
2267 __le32 type; /* CT_READ_NAME */
2268 __le32 cid;
2269 __le32 parm1;
2270 __le32 parm2;
2271 __le32 parm3;
2272 __le32 parm4;
2273 __le32 count; /* sizeof(((struct aac_get_name_resp *)NULL)->data) */
2274 };
2275
2276 struct aac_get_name_resp {
2277 __le32 dummy0;
2278 __le32 dummy1;
2279 __le32 status; /* CT_OK */
2280 __le32 parm1;
2281 __le32 parm2;
2282 __le32 parm3;
2283 __le32 parm4;
2284 __le32 parm5;
2285 u8 data[17];
2286 };
2287
2288 #define CT_CID_TO_32BITS_UID 165
2289 struct aac_get_serial {
2290 __le32 command; /* VM_ContainerConfig */
2291 __le32 type; /* CT_CID_TO_32BITS_UID */
2292 __le32 cid;
2293 };
2294
2295 struct aac_get_serial_resp {
2296 __le32 dummy0;
2297 __le32 dummy1;
2298 __le32 status; /* CT_OK */
2299 __le32 uid;
2300 };
2301
2302 /*
2303 * The following command is sent to shut down each container.
2304 */
2305
2306 struct aac_close {
2307 __le32 command;
2308 __le32 cid;
2309 };
2310
2311 struct aac_query_disk
2312 {
2313 s32 cnum;
2314 s32 bus;
2315 s32 id;
2316 s32 lun;
2317 u32 valid;
2318 u32 locked;
2319 u32 deleted;
2320 s32 instance;
2321 s8 name[10];
2322 u32 unmapped;
2323 };
2324
2325 struct aac_delete_disk {
2326 u32 disknum;
2327 u32 cnum;
2328 };
2329
2330 struct fib_ioctl
2331 {
2332 u32 fibctx;
2333 s32 wait;
2334 char __user *fib;
2335 };
2336
2337 struct revision
2338 {
2339 u32 compat;
2340 __le32 version;
2341 __le32 build;
2342 };
2343
2344
2345 /*
2346 * Ugly - non Linux like ioctl coding for back compat.
2347 */
2348
2349 #define CTL_CODE(function, method) ( \
2350 (4<< 16) | ((function) << 2) | (method) \
2351 )
2352
2353 /*
2354 * Define the method codes for how buffers are passed for I/O and FS
2355 * controls
2356 */
2357
2358 #define METHOD_BUFFERED 0
2359 #define METHOD_NEITHER 3
2360
2361 /*
2362 * Filesystem ioctls
2363 */
2364
2365 #define FSACTL_SENDFIB CTL_CODE(2050, METHOD_BUFFERED)
2366 #define FSACTL_SEND_RAW_SRB CTL_CODE(2067, METHOD_BUFFERED)
2367 #define FSACTL_DELETE_DISK 0x163
2368 #define FSACTL_QUERY_DISK 0x173
2369 #define FSACTL_OPEN_GET_ADAPTER_FIB CTL_CODE(2100, METHOD_BUFFERED)
2370 #define FSACTL_GET_NEXT_ADAPTER_FIB CTL_CODE(2101, METHOD_BUFFERED)
2371 #define FSACTL_CLOSE_GET_ADAPTER_FIB CTL_CODE(2102, METHOD_BUFFERED)
2372 #define FSACTL_MINIPORT_REV_CHECK CTL_CODE(2107, METHOD_BUFFERED)
2373 #define FSACTL_GET_PCI_INFO CTL_CODE(2119, METHOD_BUFFERED)
2374 #define FSACTL_FORCE_DELETE_DISK CTL_CODE(2120, METHOD_NEITHER)
2375 #define FSACTL_GET_CONTAINERS 2131
2376 #define FSACTL_SEND_LARGE_FIB CTL_CODE(2138, METHOD_BUFFERED)
2377 #define FSACTL_RESET_IOP CTL_CODE(2140, METHOD_BUFFERED)
2378 #define FSACTL_GET_HBA_INFO CTL_CODE(2150, METHOD_BUFFERED)
2379 /* flags defined for IOP & HW SOFT RESET */
2380 #define HW_IOP_RESET 0x01
2381 #define HW_SOFT_RESET 0x02
2382 #define IOP_HWSOFT_RESET (HW_IOP_RESET | HW_SOFT_RESET)
2383 /* HW Soft Reset register offset */
2384 #define IBW_SWR_OFFSET 0x4000
2385 #define SOFT_RESET_TIME 60
2386
2387
2388
2389 struct aac_common
2390 {
2391 /*
2392 * If this value is set to 1 then interrupt moderation will occur
2393 * in the base commuication support.
2394 */
2395 u32 irq_mod;
2396 u32 peak_fibs;
2397 u32 zero_fibs;
2398 u32 fib_timeouts;
2399 /*
2400 * Statistical counters in debug mode
2401 */
2402 #ifdef DBG
2403 u32 FibsSent;
2404 u32 FibRecved;
2405 u32 NativeSent;
2406 u32 NativeRecved;
2407 u32 NoResponseSent;
2408 u32 NoResponseRecved;
2409 u32 AsyncSent;
2410 u32 AsyncRecved;
2411 u32 NormalSent;
2412 u32 NormalRecved;
2413 #endif
2414 };
2415
2416 extern struct aac_common aac_config;
2417
2418 /*
2419 * This is for management ioctl purpose only.
2420 */
2421 struct aac_hba_info {
2422
2423 u8 driver_name[50];
2424 u8 adapter_number;
2425 u8 system_io_bus_number;
2426 u8 device_number;
2427 u32 function_number;
2428 u32 vendor_id;
2429 u32 device_id;
2430 u32 sub_vendor_id;
2431 u32 sub_system_id;
2432 u32 mapped_base_address_size;
2433 u32 base_physical_address_high_part;
2434 u32 base_physical_address_low_part;
2435
2436 u32 max_command_size;
2437 u32 max_fib_size;
2438 u32 max_scatter_gather_from_os;
2439 u32 max_scatter_gather_to_fw;
2440 u32 max_outstanding_fibs;
2441
2442 u32 queue_start_threshold;
2443 u32 queue_dump_threshold;
2444 u32 max_io_size_queued;
2445 u32 outstanding_io;
2446
2447 u32 firmware_build_number;
2448 u32 bios_build_number;
2449 u32 driver_build_number;
2450 u32 serial_number_high_part;
2451 u32 serial_number_low_part;
2452 u32 supported_options;
2453 u32 feature_bits;
2454 u32 currentnumber_ports;
2455
2456 u8 new_comm_interface:1;
2457 u8 new_commands_supported:1;
2458 u8 disable_passthrough:1;
2459 u8 expose_non_dasd:1;
2460 u8 queue_allowed:1;
2461 u8 bled_check_enabled:1;
2462 u8 reserved1:1;
2463 u8 reserted2:1;
2464
2465 u32 reserved3[10];
2466
2467 };
2468
2469 /*
2470 * The following macro is used when sending and receiving FIBs. It is
2471 * only used for debugging.
2472 */
2473
2474 #ifdef DBG
2475 #define FIB_COUNTER_INCREMENT(counter) (counter)++
2476 #else
2477 #define FIB_COUNTER_INCREMENT(counter)
2478 #endif
2479
2480 /*
2481 * Adapter direct commands
2482 * Monitor/Kernel API
2483 */
2484
2485 #define BREAKPOINT_REQUEST 0x00000004
2486 #define INIT_STRUCT_BASE_ADDRESS 0x00000005
2487 #define READ_PERMANENT_PARAMETERS 0x0000000a
2488 #define WRITE_PERMANENT_PARAMETERS 0x0000000b
2489 #define HOST_CRASHING 0x0000000d
2490 #define SEND_SYNCHRONOUS_FIB 0x0000000c
2491 #define COMMAND_POST_RESULTS 0x00000014
2492 #define GET_ADAPTER_PROPERTIES 0x00000019
2493 #define GET_DRIVER_BUFFER_PROPERTIES 0x00000023
2494 #define RCV_TEMP_READINGS 0x00000025
2495 #define GET_COMM_PREFERRED_SETTINGS 0x00000026
2496 #define IOP_RESET_FW_FIB_DUMP 0x00000034
2497 #define DROP_IO 0x00000035
2498 #define IOP_RESET 0x00001000
2499 #define IOP_RESET_ALWAYS 0x00001001
2500 #define RE_INIT_ADAPTER 0x000000ee
2501
2502 #define IOP_SRC_RESET_MASK 0x00000100
2503
2504 /*
2505 * Adapter Status Register
2506 *
2507 * Phase Staus mailbox is 32bits:
2508 * <31:16> = Phase Status
2509 * <15:0> = Phase
2510 *
2511 * The adapter reports is present state through the phase. Only
2512 * a single phase should be ever be set. Each phase can have multiple
2513 * phase status bits to provide more detailed information about the
2514 * state of the board. Care should be taken to ensure that any phase
2515 * status bits that are set when changing the phase are also valid
2516 * for the new phase or be cleared out. Adapter software (monitor,
2517 * iflash, kernel) is responsible for properly maintining the phase
2518 * status mailbox when it is running.
2519 *
2520 * MONKER_API Phases
2521 *
2522 * Phases are bit oriented. It is NOT valid to have multiple bits set
2523 */
2524
2525 #define SELF_TEST_FAILED 0x00000004
2526 #define MONITOR_PANIC 0x00000020
2527 #define KERNEL_BOOTING 0x00000040
2528 #define KERNEL_UP_AND_RUNNING 0x00000080
2529 #define KERNEL_PANIC 0x00000100
2530 #define FLASH_UPD_PENDING 0x00002000
2531 #define FLASH_UPD_SUCCESS 0x00004000
2532 #define FLASH_UPD_FAILED 0x00008000
2533 #define INVALID_OMR 0xffffffff
2534 #define FWUPD_TIMEOUT (5 * 60)
2535
2536 /*
2537 * Doorbell bit defines
2538 */
2539
2540 #define DoorBellSyncCmdAvailable (1<<0) /* Host -> Adapter */
2541 #define DoorBellPrintfDone (1<<5) /* Host -> Adapter */
2542 #define DoorBellAdapterNormCmdReady (1<<1) /* Adapter -> Host */
2543 #define DoorBellAdapterNormRespReady (1<<2) /* Adapter -> Host */
2544 #define DoorBellAdapterNormCmdNotFull (1<<3) /* Adapter -> Host */
2545 #define DoorBellAdapterNormRespNotFull (1<<4) /* Adapter -> Host */
2546 #define DoorBellPrintfReady (1<<5) /* Adapter -> Host */
2547 #define DoorBellAifPending (1<<6) /* Adapter -> Host */
2548
2549 /* PMC specific outbound doorbell bits */
2550 #define PmDoorBellResponseSent (1<<1) /* Adapter -> Host */
2551
2552 /*
2553 * For FIB communication, we need all of the following things
2554 * to send back to the user.
2555 */
2556
2557 #define AifCmdEventNotify 1 /* Notify of event */
2558 #define AifEnConfigChange 3 /* Adapter configuration change */
2559 #define AifEnContainerChange 4 /* Container configuration change */
2560 #define AifEnDeviceFailure 5 /* SCSI device failed */
2561 #define AifEnEnclosureManagement 13 /* EM_DRIVE_* */
2562 #define EM_DRIVE_INSERTION 31
2563 #define EM_DRIVE_REMOVAL 32
2564 #define EM_SES_DRIVE_INSERTION 33
2565 #define EM_SES_DRIVE_REMOVAL 26
2566 #define AifEnBatteryEvent 14 /* Change in Battery State */
2567 #define AifEnAddContainer 15 /* A new array was created */
2568 #define AifEnDeleteContainer 16 /* A container was deleted */
2569 #define AifEnExpEvent 23 /* Firmware Event Log */
2570 #define AifExeFirmwarePanic 3 /* Firmware Event Panic */
2571 #define AifHighPriority 3 /* Highest Priority Event */
2572 #define AifEnAddJBOD 30 /* JBOD created */
2573 #define AifEnDeleteJBOD 31 /* JBOD deleted */
2574
2575 #define AifBuManagerEvent 42 /* Bu management*/
2576 #define AifBuCacheDataLoss 10
2577 #define AifBuCacheDataRecover 11
2578
2579 #define AifCmdJobProgress 2 /* Progress report */
2580 #define AifJobCtrZero 101 /* Array Zero progress */
2581 #define AifJobStsSuccess 1 /* Job completes */
2582 #define AifJobStsRunning 102 /* Job running */
2583 #define AifCmdAPIReport 3 /* Report from other user of API */
2584 #define AifCmdDriverNotify 4 /* Notify host driver of event */
2585 #define AifDenMorphComplete 200 /* A morph operation completed */
2586 #define AifDenVolumeExtendComplete 201 /* A volume extend completed */
2587 #define AifReqJobList 100 /* Gets back complete job list */
2588 #define AifReqJobsForCtr 101 /* Gets back jobs for specific container */
2589 #define AifReqJobsForScsi 102 /* Gets back jobs for specific SCSI device */
2590 #define AifReqJobReport 103 /* Gets back a specific job report or list of them */
2591 #define AifReqTerminateJob 104 /* Terminates job */
2592 #define AifReqSuspendJob 105 /* Suspends a job */
2593 #define AifReqResumeJob 106 /* Resumes a job */
2594 #define AifReqSendAPIReport 107 /* API generic report requests */
2595 #define AifReqAPIJobStart 108 /* Start a job from the API */
2596 #define AifReqAPIJobUpdate 109 /* Update a job report from the API */
2597 #define AifReqAPIJobFinish 110 /* Finish a job from the API */
2598
2599 /* PMC NEW COMM: Request the event data */
2600 #define AifReqEvent 200
2601 #define AifRawDeviceRemove 203 /* RAW device deleted */
2602 #define AifNativeDeviceAdd 204 /* native HBA device added */
2603 #define AifNativeDeviceRemove 205 /* native HBA device removed */
2604
2605
2606 /*
2607 * Adapter Initiated FIB command structures. Start with the adapter
2608 * initiated FIBs that really come from the adapter, and get responded
2609 * to by the host.
2610 */
2611
2612 struct aac_aifcmd {
2613 __le32 command; /* Tell host what type of notify this is */
2614 __le32 seqnum; /* To allow ordering of reports (if necessary) */
2615 u8 data[]; /* Undefined length (from kernel viewpoint) */
2616 };
2617
2618 /**
2619 * Convert capacity to cylinders
2620 * accounting for the fact capacity could be a 64 bit value
2621 *
2622 */
2623 static inline unsigned int cap_to_cyls(sector_t capacity, unsigned divisor)
2624 {
2625 sector_div(capacity, divisor);
2626 return capacity;
2627 }
2628
2629 static inline int aac_pci_offline(struct aac_dev *dev)
2630 {
2631 return pci_channel_offline(dev->pdev) || dev->handle_pci_error;
2632 }
2633
2634 static inline int aac_adapter_check_health(struct aac_dev *dev)
2635 {
2636 if (unlikely(aac_pci_offline(dev)))
2637 return -1;
2638
2639 return (dev)->a_ops.adapter_check_health(dev);
2640 }
2641
2642
2643 int aac_scan_host(struct aac_dev *dev);
2644
2645 static inline void aac_schedule_safw_scan_worker(struct aac_dev *dev)
2646 {
2647 schedule_delayed_work(&dev->safw_rescan_work, AAC_RESCAN_DELAY);
2648 }
2649
2650 static inline void aac_schedule_src_reinit_aif_worker(struct aac_dev *dev)
2651 {
2652 schedule_delayed_work(&dev->src_reinit_aif_worker, AAC_RESCAN_DELAY);
2653 }
2654
2655 static inline void aac_safw_rescan_worker(struct work_struct *work)
2656 {
2657 struct aac_dev *dev = container_of(to_delayed_work(work),
2658 struct aac_dev, safw_rescan_work);
2659
2660 wait_event(dev->scsi_host_ptr->host_wait,
2661 !scsi_host_in_recovery(dev->scsi_host_ptr));
2662
2663 aac_scan_host(dev);
2664 }
2665
2666 static inline void aac_cancel_rescan_worker(struct aac_dev *dev)
2667 {
2668 cancel_delayed_work_sync(&dev->safw_rescan_work);
2669 cancel_delayed_work_sync(&dev->src_reinit_aif_worker);
2670 }
2671
2672 enum aac_cmd_owner {
2673 AAC_OWNER_MIDLEVEL = 0x101,
2674 AAC_OWNER_LOWLEVEL = 0x102,
2675 AAC_OWNER_ERROR_HANDLER = 0x103,
2676 AAC_OWNER_FIRMWARE = 0x106,
2677 };
2678
2679 struct aac_cmd_priv {
2680 int (*callback)(struct scsi_cmnd *);
2681 int status;
2682 enum aac_cmd_owner owner;
2683 bool sent_command;
2684 };
2685
2686 static inline struct aac_cmd_priv *aac_priv(struct scsi_cmnd *cmd)
2687 {
2688 return scsi_cmd_priv(cmd);
2689 }
2690
2691 void aac_safw_rescan_worker(struct work_struct *work);
2692 void aac_src_reinit_aif_worker(struct work_struct *work);
2693 int aac_acquire_irq(struct aac_dev *dev);
2694 void aac_free_irq(struct aac_dev *dev);
2695 int aac_setup_safw_adapter(struct aac_dev *dev);
2696 const char *aac_driverinfo(struct Scsi_Host *);
2697 void aac_fib_vector_assign(struct aac_dev *dev);
2698 struct fib *aac_fib_alloc(struct aac_dev *dev);
2699 struct fib *aac_fib_alloc_tag(struct aac_dev *dev, struct scsi_cmnd *scmd);
2700 int aac_fib_setup(struct aac_dev *dev);
2701 void aac_fib_map_free(struct aac_dev *dev);
2702 void aac_fib_free(struct fib * context);
2703 void aac_fib_init(struct fib * context);
2704 void aac_printf(struct aac_dev *dev, u32 val);
2705 int aac_fib_send(u16 command, struct fib * context, unsigned long size, int priority, int wait, int reply, fib_callback callback, void *ctxt);
2706 int aac_hba_send(u8 command, struct fib *context,
2707 fib_callback callback, void *ctxt);
2708 int aac_consumer_get(struct aac_dev * dev, struct aac_queue * q, struct aac_entry **entry);
2709 void aac_consumer_free(struct aac_dev * dev, struct aac_queue * q, u32 qnum);
2710 int aac_fib_complete(struct fib * context);
2711 void aac_hba_callback(void *context, struct fib *fibptr);
2712 #define fib_data(fibctx) ((void *)(fibctx)->hw_fib_va->data)
2713 struct aac_dev *aac_init_adapter(struct aac_dev *dev);
2714 void aac_src_access_devreg(struct aac_dev *dev, int mode);
2715 void aac_set_intx_mode(struct aac_dev *dev);
2716 int aac_get_config_status(struct aac_dev *dev, int commit_flag);
2717 int aac_get_containers(struct aac_dev *dev);
2718 int aac_scsi_cmd(struct scsi_cmnd *cmd);
2719 int aac_dev_ioctl(struct aac_dev *dev, unsigned int cmd, void __user *arg);
2720 #ifndef shost_to_class
2721 #define shost_to_class(shost) &shost->shost_dev
2722 #endif
2723 ssize_t aac_get_serial_number(struct device *dev, char *buf);
2724 int aac_do_ioctl(struct aac_dev *dev, unsigned int cmd, void __user *arg);
2725 int aac_rx_init(struct aac_dev *dev);
2726 int aac_rkt_init(struct aac_dev *dev);
2727 int aac_nark_init(struct aac_dev *dev);
2728 int aac_sa_init(struct aac_dev *dev);
2729 int aac_src_init(struct aac_dev *dev);
2730 int aac_srcv_init(struct aac_dev *dev);
2731 int aac_queue_get(struct aac_dev * dev, u32 * index, u32 qid, struct hw_fib * hw_fib, int wait, struct fib * fibptr, unsigned long *nonotify);
2732 void aac_define_int_mode(struct aac_dev *dev);
2733 unsigned int aac_response_normal(struct aac_queue * q);
2734 unsigned int aac_command_normal(struct aac_queue * q);
2735 unsigned int aac_intr_normal(struct aac_dev *dev, u32 Index,
2736 int isAif, int isFastResponse,
2737 struct hw_fib *aif_fib);
2738 int aac_reset_adapter(struct aac_dev *dev, int forced, u8 reset_type);
2739 int aac_check_health(struct aac_dev * dev);
2740 int aac_command_thread(void *data);
2741 int aac_close_fib_context(struct aac_dev * dev, struct aac_fib_context *fibctx);
2742 int aac_fib_adapter_complete(struct fib * fibptr, unsigned short size);
2743 struct aac_driver_ident* aac_get_driver_ident(int devtype);
2744 int aac_get_adapter_info(struct aac_dev* dev);
2745 int aac_send_shutdown(struct aac_dev *dev);
2746 int aac_probe_container(struct aac_dev *dev, int cid);
2747 int _aac_rx_init(struct aac_dev *dev);
2748 int aac_rx_select_comm(struct aac_dev *dev, int comm);
2749 int aac_rx_deliver_producer(struct fib * fib);
2750 void aac_reinit_aif(struct aac_dev *aac, unsigned int index);
2751
2752 static inline int aac_is_src(struct aac_dev *dev)
2753 {
2754 u16 device = dev->pdev->device;
2755
2756 if (device == PMC_DEVICE_S6 ||
2757 device == PMC_DEVICE_S7 ||
2758 device == PMC_DEVICE_S8)
2759 return 1;
2760 return 0;
2761 }
2762
2763 static inline int aac_supports_2T(struct aac_dev *dev)
2764 {
2765 return (dev->adapter_info.options & AAC_OPT_NEW_COMM_64);
2766 }
2767
2768 char * get_container_type(unsigned type);
2769 extern int numacb;
2770 extern char aac_driver_version[];
2771 extern int startup_timeout;
2772 extern int aif_timeout;
2773 extern int expose_physicals;
2774 extern int aac_reset_devices;
2775 extern int aac_msi;
2776 extern int aac_commit;
2777 extern int update_interval;
2778 extern int check_interval;
2779 extern int aac_check_reset;
2780 extern int aac_fib_dump;
2781 #endif
Kernel DRM miscellaneous fixes and cross-tree changes