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drm/tests: hdmi: Fix memory leaks in drm_display_mode_from_cea_vic()
[drm/drm-misc.git] / drivers / scsi / esp_scsi.h
blob00cd7c0ccc769833dcca75159419e0c59edad651
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* esp_scsi.h: Defines and structures for the ESP driver.
3 *
4 * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
5 */
6
7 #ifndef _ESP_SCSI_H
8 #define _ESP_SCSI_H
9
10 /* Access Description Offset */
11 #define ESP_TCLOW 0x00UL /* rw Low bits transfer count 0x00 */
12 #define ESP_TCMED 0x01UL /* rw Mid bits transfer count 0x04 */
13 #define ESP_FDATA 0x02UL /* rw FIFO data bits 0x08 */
14 #define ESP_CMD 0x03UL /* rw SCSI command bits 0x0c */
15 #define ESP_STATUS 0x04UL /* ro ESP status register 0x10 */
16 #define ESP_BUSID ESP_STATUS /* wo BusID for sel/resel 0x10 */
17 #define ESP_INTRPT 0x05UL /* ro Kind of interrupt 0x14 */
18 #define ESP_TIMEO ESP_INTRPT /* wo Timeout for sel/resel 0x14 */
19 #define ESP_SSTEP 0x06UL /* ro Sequence step register 0x18 */
20 #define ESP_STP ESP_SSTEP /* wo Transfer period/sync 0x18 */
21 #define ESP_FFLAGS 0x07UL /* ro Bits current FIFO info 0x1c */
22 #define ESP_SOFF ESP_FFLAGS /* wo Sync offset 0x1c */
23 #define ESP_CFG1 0x08UL /* rw First cfg register 0x20 */
24 #define ESP_CFACT 0x09UL /* wo Clock conv factor 0x24 */
25 #define ESP_STATUS2 ESP_CFACT /* ro HME status2 register 0x24 */
26 #define ESP_CTEST 0x0aUL /* wo Chip test register 0x28 */
27 #define ESP_CFG2 0x0bUL /* rw Second cfg register 0x2c */
28 #define ESP_CFG3 0x0cUL /* rw Third cfg register 0x30 */
29 #define ESP_CFG4 0x0dUL /* rw Fourth cfg register 0x34 */
30 #define ESP_TCHI 0x0eUL /* rw High bits transf count 0x38 */
31 #define ESP_UID ESP_TCHI /* ro Unique ID code 0x38 */
32 #define FAS_RLO ESP_TCHI /* rw HME extended counter 0x38 */
33 #define ESP_FGRND 0x0fUL /* rw Data base for fifo 0x3c */
34 #define FAS_RHI ESP_FGRND /* rw HME extended counter 0x3c */
35
36 #define SBUS_ESP_REG_SIZE 0x40UL
37
38 /* Bitfield meanings for the above registers. */
39
40 /* ESP config reg 1, read-write, found on all ESP chips */
41 #define ESP_CONFIG1_ID 0x07 /* My BUS ID bits */
42 #define ESP_CONFIG1_CHTEST 0x08 /* Enable ESP chip tests */
43 #define ESP_CONFIG1_PENABLE 0x10 /* Enable parity checks */
44 #define ESP_CONFIG1_PARTEST 0x20 /* Parity test mode enabled? */
45 #define ESP_CONFIG1_SRRDISAB 0x40 /* Disable SCSI reset reports */
46 #define ESP_CONFIG1_SLCABLE 0x80 /* Enable slow cable mode */
47
48 /* ESP config reg 2, read-write, found only on esp100a+esp200+esp236 chips */
49 #define ESP_CONFIG2_DMAPARITY 0x01 /* enable DMA Parity (200,236) */
50 #define ESP_CONFIG2_REGPARITY 0x02 /* enable reg Parity (200,236) */
51 #define ESP_CONFIG2_BADPARITY 0x04 /* Bad parity target abort */
52 #define ESP_CONFIG2_SCSI2ENAB 0x08 /* Enable SCSI-2 features (tgtmode) */
53 #define ESP_CONFIG2_HI 0x10 /* High Impedance DREQ ??? */
54 #define ESP_CONFIG2_HMEFENAB 0x10 /* HME features enable */
55 #define ESP_CONFIG2_BCM 0x20 /* Enable byte-ctrl (236) */
56 #define ESP_CONFIG2_DISPINT 0x20 /* Disable pause irq (hme) */
57 #define ESP_CONFIG2_FENAB 0x40 /* Enable features (fas100,216) */
58 #define ESP_CONFIG2_SPL 0x40 /* Enable status-phase latch (236) */
59 #define ESP_CONFIG2_MKDONE 0x40 /* HME magic feature */
60 #define ESP_CONFIG2_HME32 0x80 /* HME 32 extended */
61 #define ESP_CONFIG2_MAGIC 0xe0 /* Invalid bits... */
62
63 /* ESP config register 3 read-write, found only esp236+fas236+fas100a+hme chips */
64 #define ESP_CONFIG3_FCLOCK 0x01 /* FAST SCSI clock rate (esp100a/hme) */
65 #define ESP_CONFIG3_TEM 0x01 /* Enable thresh-8 mode (esp/fas236) */
66 #define ESP_CONFIG3_FAST 0x02 /* Enable FAST SCSI (esp100a/hme) */
67 #define ESP_CONFIG3_ADMA 0x02 /* Enable alternate-dma (esp/fas236) */
68 #define ESP_CONFIG3_TENB 0x04 /* group2 SCSI2 support (esp100a/hme) */
69 #define ESP_CONFIG3_SRB 0x04 /* Save residual byte (esp/fas236) */
70 #define ESP_CONFIG3_TMS 0x08 /* Three-byte msg's ok (esp100a/hme) */
71 #define ESP_CONFIG3_FCLK 0x08 /* Fast SCSI clock rate (esp/fas236) */
72 #define ESP_CONFIG3_IDMSG 0x10 /* ID message checking (esp100a/hme) */
73 #define ESP_CONFIG3_FSCSI 0x10 /* Enable FAST SCSI (esp/fas236) */
74 #define ESP_CONFIG3_GTM 0x20 /* group2 SCSI2 support (esp/fas236) */
75 #define ESP_CONFIG3_IDBIT3 0x20 /* Bit 3 of HME SCSI-ID (hme) */
76 #define ESP_CONFIG3_TBMS 0x40 /* Three-byte msg's ok (esp/fas236) */
77 #define ESP_CONFIG3_EWIDE 0x40 /* Enable Wide-SCSI (hme) */
78 #define ESP_CONFIG3_IMS 0x80 /* ID msg chk'ng (esp/fas236) */
79 #define ESP_CONFIG3_OBPUSH 0x80 /* Push odd-byte to dma (hme) */
80
81 /* ESP config register 4 read-write */
82 #define ESP_CONFIG4_BBTE 0x01 /* Back-to-back transfers (fsc) */
83 #define ESP_CONGIG4_TEST 0x02 /* Transfer counter test mode (fsc) */
84 #define ESP_CONFIG4_RADE 0x04 /* Active negation (am53c974/fsc) */
85 #define ESP_CONFIG4_RAE 0x08 /* Act. negation REQ/ACK (am53c974) */
86 #define ESP_CONFIG4_PWD 0x20 /* Reduced power feature (am53c974) */
87 #define ESP_CONFIG4_GE0 0x40 /* Glitch eater bit 0 (am53c974) */
88 #define ESP_CONFIG4_GE1 0x80 /* Glitch eater bit 1 (am53c974) */
89
90 #define ESP_CONFIG_GE_12NS (0)
91 #define ESP_CONFIG_GE_25NS (ESP_CONFIG_GE1)
92 #define ESP_CONFIG_GE_35NS (ESP_CONFIG_GE0)
93 #define ESP_CONFIG_GE_0NS (ESP_CONFIG_GE0 | ESP_CONFIG_GE1)
94
95 /* ESP command register read-write */
96 /* Group 1 commands: These may be sent at any point in time to the ESP
97 * chip. None of them can generate interrupts 'cept
98 * the "SCSI bus reset" command if you have not disabled
99 * SCSI reset interrupts in the config1 ESP register.
100 */
101 #define ESP_CMD_NULL 0x00 /* Null command, ie. a nop */
102 #define ESP_CMD_FLUSH 0x01 /* FIFO Flush */
103 #define ESP_CMD_RC 0x02 /* Chip reset */
104 #define ESP_CMD_RS 0x03 /* SCSI bus reset */
105
106 /* Group 2 commands: ESP must be an initiator and connected to a target
107 * for these commands to work.
108 */
109 #define ESP_CMD_TI 0x10 /* Transfer Information */
110 #define ESP_CMD_ICCSEQ 0x11 /* Initiator cmd complete sequence */
111 #define ESP_CMD_MOK 0x12 /* Message okie-dokie */
112 #define ESP_CMD_TPAD 0x18 /* Transfer Pad */
113 #define ESP_CMD_SATN 0x1a /* Set ATN */
114 #define ESP_CMD_RATN 0x1b /* De-assert ATN */
115
116 /* Group 3 commands: ESP must be in the MSGOUT or MSGIN state and be connected
117 * to a target as the initiator for these commands to work.
118 */
119 #define ESP_CMD_SMSG 0x20 /* Send message */
120 #define ESP_CMD_SSTAT 0x21 /* Send status */
121 #define ESP_CMD_SDATA 0x22 /* Send data */
122 #define ESP_CMD_DSEQ 0x23 /* Discontinue Sequence */
123 #define ESP_CMD_TSEQ 0x24 /* Terminate Sequence */
124 #define ESP_CMD_TCCSEQ 0x25 /* Target cmd cmplt sequence */
125 #define ESP_CMD_DCNCT 0x27 /* Disconnect */
126 #define ESP_CMD_RMSG 0x28 /* Receive Message */
127 #define ESP_CMD_RCMD 0x29 /* Receive Command */
128 #define ESP_CMD_RDATA 0x2a /* Receive Data */
129 #define ESP_CMD_RCSEQ 0x2b /* Receive cmd sequence */
130
131 /* Group 4 commands: The ESP must be in the disconnected state and must
132 * not be connected to any targets as initiator for
133 * these commands to work.
134 */
135 #define ESP_CMD_RSEL 0x40 /* Reselect */
136 #define ESP_CMD_SEL 0x41 /* Select w/o ATN */
137 #define ESP_CMD_SELA 0x42 /* Select w/ATN */
138 #define ESP_CMD_SELAS 0x43 /* Select w/ATN & STOP */
139 #define ESP_CMD_ESEL 0x44 /* Enable selection */
140 #define ESP_CMD_DSEL 0x45 /* Disable selections */
141 #define ESP_CMD_SA3 0x46 /* Select w/ATN3 */
142 #define ESP_CMD_RSEL3 0x47 /* Reselect3 */
143
144 /* This bit enables the ESP's DMA on the SBus */
145 #define ESP_CMD_DMA 0x80 /* Do DMA? */
146
147 /* ESP status register read-only */
148 #define ESP_STAT_PIO 0x01 /* IO phase bit */
149 #define ESP_STAT_PCD 0x02 /* CD phase bit */
150 #define ESP_STAT_PMSG 0x04 /* MSG phase bit */
151 #define ESP_STAT_PMASK 0x07 /* Mask of phase bits */
152 #define ESP_STAT_TDONE 0x08 /* Transfer Completed */
153 #define ESP_STAT_TCNT 0x10 /* Transfer Counter Is Zero */
154 #define ESP_STAT_PERR 0x20 /* Parity error */
155 #define ESP_STAT_SPAM 0x40 /* Real bad error */
156 /* This indicates the 'interrupt pending' condition on esp236, it is a reserved
157 * bit on other revs of the ESP.
158 */
159 #define ESP_STAT_INTR 0x80 /* Interrupt */
160
161 /* The status register can be masked with ESP_STAT_PMASK and compared
162 * with the following values to determine the current phase the ESP
163 * (at least thinks it) is in. For our purposes we also add our own
164 * software 'done' bit for our phase management engine.
165 */
166 #define ESP_DOP (0) /* Data Out */
167 #define ESP_DIP (ESP_STAT_PIO) /* Data In */
168 #define ESP_CMDP (ESP_STAT_PCD) /* Command */
169 #define ESP_STATP (ESP_STAT_PCD|ESP_STAT_PIO) /* Status */
170 #define ESP_MOP (ESP_STAT_PMSG|ESP_STAT_PCD) /* Message Out */
171 #define ESP_MIP (ESP_STAT_PMSG|ESP_STAT_PCD|ESP_STAT_PIO) /* Message In */
172
173 /* HME only: status 2 register */
174 #define ESP_STAT2_SCHBIT 0x01 /* Upper bits 3-7 of sstep enabled */
175 #define ESP_STAT2_FFLAGS 0x02 /* The fifo flags are now latched */
176 #define ESP_STAT2_XCNT 0x04 /* The transfer counter is latched */
177 #define ESP_STAT2_CREGA 0x08 /* The command reg is active now */
178 #define ESP_STAT2_WIDE 0x10 /* Interface on this adapter is wide */
179 #define ESP_STAT2_F1BYTE 0x20 /* There is one byte at top of fifo */
180 #define ESP_STAT2_FMSB 0x40 /* Next byte in fifo is most significant */
181 #define ESP_STAT2_FEMPTY 0x80 /* FIFO is empty */
182
183 /* ESP interrupt register read-only */
184 #define ESP_INTR_S 0x01 /* Select w/o ATN */
185 #define ESP_INTR_SATN 0x02 /* Select w/ATN */
186 #define ESP_INTR_RSEL 0x04 /* Reselected */
187 #define ESP_INTR_FDONE 0x08 /* Function done */
188 #define ESP_INTR_BSERV 0x10 /* Bus service */
189 #define ESP_INTR_DC 0x20 /* Disconnect */
190 #define ESP_INTR_IC 0x40 /* Illegal command given */
191 #define ESP_INTR_SR 0x80 /* SCSI bus reset detected */
192
193 /* ESP sequence step register read-only */
194 #define ESP_STEP_VBITS 0x07 /* Valid bits */
195 #define ESP_STEP_ASEL 0x00 /* Selection&Arbitrate cmplt */
196 #define ESP_STEP_SID 0x01 /* One msg byte sent */
197 #define ESP_STEP_NCMD 0x02 /* Was not in command phase */
198 #define ESP_STEP_PPC 0x03 /* Early phase chg caused cmnd
199 * bytes to be lost
200 */
201 #define ESP_STEP_FINI4 0x04 /* Command was sent ok */
202
203 /* Ho hum, some ESP's set the step register to this as well... */
204 #define ESP_STEP_FINI5 0x05
205 #define ESP_STEP_FINI6 0x06
206 #define ESP_STEP_FINI7 0x07
207
208 /* ESP chip-test register read-write */
209 #define ESP_TEST_TARG 0x01 /* Target test mode */
210 #define ESP_TEST_INI 0x02 /* Initiator test mode */
211 #define ESP_TEST_TS 0x04 /* Tristate test mode */
212
213 /* ESP unique ID register read-only, found on fas236+fas100a only */
214 #define ESP_UID_FAM 0xf8 /* ESP family bitmask */
215
216 #define ESP_FAMILY(uid) (((uid) & ESP_UID_FAM) >> 3)
217
218 /* Values for the ESP family bits */
219 #define ESP_UID_F100A 0x00 /* ESP FAS100A */
220 #define ESP_UID_F236 0x02 /* ESP FAS236 */
221 #define ESP_UID_HME 0x0a /* FAS HME */
222 #define ESP_UID_FSC 0x14 /* NCR/Symbios Logic 53CF9x-2 */
223
224 /* ESP fifo flags register read-only */
225 /* Note that the following implies a 16 byte FIFO on the ESP. */
226 #define ESP_FF_FBYTES 0x1f /* Num bytes in FIFO */
227 #define ESP_FF_ONOTZERO 0x20 /* offset ctr not zero (esp100) */
228 #define ESP_FF_SSTEP 0xe0 /* Sequence step */
229
230 /* ESP clock conversion factor register write-only */
231 #define ESP_CCF_F0 0x00 /* 35.01MHz - 40MHz */
232 #define ESP_CCF_NEVER 0x01 /* Set it to this and die */
233 #define ESP_CCF_F2 0x02 /* 10MHz */
234 #define ESP_CCF_F3 0x03 /* 10.01MHz - 15MHz */
235 #define ESP_CCF_F4 0x04 /* 15.01MHz - 20MHz */
236 #define ESP_CCF_F5 0x05 /* 20.01MHz - 25MHz */
237 #define ESP_CCF_F6 0x06 /* 25.01MHz - 30MHz */
238 #define ESP_CCF_F7 0x07 /* 30.01MHz - 35MHz */
239
240 /* HME only... */
241 #define ESP_BUSID_RESELID 0x10
242 #define ESP_BUSID_CTR32BIT 0x40
243
244 #define ESP_BUS_TIMEOUT 250 /* In milli-seconds */
245 #define ESP_TIMEO_CONST 8192
246 #define ESP_NEG_DEFP(mhz, cfact) \
247 ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact)))
248 #define ESP_HZ_TO_CYCLE(hertz) ((1000000000) / ((hertz) / 1000))
249 #define ESP_TICK(ccf, cycle) ((7682 * (ccf) * (cycle) / 1000))
250
251 /* For slow to medium speed input clock rates we shoot for 5mb/s, but for high
252 * input clock rates we try to do 10mb/s although I don't think a transfer can
253 * even run that fast with an ESP even with DMA2 scatter gather pipelining.
254 */
255 #define SYNC_DEFP_SLOW 0x32 /* 5mb/s */
256 #define SYNC_DEFP_FAST 0x19 /* 10mb/s */
257
258 struct esp_cmd_priv {
259 int num_sg;
260 int cur_residue;
261 struct scatterlist *prv_sg;
262 struct scatterlist *cur_sg;
263 int tot_residue;
264 };
265
266 #define ESP_CMD_PRIV(cmd) ((struct esp_cmd_priv *)scsi_cmd_priv(cmd))
267
268 /* NOTE: this enum is ordered based on chip features! */
269 enum esp_rev {
270 ESP100, /* NCR53C90 - very broken */
271 ESP100A, /* NCR53C90A */
272 ESP236,
273 FAS236,
274 PCSCSI, /* AM53c974 */
275 FSC, /* NCR/Symbios Logic 53CF9x-2 */
276 FAS100A,
277 FAST,
278 FASHME,
279 };
280
281 struct esp_cmd_entry {
282 struct list_head list;
283
284 struct scsi_cmnd *cmd;
285
286 unsigned int saved_cur_residue;
287 struct scatterlist *saved_prv_sg;
288 struct scatterlist *saved_cur_sg;
289 unsigned int saved_tot_residue;
290
291 u8 flags;
292 #define ESP_CMD_FLAG_WRITE 0x01 /* DMA is a write */
293 #define ESP_CMD_FLAG_AUTOSENSE 0x04 /* Doing automatic REQUEST_SENSE */
294 #define ESP_CMD_FLAG_RESIDUAL 0x08 /* AM53c974 BLAST residual */
295
296 u8 tag[2];
297 u8 orig_tag[2];
298
299 u8 status;
300 u8 message;
301
302 unsigned char *sense_ptr;
303 unsigned char *saved_sense_ptr;
304 dma_addr_t sense_dma;
305
306 struct completion *eh_done;
307 };
308
309 #define ESP_DEFAULT_TAGS 16
310
311 #define ESP_MAX_TARGET 16
312 #define ESP_MAX_LUN 8
313 #define ESP_MAX_TAG 256
314
315 struct esp_lun_data {
316 struct esp_cmd_entry *non_tagged_cmd;
317 int num_tagged;
318 int hold;
319 struct esp_cmd_entry *tagged_cmds[ESP_MAX_TAG];
320 };
321
322 struct esp_target_data {
323 /* These are the ESP_STP, ESP_SOFF, and ESP_CFG3 register values which
324 * match the currently negotiated settings for this target. The SCSI
325 * protocol values are maintained in spi_{offset,period,wide}(starget).
326 */
327 u8 esp_period;
328 u8 esp_offset;
329 u8 esp_config3;
330
331 u8 flags;
332 #define ESP_TGT_WIDE 0x01
333 #define ESP_TGT_DISCONNECT 0x02
334 #define ESP_TGT_NEGO_WIDE 0x04
335 #define ESP_TGT_NEGO_SYNC 0x08
336 #define ESP_TGT_CHECK_NEGO 0x40
337 #define ESP_TGT_BROKEN 0x80
338
339 /* When ESP_TGT_CHECK_NEGO is set, on the next scsi command to this
340 * device we will try to negotiate the following parameters.
341 */
342 u8 nego_goal_period;
343 u8 nego_goal_offset;
344 u8 nego_goal_width;
345 u8 nego_goal_tags;
346
347 struct scsi_target *starget;
348 };
349
350 struct esp_event_ent {
351 u8 type;
352 #define ESP_EVENT_TYPE_EVENT 0x01
353 #define ESP_EVENT_TYPE_CMD 0x02
354 u8 val;
355
356 u8 sreg;
357 u8 seqreg;
358 u8 sreg2;
359 u8 ireg;
360 u8 select_state;
361 u8 event;
362 u8 __pad;
363 };
364
365 struct esp;
366 struct esp_driver_ops {
367 /* Read and write the ESP 8-bit registers. On some
368 * applications of the ESP chip the registers are at 4-byte
369 * instead of 1-byte intervals.
370 */
371 void (*esp_write8)(struct esp *esp, u8 val, unsigned long reg);
372 u8 (*esp_read8)(struct esp *esp, unsigned long reg);
373
374 /* Return non-zero if there is an IRQ pending. Usually this
375 * status bit lives in the DMA controller sitting in front of
376 * the ESP. This has to be accurate or else the ESP interrupt
377 * handler will not run.
378 */
379 int (*irq_pending)(struct esp *esp);
380
381 /* Return the maximum allowable size of a DMA transfer for a
382 * given buffer.
383 */
384 u32 (*dma_length_limit)(struct esp *esp, u32 dma_addr,
385 u32 dma_len);
386
387 /* Reset the DMA engine entirely. On return, ESP interrupts
388 * should be enabled. Often the interrupt enabling is
389 * controlled in the DMA engine.
390 */
391 void (*reset_dma)(struct esp *esp);
392
393 /* Drain any pending DMA in the DMA engine after a transfer.
394 * This is for writes to memory.
395 */
396 void (*dma_drain)(struct esp *esp);
397
398 /* Invalidate the DMA engine after a DMA transfer. */
399 void (*dma_invalidate)(struct esp *esp);
400
401 /* Setup an ESP command that will use a DMA transfer.
402 * The 'esp_count' specifies what transfer length should be
403 * programmed into the ESP transfer counter registers, whereas
404 * the 'dma_count' is the length that should be programmed into
405 * the DMA controller. Usually they are the same. If 'write'
406 * is non-zero, this transfer is a write into memory. 'cmd'
407 * holds the ESP command that should be issued by calling
408 * scsi_esp_cmd() at the appropriate time while programming
409 * the DMA hardware.
410 */
411 void (*send_dma_cmd)(struct esp *esp, u32 dma_addr, u32 esp_count,
412 u32 dma_count, int write, u8 cmd);
413
414 /* Return non-zero if the DMA engine is reporting an error
415 * currently.
416 */
417 int (*dma_error)(struct esp *esp);
418 };
419
420 #define ESP_MAX_MSG_SZ 8
421 #define ESP_EVENT_LOG_SZ 32
422
423 #define ESP_QUICKIRQ_LIMIT 100
424 #define ESP_RESELECT_TAG_LIMIT 2500
425
426 struct esp {
427 void __iomem *regs;
428 void __iomem *dma_regs;
429
430 const struct esp_driver_ops *ops;
431
432 struct Scsi_Host *host;
433 struct device *dev;
434
435 struct esp_cmd_entry *active_cmd;
436
437 struct list_head queued_cmds;
438 struct list_head active_cmds;
439
440 u8 *command_block;
441 dma_addr_t command_block_dma;
442
443 unsigned int data_dma_len;
444
445 /* The following are used to determine the cause of an IRQ. Upon every
446 * IRQ entry we synchronize these with the hardware registers.
447 */
448 u8 sreg;
449 u8 seqreg;
450 u8 sreg2;
451 u8 ireg;
452
453 u32 prev_hme_dmacsr;
454 u8 prev_soff;
455 u8 prev_stp;
456 u8 prev_cfg3;
457 u8 num_tags;
458
459 struct list_head esp_cmd_pool;
460
461 struct esp_target_data target[ESP_MAX_TARGET];
462
463 int fifo_cnt;
464 u8 fifo[16];
465
466 struct esp_event_ent esp_event_log[ESP_EVENT_LOG_SZ];
467 int esp_event_cur;
468
469 u8 msg_out[ESP_MAX_MSG_SZ];
470 int msg_out_len;
471
472 u8 msg_in[ESP_MAX_MSG_SZ];
473 int msg_in_len;
474
475 u8 bursts;
476 u8 config1;
477 u8 config2;
478 u8 config4;
479
480 u8 scsi_id;
481 u32 scsi_id_mask;
482
483 enum esp_rev rev;
484
485 u32 flags;
486 #define ESP_FLAG_DIFFERENTIAL 0x00000001
487 #define ESP_FLAG_RESETTING 0x00000002
488 #define ESP_FLAG_WIDE_CAPABLE 0x00000008
489 #define ESP_FLAG_QUICKIRQ_CHECK 0x00000010
490 #define ESP_FLAG_DISABLE_SYNC 0x00000020
491 #define ESP_FLAG_USE_FIFO 0x00000040
492 #define ESP_FLAG_NO_DMA_MAP 0x00000080
493
494 u8 select_state;
495 #define ESP_SELECT_NONE 0x00 /* Not selecting */
496 #define ESP_SELECT_BASIC 0x01 /* Select w/o MSGOUT phase */
497 #define ESP_SELECT_MSGOUT 0x02 /* Select with MSGOUT */
498
499 /* When we are not selecting, we are expecting an event. */
500 u8 event;
501 #define ESP_EVENT_NONE 0x00
502 #define ESP_EVENT_CMD_START 0x01
503 #define ESP_EVENT_CMD_DONE 0x02
504 #define ESP_EVENT_DATA_IN 0x03
505 #define ESP_EVENT_DATA_OUT 0x04
506 #define ESP_EVENT_DATA_DONE 0x05
507 #define ESP_EVENT_MSGIN 0x06
508 #define ESP_EVENT_MSGIN_MORE 0x07
509 #define ESP_EVENT_MSGIN_DONE 0x08
510 #define ESP_EVENT_MSGOUT 0x09
511 #define ESP_EVENT_MSGOUT_DONE 0x0a
512 #define ESP_EVENT_STATUS 0x0b
513 #define ESP_EVENT_FREE_BUS 0x0c
514 #define ESP_EVENT_CHECK_PHASE 0x0d
515 #define ESP_EVENT_RESET 0x10
516
517 /* Probed in esp_get_clock_params() */
518 u32 cfact;
519 u32 cfreq;
520 u32 ccycle;
521 u32 ctick;
522 u32 neg_defp;
523 u32 sync_defp;
524
525 /* Computed in esp_reset_esp() */
526 u32 max_period;
527 u32 min_period;
528 u32 radelay;
529
530 /* ESP_CMD_SELAS command state */
531 u8 *cmd_bytes_ptr;
532 int cmd_bytes_left;
533
534 struct completion *eh_reset;
535
536 void *dma;
537 int dmarev;
538
539 /* These are used by esp_send_pio_cmd() */
540 u8 __iomem *fifo_reg;
541 int send_cmd_error;
542 u32 send_cmd_residual;
543 };
544
545 /* A front-end driver for the ESP chip should do the following in
546 * it's device probe routine:
547 * 1) Allocate the host and private area using scsi_host_alloc()
548 * with size 'sizeof(struct esp)'. The first argument to
549 * scsi_host_alloc() should be &scsi_esp_template.
550 * 2) Set host->max_id as appropriate.
551 * 3) Set esp->host to the scsi_host itself, and esp->dev
552 * to the device object pointer.
553 * 4) Hook up esp->ops to the front-end implementation.
554 * 5) If the ESP chip supports wide transfers, set ESP_FLAG_WIDE_CAPABLE
555 * in esp->flags.
556 * 6) Map the DMA and ESP chip registers.
557 * 7) DMA map the ESP command block, store the DMA address
558 * in esp->command_block_dma.
559 * 8) Register the scsi_esp_intr() interrupt handler.
560 * 9) Probe for and provide the following chip properties:
561 * esp->scsi_id (assign to esp->host->this_id too)
562 * esp->scsi_id_mask
563 * If ESP bus is differential, set ESP_FLAG_DIFFERENTIAL
564 * esp->cfreq
565 * DMA burst bit mask in esp->bursts, if necessary
566 * 10) Perform any actions necessary before the ESP device can
567 * be programmed for the first time. On some configs, for
568 * example, the DMA engine has to be reset before ESP can
569 * be programmed.
570 * 11) If necessary, call dev_set_drvdata() as needed.
571 * 12) Call scsi_esp_register() with prepared 'esp' structure.
572 * 13) Check scsi_esp_register() return value, release all resources
573 * if an error was returned.
574 */
575 extern const struct scsi_host_template scsi_esp_template;
576 extern int scsi_esp_register(struct esp *);
577
578 extern void scsi_esp_unregister(struct esp *);
579 extern irqreturn_t scsi_esp_intr(int, void *);
580 extern void scsi_esp_cmd(struct esp *, u8);
581
582 extern void esp_send_pio_cmd(struct esp *esp, u32 dma_addr, u32 esp_count,
583 u32 dma_count, int write, u8 cmd);
584
585 #endif /* !(_ESP_SCSI_H) */
Kernel DRM miscellaneous fixes and cross-tree changes