drm/tests: hdmi: Fix memory leaks in drm_display_mode_from_cea_vic()
[drm/drm-misc.git] / drivers / scsi / fnic / cq_desc.h
blob0eb4ba277264a85f1977eab02f2d934387b467eb
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright 2008 Cisco Systems, Inc. All rights reserved.
4 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
5 */
6 #ifndef _CQ_DESC_H_
7 #define _CQ_DESC_H_
9 /*
10 * Completion queue descriptor types
12 enum cq_desc_types {
13 CQ_DESC_TYPE_WQ_ENET = 0,
14 CQ_DESC_TYPE_DESC_COPY = 1,
15 CQ_DESC_TYPE_WQ_EXCH = 2,
16 CQ_DESC_TYPE_RQ_ENET = 3,
17 CQ_DESC_TYPE_RQ_FCP = 4,
20 /* Completion queue descriptor: 16B
22 * All completion queues have this basic layout. The
23 * type_specfic area is unique for each completion
24 * queue type.
26 struct cq_desc {
27 __le16 completed_index;
28 __le16 q_number;
29 u8 type_specfic[11];
30 u8 type_color;
33 #define CQ_DESC_TYPE_BITS 4
34 #define CQ_DESC_TYPE_MASK ((1 << CQ_DESC_TYPE_BITS) - 1)
35 #define CQ_DESC_COLOR_MASK 1
36 #define CQ_DESC_COLOR_SHIFT 7
37 #define CQ_DESC_Q_NUM_BITS 10
38 #define CQ_DESC_Q_NUM_MASK ((1 << CQ_DESC_Q_NUM_BITS) - 1)
39 #define CQ_DESC_COMP_NDX_BITS 12
40 #define CQ_DESC_COMP_NDX_MASK ((1 << CQ_DESC_COMP_NDX_BITS) - 1)
42 static inline void cq_desc_dec(const struct cq_desc *desc_arg,
43 u8 *type, u8 *color, u16 *q_number, u16 *completed_index)
45 const struct cq_desc *desc = desc_arg;
46 const u8 type_color = desc->type_color;
48 *color = (type_color >> CQ_DESC_COLOR_SHIFT) & CQ_DESC_COLOR_MASK;
51 * Make sure color bit is read from desc *before* other fields
52 * are read from desc. Hardware guarantees color bit is last
53 * bit (byte) written. Adding the rmb() prevents the compiler
54 * and/or CPU from reordering the reads which would potentially
55 * result in reading stale values.
58 rmb();
60 *type = type_color & CQ_DESC_TYPE_MASK;
61 *q_number = le16_to_cpu(desc->q_number) & CQ_DESC_Q_NUM_MASK;
62 *completed_index = le16_to_cpu(desc->completed_index) &
63 CQ_DESC_COMP_NDX_MASK;
66 #endif /* _CQ_DESC_H_ */