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drm/tests: hdmi: Fix memory leaks in drm_display_mode_from_cea_vic()
[drm/drm-misc.git] / drivers / scsi / qla2xxx / qla_mr.c
blob82a7e21ddc8384cd2810211eba66805a2c362891
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
5 */
6 #include "qla_def.h"
7 #include <linux/delay.h>
8 #include <linux/ktime.h>
9 #include <linux/pci.h>
10 #include <linux/ratelimit.h>
11 #include <linux/vmalloc.h>
12 #include <scsi/scsi_tcq.h>
13 #include <linux/utsname.h>
14
15
16 /* QLAFX00 specific Mailbox implementation functions */
17
18 /*
19 * qlafx00_mailbox_command
20 * Issue mailbox command and waits for completion.
21 *
22 * Input:
23 * ha = adapter block pointer.
24 * mcp = driver internal mbx struct pointer.
25 *
26 * Output:
27 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
28 *
29 * Returns:
30 * 0 : QLA_SUCCESS = cmd performed success
31 * 1 : QLA_FUNCTION_FAILED (error encountered)
32 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
33 *
34 * Context:
35 * Kernel context.
36 */
37 static int
38 qlafx00_mailbox_command(scsi_qla_host_t *vha, struct mbx_cmd_32 *mcp)
39
40 {
41 int rval;
42 unsigned long flags = 0;
43 device_reg_t *reg;
44 uint8_t abort_active;
45 uint8_t io_lock_on;
46 uint16_t command = 0;
47 uint32_t *iptr;
48 __le32 __iomem *optr;
49 uint32_t cnt;
50 uint32_t mboxes;
51 unsigned long wait_time;
52 struct qla_hw_data *ha = vha->hw;
53 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
54
55 if (ha->pdev->error_state == pci_channel_io_perm_failure) {
56 ql_log(ql_log_warn, vha, 0x115c,
57 "PCI channel failed permanently, exiting.\n");
58 return QLA_FUNCTION_TIMEOUT;
59 }
60
61 if (vha->device_flags & DFLG_DEV_FAILED) {
62 ql_log(ql_log_warn, vha, 0x115f,
63 "Device in failed state, exiting.\n");
64 return QLA_FUNCTION_TIMEOUT;
65 }
66
67 reg = ha->iobase;
68 io_lock_on = base_vha->flags.init_done;
69
70 rval = QLA_SUCCESS;
71 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
72
73 if (ha->flags.pci_channel_io_perm_failure) {
74 ql_log(ql_log_warn, vha, 0x1175,
75 "Perm failure on EEH timeout MBX, exiting.\n");
76 return QLA_FUNCTION_TIMEOUT;
77 }
78
79 if (ha->flags.isp82xx_fw_hung) {
80 /* Setting Link-Down error */
81 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
82 ql_log(ql_log_warn, vha, 0x1176,
83 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
84 rval = QLA_FUNCTION_FAILED;
85 goto premature_exit;
86 }
87
88 /*
89 * Wait for active mailbox commands to finish by waiting at most tov
90 * seconds. This is to serialize actual issuing of mailbox cmds during
91 * non ISP abort time.
92 */
93 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
94 /* Timeout occurred. Return error. */
95 ql_log(ql_log_warn, vha, 0x1177,
96 "Cmd access timeout, cmd=0x%x, Exiting.\n",
97 mcp->mb[0]);
98 return QLA_FUNCTION_TIMEOUT;
99 }
100
101 ha->flags.mbox_busy = 1;
102 /* Save mailbox command for debug */
103 ha->mcp32 = mcp;
104
105 ql_dbg(ql_dbg_mbx, vha, 0x1178,
106 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
107
108 spin_lock_irqsave(&ha->hardware_lock, flags);
109
110 /* Load mailbox registers. */
111 optr = &reg->ispfx00.mailbox0;
112
113 iptr = mcp->mb;
114 command = mcp->mb[0];
115 mboxes = mcp->out_mb;
116
117 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
118 if (mboxes & BIT_0)
119 wrt_reg_dword(optr, *iptr);
120
121 mboxes >>= 1;
122 optr++;
123 iptr++;
124 }
125
126 /* Issue set host interrupt command to send cmd out. */
127 ha->flags.mbox_int = 0;
128 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
129
130 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1172,
131 (uint8_t *)mcp->mb, 16);
132 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1173,
133 ((uint8_t *)mcp->mb + 0x10), 16);
134 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1174,
135 ((uint8_t *)mcp->mb + 0x20), 8);
136
137 /* Unlock mbx registers and wait for interrupt */
138 ql_dbg(ql_dbg_mbx, vha, 0x1179,
139 "Going to unlock irq & waiting for interrupts. "
140 "jiffies=%lx.\n", jiffies);
141
142 /* Wait for mbx cmd completion until timeout */
143 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
144 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
145
146 QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
147 spin_unlock_irqrestore(&ha->hardware_lock, flags);
148
149 WARN_ON_ONCE(wait_for_completion_timeout(&ha->mbx_intr_comp,
150 mcp->tov * HZ) != 0);
151 } else {
152 ql_dbg(ql_dbg_mbx, vha, 0x112c,
153 "Cmd=%x Polling Mode.\n", command);
154
155 QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
156 spin_unlock_irqrestore(&ha->hardware_lock, flags);
157
158 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
159 while (!ha->flags.mbox_int) {
160 if (time_after(jiffies, wait_time))
161 break;
162
163 /* Check for pending interrupts. */
164 qla2x00_poll(ha->rsp_q_map[0]);
165
166 if (!ha->flags.mbox_int &&
167 !(IS_QLA2200(ha) &&
168 command == MBC_LOAD_RISC_RAM_EXTENDED))
169 usleep_range(10000, 11000);
170 } /* while */
171 ql_dbg(ql_dbg_mbx, vha, 0x112d,
172 "Waited %d sec.\n",
173 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
174 }
175
176 /* Check whether we timed out */
177 if (ha->flags.mbox_int) {
178 uint32_t *iptr2;
179
180 ql_dbg(ql_dbg_mbx, vha, 0x112e,
181 "Cmd=%x completed.\n", command);
182
183 /* Got interrupt. Clear the flag. */
184 ha->flags.mbox_int = 0;
185 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
186
187 if (ha->mailbox_out32[0] != MBS_COMMAND_COMPLETE)
188 rval = QLA_FUNCTION_FAILED;
189
190 /* Load return mailbox registers. */
191 iptr2 = mcp->mb;
192 iptr = (uint32_t *)&ha->mailbox_out32[0];
193 mboxes = mcp->in_mb;
194 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
195 if (mboxes & BIT_0)
196 *iptr2 = *iptr;
197
198 mboxes >>= 1;
199 iptr2++;
200 iptr++;
201 }
202 } else {
203
204 rval = QLA_FUNCTION_TIMEOUT;
205 }
206
207 ha->flags.mbox_busy = 0;
208
209 /* Clean up */
210 ha->mcp32 = NULL;
211
212 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
213 ql_dbg(ql_dbg_mbx, vha, 0x113a,
214 "checking for additional resp interrupt.\n");
215
216 /* polling mode for non isp_abort commands. */
217 qla2x00_poll(ha->rsp_q_map[0]);
218 }
219
220 if (rval == QLA_FUNCTION_TIMEOUT &&
221 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
222 if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
223 ha->flags.eeh_busy) {
224 /* not in dpc. schedule it for dpc to take over. */
225 ql_dbg(ql_dbg_mbx, vha, 0x115d,
226 "Timeout, schedule isp_abort_needed.\n");
227
228 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
229 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
230 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
231
232 ql_log(ql_log_info, base_vha, 0x115e,
233 "Mailbox cmd timeout occurred, cmd=0x%x, "
234 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
235 "abort.\n", command, mcp->mb[0],
236 ha->flags.eeh_busy);
237 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
238 qla2xxx_wake_dpc(vha);
239 }
240 } else if (!abort_active) {
241 /* call abort directly since we are in the DPC thread */
242 ql_dbg(ql_dbg_mbx, vha, 0x1160,
243 "Timeout, calling abort_isp.\n");
244
245 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
246 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
247 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
248
249 ql_log(ql_log_info, base_vha, 0x1161,
250 "Mailbox cmd timeout occurred, cmd=0x%x, "
251 "mb[0]=0x%x. Scheduling ISP abort ",
252 command, mcp->mb[0]);
253
254 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
255 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
256 if (ha->isp_ops->abort_isp(vha)) {
257 /* Failed. retry later. */
258 set_bit(ISP_ABORT_NEEDED,
259 &vha->dpc_flags);
260 }
261 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
262 ql_dbg(ql_dbg_mbx, vha, 0x1162,
263 "Finished abort_isp.\n");
264 }
265 }
266 }
267
268 premature_exit:
269 /* Allow next mbx cmd to come in. */
270 complete(&ha->mbx_cmd_comp);
271
272 if (rval) {
273 ql_log(ql_log_warn, base_vha, 0x1163,
274 "**** Failed=%x mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n",
275 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
276 command);
277 } else {
278 ql_dbg(ql_dbg_mbx, base_vha, 0x1164, "Done %s.\n", __func__);
279 }
280
281 return rval;
282 }
283
284 /*
285 * qlafx00_driver_shutdown
286 * Indicate a driver shutdown to firmware.
287 *
288 * Input:
289 * ha = adapter block pointer.
290 *
291 * Returns:
292 * local function return status code.
293 *
294 * Context:
295 * Kernel context.
296 */
297 int
298 qlafx00_driver_shutdown(scsi_qla_host_t *vha, int tmo)
299 {
300 int rval;
301 struct mbx_cmd_32 mc;
302 struct mbx_cmd_32 *mcp = &mc;
303
304 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1166,
305 "Entered %s.\n", __func__);
306
307 mcp->mb[0] = MBC_MR_DRV_SHUTDOWN;
308 mcp->out_mb = MBX_0;
309 mcp->in_mb = MBX_0;
310 if (tmo)
311 mcp->tov = tmo;
312 else
313 mcp->tov = MBX_TOV_SECONDS;
314 mcp->flags = 0;
315 rval = qlafx00_mailbox_command(vha, mcp);
316
317 if (rval != QLA_SUCCESS) {
318 ql_dbg(ql_dbg_mbx, vha, 0x1167,
319 "Failed=%x.\n", rval);
320 } else {
321 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1168,
322 "Done %s.\n", __func__);
323 }
324
325 return rval;
326 }
327
328 /*
329 * qlafx00_get_firmware_state
330 * Get adapter firmware state.
331 *
332 * Input:
333 * ha = adapter block pointer.
334 * TARGET_QUEUE_LOCK must be released.
335 * ADAPTER_STATE_LOCK must be released.
336 *
337 * Returns:
338 * qla7xxx local function return status code.
339 *
340 * Context:
341 * Kernel context.
342 */
343 static int
344 qlafx00_get_firmware_state(scsi_qla_host_t *vha, uint32_t *states)
345 {
346 int rval;
347 struct mbx_cmd_32 mc;
348 struct mbx_cmd_32 *mcp = &mc;
349
350 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1169,
351 "Entered %s.\n", __func__);
352
353 mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
354 mcp->out_mb = MBX_0;
355 mcp->in_mb = MBX_1|MBX_0;
356 mcp->tov = MBX_TOV_SECONDS;
357 mcp->flags = 0;
358 rval = qlafx00_mailbox_command(vha, mcp);
359
360 /* Return firmware states. */
361 states[0] = mcp->mb[1];
362
363 if (rval != QLA_SUCCESS) {
364 ql_dbg(ql_dbg_mbx, vha, 0x116a,
365 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
366 } else {
367 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116b,
368 "Done %s.\n", __func__);
369 }
370 return rval;
371 }
372
373 /*
374 * qlafx00_init_firmware
375 * Initialize adapter firmware.
376 *
377 * Input:
378 * ha = adapter block pointer.
379 * dptr = Initialization control block pointer.
380 * size = size of initialization control block.
381 * TARGET_QUEUE_LOCK must be released.
382 * ADAPTER_STATE_LOCK must be released.
383 *
384 * Returns:
385 * qlafx00 local function return status code.
386 *
387 * Context:
388 * Kernel context.
389 */
390 int
391 qlafx00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
392 {
393 int rval;
394 struct mbx_cmd_32 mc;
395 struct mbx_cmd_32 *mcp = &mc;
396 struct qla_hw_data *ha = vha->hw;
397
398 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116c,
399 "Entered %s.\n", __func__);
400
401 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
402
403 mcp->mb[1] = 0;
404 mcp->mb[2] = MSD(ha->init_cb_dma);
405 mcp->mb[3] = LSD(ha->init_cb_dma);
406
407 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
408 mcp->in_mb = MBX_0;
409 mcp->buf_size = size;
410 mcp->flags = MBX_DMA_OUT;
411 mcp->tov = MBX_TOV_SECONDS;
412 rval = qlafx00_mailbox_command(vha, mcp);
413
414 if (rval != QLA_SUCCESS) {
415 ql_dbg(ql_dbg_mbx, vha, 0x116d,
416 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
417 } else {
418 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116e,
419 "Done %s.\n", __func__);
420 }
421 return rval;
422 }
423
424 /*
425 * qlafx00_mbx_reg_test
426 */
427 static int
428 qlafx00_mbx_reg_test(scsi_qla_host_t *vha)
429 {
430 int rval;
431 struct mbx_cmd_32 mc;
432 struct mbx_cmd_32 *mcp = &mc;
433
434 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116f,
435 "Entered %s.\n", __func__);
436
437
438 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
439 mcp->mb[1] = 0xAAAA;
440 mcp->mb[2] = 0x5555;
441 mcp->mb[3] = 0xAA55;
442 mcp->mb[4] = 0x55AA;
443 mcp->mb[5] = 0xA5A5;
444 mcp->mb[6] = 0x5A5A;
445 mcp->mb[7] = 0x2525;
446 mcp->mb[8] = 0xBBBB;
447 mcp->mb[9] = 0x6666;
448 mcp->mb[10] = 0xBB66;
449 mcp->mb[11] = 0x66BB;
450 mcp->mb[12] = 0xB6B6;
451 mcp->mb[13] = 0x6B6B;
452 mcp->mb[14] = 0x3636;
453 mcp->mb[15] = 0xCCCC;
454
455
456 mcp->out_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
457 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
458 mcp->in_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
459 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
460 mcp->buf_size = 0;
461 mcp->flags = MBX_DMA_OUT;
462 mcp->tov = MBX_TOV_SECONDS;
463 rval = qlafx00_mailbox_command(vha, mcp);
464 if (rval == QLA_SUCCESS) {
465 if (mcp->mb[17] != 0xAAAA || mcp->mb[18] != 0x5555 ||
466 mcp->mb[19] != 0xAA55 || mcp->mb[20] != 0x55AA)
467 rval = QLA_FUNCTION_FAILED;
468 if (mcp->mb[21] != 0xA5A5 || mcp->mb[22] != 0x5A5A ||
469 mcp->mb[23] != 0x2525 || mcp->mb[24] != 0xBBBB)
470 rval = QLA_FUNCTION_FAILED;
471 if (mcp->mb[25] != 0x6666 || mcp->mb[26] != 0xBB66 ||
472 mcp->mb[27] != 0x66BB || mcp->mb[28] != 0xB6B6)
473 rval = QLA_FUNCTION_FAILED;
474 if (mcp->mb[29] != 0x6B6B || mcp->mb[30] != 0x3636 ||
475 mcp->mb[31] != 0xCCCC)
476 rval = QLA_FUNCTION_FAILED;
477 }
478
479 if (rval != QLA_SUCCESS) {
480 ql_dbg(ql_dbg_mbx, vha, 0x1170,
481 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
482 } else {
483 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1171,
484 "Done %s.\n", __func__);
485 }
486 return rval;
487 }
488
489 /**
490 * qlafx00_pci_config() - Setup ISPFx00 PCI configuration registers.
491 * @vha: HA context
492 *
493 * Returns 0 on success.
494 */
495 int
496 qlafx00_pci_config(scsi_qla_host_t *vha)
497 {
498 uint16_t w;
499 struct qla_hw_data *ha = vha->hw;
500
501 pci_set_master(ha->pdev);
502 pci_try_set_mwi(ha->pdev);
503
504 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
505 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
506 w &= ~PCI_COMMAND_INTX_DISABLE;
507 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
508
509 /* PCIe -- adjust Maximum Read Request Size (2048). */
510 if (pci_is_pcie(ha->pdev))
511 pcie_set_readrq(ha->pdev, 2048);
512
513 ha->chip_revision = ha->pdev->revision;
514
515 return QLA_SUCCESS;
516 }
517
518 /**
519 * qlafx00_soc_cpu_reset() - Perform warm reset of iSA(CPUs being reset on SOC).
520 * @vha: HA context
521 *
522 */
523 static inline void
524 qlafx00_soc_cpu_reset(scsi_qla_host_t *vha)
525 {
526 unsigned long flags = 0;
527 struct qla_hw_data *ha = vha->hw;
528 int i, core;
529 uint32_t cnt;
530 uint32_t reg_val;
531
532 spin_lock_irqsave(&ha->hardware_lock, flags);
533
534 QLAFX00_SET_HBA_SOC_REG(ha, 0x80004, 0);
535 QLAFX00_SET_HBA_SOC_REG(ha, 0x82004, 0);
536
537 /* stop the XOR DMA engines */
538 QLAFX00_SET_HBA_SOC_REG(ha, 0x60920, 0x02);
539 QLAFX00_SET_HBA_SOC_REG(ha, 0x60924, 0x02);
540 QLAFX00_SET_HBA_SOC_REG(ha, 0xf0920, 0x02);
541 QLAFX00_SET_HBA_SOC_REG(ha, 0xf0924, 0x02);
542
543 /* stop the IDMA engines */
544 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60840);
545 reg_val &= ~(1<<12);
546 QLAFX00_SET_HBA_SOC_REG(ha, 0x60840, reg_val);
547
548 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60844);
549 reg_val &= ~(1<<12);
550 QLAFX00_SET_HBA_SOC_REG(ha, 0x60844, reg_val);
551
552 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60848);
553 reg_val &= ~(1<<12);
554 QLAFX00_SET_HBA_SOC_REG(ha, 0x60848, reg_val);
555
556 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x6084C);
557 reg_val &= ~(1<<12);
558 QLAFX00_SET_HBA_SOC_REG(ha, 0x6084C, reg_val);
559
560 for (i = 0; i < 100000; i++) {
561 if ((QLAFX00_GET_HBA_SOC_REG(ha, 0xd0000) & 0x10000000) == 0 &&
562 (QLAFX00_GET_HBA_SOC_REG(ha, 0x10600) & 0x1) == 0)
563 break;
564 udelay(100);
565 }
566
567 /* Set all 4 cores in reset */
568 for (i = 0; i < 4; i++) {
569 QLAFX00_SET_HBA_SOC_REG(ha,
570 (SOC_SW_RST_CONTROL_REG_CORE0 + 8*i), (0xF01));
571 QLAFX00_SET_HBA_SOC_REG(ha,
572 (SOC_SW_RST_CONTROL_REG_CORE0 + 4 + 8*i), (0x01010101));
573 }
574
575 /* Reset all units in Fabric */
576 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x011f0101));
577
578 /* */
579 QLAFX00_SET_HBA_SOC_REG(ha, 0x10610, 1);
580 QLAFX00_SET_HBA_SOC_REG(ha, 0x10600, 0);
581
582 /* Set all 4 core Memory Power Down Registers */
583 for (i = 0; i < 5; i++) {
584 QLAFX00_SET_HBA_SOC_REG(ha,
585 (SOC_PWR_MANAGEMENT_PWR_DOWN_REG + 4*i), (0x0));
586 }
587
588 /* Reset all interrupt control registers */
589 for (i = 0; i < 115; i++) {
590 QLAFX00_SET_HBA_SOC_REG(ha,
591 (SOC_INTERRUPT_SOURCE_I_CONTROL_REG + 4*i), (0x0));
592 }
593
594 /* Reset Timers control registers. per core */
595 for (core = 0; core < 4; core++)
596 for (i = 0; i < 8; i++)
597 QLAFX00_SET_HBA_SOC_REG(ha,
598 (SOC_CORE_TIMER_REG + 0x100*core + 4*i), (0x0));
599
600 /* Reset per core IRQ ack register */
601 for (core = 0; core < 4; core++)
602 QLAFX00_SET_HBA_SOC_REG(ha,
603 (SOC_IRQ_ACK_REG + 0x100*core), (0x3FF));
604
605 /* Set Fabric control and config to defaults */
606 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONTROL_REG, (0x2));
607 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONFIG_REG, (0x3));
608
609 /* Kick in Fabric units */
610 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x0));
611
612 /* Kick in Core0 to start boot process */
613 QLAFX00_SET_HBA_SOC_REG(ha, SOC_SW_RST_CONTROL_REG_CORE0, (0xF00));
614
615 spin_unlock_irqrestore(&ha->hardware_lock, flags);
616
617 /* Wait 10secs for soft-reset to complete. */
618 for (cnt = 10; cnt; cnt--) {
619 msleep(1000);
620 barrier();
621 }
622 }
623
624 /**
625 * qlafx00_soft_reset() - Soft Reset ISPFx00.
626 * @vha: HA context
627 *
628 * Returns 0 on success.
629 */
630 int
631 qlafx00_soft_reset(scsi_qla_host_t *vha)
632 {
633 struct qla_hw_data *ha = vha->hw;
634 int rval = QLA_FUNCTION_FAILED;
635
636 if (unlikely(pci_channel_offline(ha->pdev) &&
637 ha->flags.pci_channel_io_perm_failure))
638 return rval;
639
640 ha->isp_ops->disable_intrs(ha);
641 qlafx00_soc_cpu_reset(vha);
642
643 return QLA_SUCCESS;
644 }
645
646 /**
647 * qlafx00_chip_diag() - Test ISPFx00 for proper operation.
648 * @vha: HA context
649 *
650 * Returns 0 on success.
651 */
652 int
653 qlafx00_chip_diag(scsi_qla_host_t *vha)
654 {
655 int rval = 0;
656 struct qla_hw_data *ha = vha->hw;
657 struct req_que *req = ha->req_q_map[0];
658
659 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
660
661 rval = qlafx00_mbx_reg_test(vha);
662 if (rval) {
663 ql_log(ql_log_warn, vha, 0x1165,
664 "Failed mailbox send register test\n");
665 } else {
666 /* Flag a successful rval */
667 rval = QLA_SUCCESS;
668 }
669 return rval;
670 }
671
672 void
673 qlafx00_config_rings(struct scsi_qla_host *vha)
674 {
675 struct qla_hw_data *ha = vha->hw;
676 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
677
678 wrt_reg_dword(&reg->req_q_in, 0);
679 wrt_reg_dword(&reg->req_q_out, 0);
680
681 wrt_reg_dword(&reg->rsp_q_in, 0);
682 wrt_reg_dword(&reg->rsp_q_out, 0);
683
684 /* PCI posting */
685 rd_reg_dword(&reg->rsp_q_out);
686 }
687
688 char *
689 qlafx00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
690 {
691 struct qla_hw_data *ha = vha->hw;
692
693 if (pci_is_pcie(ha->pdev))
694 strscpy(str, "PCIe iSA", str_len);
695 return str;
696 }
697
698 char *
699 qlafx00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
700 {
701 struct qla_hw_data *ha = vha->hw;
702
703 snprintf(str, size, "%s", ha->mr.fw_version);
704 return str;
705 }
706
707 void
708 qlafx00_enable_intrs(struct qla_hw_data *ha)
709 {
710 unsigned long flags = 0;
711
712 spin_lock_irqsave(&ha->hardware_lock, flags);
713 ha->interrupts_on = 1;
714 QLAFX00_ENABLE_ICNTRL_REG(ha);
715 spin_unlock_irqrestore(&ha->hardware_lock, flags);
716 }
717
718 void
719 qlafx00_disable_intrs(struct qla_hw_data *ha)
720 {
721 unsigned long flags = 0;
722
723 spin_lock_irqsave(&ha->hardware_lock, flags);
724 ha->interrupts_on = 0;
725 QLAFX00_DISABLE_ICNTRL_REG(ha);
726 spin_unlock_irqrestore(&ha->hardware_lock, flags);
727 }
728
729 int
730 qlafx00_abort_target(fc_port_t *fcport, uint64_t l, int tag)
731 {
732 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
733 }
734
735 int
736 qlafx00_lun_reset(fc_port_t *fcport, uint64_t l, int tag)
737 {
738 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
739 }
740
741 int
742 qlafx00_iospace_config(struct qla_hw_data *ha)
743 {
744 if (pci_request_selected_regions(ha->pdev, ha->bars,
745 QLA2XXX_DRIVER_NAME)) {
746 ql_log_pci(ql_log_fatal, ha->pdev, 0x014e,
747 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
748 pci_name(ha->pdev));
749 goto iospace_error_exit;
750 }
751
752 /* Use MMIO operations for all accesses. */
753 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
754 ql_log_pci(ql_log_warn, ha->pdev, 0x014f,
755 "Invalid pci I/O region size (%s).\n",
756 pci_name(ha->pdev));
757 goto iospace_error_exit;
758 }
759 if (pci_resource_len(ha->pdev, 0) < BAR0_LEN_FX00) {
760 ql_log_pci(ql_log_warn, ha->pdev, 0x0127,
761 "Invalid PCI mem BAR0 region size (%s), aborting\n",
762 pci_name(ha->pdev));
763 goto iospace_error_exit;
764 }
765
766 ha->cregbase =
767 ioremap(pci_resource_start(ha->pdev, 0), BAR0_LEN_FX00);
768 if (!ha->cregbase) {
769 ql_log_pci(ql_log_fatal, ha->pdev, 0x0128,
770 "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
771 goto iospace_error_exit;
772 }
773
774 if (!(pci_resource_flags(ha->pdev, 2) & IORESOURCE_MEM)) {
775 ql_log_pci(ql_log_warn, ha->pdev, 0x0129,
776 "region #2 not an MMIO resource (%s), aborting\n",
777 pci_name(ha->pdev));
778 goto iospace_error_exit;
779 }
780 if (pci_resource_len(ha->pdev, 2) < BAR2_LEN_FX00) {
781 ql_log_pci(ql_log_warn, ha->pdev, 0x012a,
782 "Invalid PCI mem BAR2 region size (%s), aborting\n",
783 pci_name(ha->pdev));
784 goto iospace_error_exit;
785 }
786
787 ha->iobase =
788 ioremap(pci_resource_start(ha->pdev, 2), BAR2_LEN_FX00);
789 if (!ha->iobase) {
790 ql_log_pci(ql_log_fatal, ha->pdev, 0x012b,
791 "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
792 goto iospace_error_exit;
793 }
794
795 /* Determine queue resources */
796 ha->max_req_queues = ha->max_rsp_queues = 1;
797
798 ql_log_pci(ql_log_info, ha->pdev, 0x012c,
799 "Bars 0x%x, iobase0 0x%p, iobase2 0x%p\n",
800 ha->bars, ha->cregbase, ha->iobase);
801
802 return 0;
803
804 iospace_error_exit:
805 return -ENOMEM;
806 }
807
808 static void
809 qlafx00_save_queue_ptrs(struct scsi_qla_host *vha)
810 {
811 struct qla_hw_data *ha = vha->hw;
812 struct req_que *req = ha->req_q_map[0];
813 struct rsp_que *rsp = ha->rsp_q_map[0];
814
815 req->length_fx00 = req->length;
816 req->ring_fx00 = req->ring;
817 req->dma_fx00 = req->dma;
818
819 rsp->length_fx00 = rsp->length;
820 rsp->ring_fx00 = rsp->ring;
821 rsp->dma_fx00 = rsp->dma;
822
823 ql_dbg(ql_dbg_init, vha, 0x012d,
824 "req: %p, ring_fx00: %p, length_fx00: 0x%x,"
825 "req->dma_fx00: 0x%llx\n", req, req->ring_fx00,
826 req->length_fx00, (u64)req->dma_fx00);
827
828 ql_dbg(ql_dbg_init, vha, 0x012e,
829 "rsp: %p, ring_fx00: %p, length_fx00: 0x%x,"
830 "rsp->dma_fx00: 0x%llx\n", rsp, rsp->ring_fx00,
831 rsp->length_fx00, (u64)rsp->dma_fx00);
832 }
833
834 static int
835 qlafx00_config_queues(struct scsi_qla_host *vha)
836 {
837 struct qla_hw_data *ha = vha->hw;
838 struct req_que *req = ha->req_q_map[0];
839 struct rsp_que *rsp = ha->rsp_q_map[0];
840 dma_addr_t bar2_hdl = pci_resource_start(ha->pdev, 2);
841
842 req->length = ha->req_que_len;
843 req->ring = (void __force *)ha->iobase + ha->req_que_off;
844 req->dma = bar2_hdl + ha->req_que_off;
845 if ((!req->ring) || (req->length == 0)) {
846 ql_log_pci(ql_log_info, ha->pdev, 0x012f,
847 "Unable to allocate memory for req_ring\n");
848 return QLA_FUNCTION_FAILED;
849 }
850
851 ql_dbg(ql_dbg_init, vha, 0x0130,
852 "req: %p req_ring pointer %p req len 0x%x "
853 "req off 0x%x\n, req->dma: 0x%llx",
854 req, req->ring, req->length,
855 ha->req_que_off, (u64)req->dma);
856
857 rsp->length = ha->rsp_que_len;
858 rsp->ring = (void __force *)ha->iobase + ha->rsp_que_off;
859 rsp->dma = bar2_hdl + ha->rsp_que_off;
860 if ((!rsp->ring) || (rsp->length == 0)) {
861 ql_log_pci(ql_log_info, ha->pdev, 0x0131,
862 "Unable to allocate memory for rsp_ring\n");
863 return QLA_FUNCTION_FAILED;
864 }
865
866 ql_dbg(ql_dbg_init, vha, 0x0132,
867 "rsp: %p rsp_ring pointer %p rsp len 0x%x "
868 "rsp off 0x%x, rsp->dma: 0x%llx\n",
869 rsp, rsp->ring, rsp->length,
870 ha->rsp_que_off, (u64)rsp->dma);
871
872 return QLA_SUCCESS;
873 }
874
875 static int
876 qlafx00_init_fw_ready(scsi_qla_host_t *vha)
877 {
878 int rval = 0;
879 unsigned long wtime;
880 uint16_t wait_time; /* Wait time */
881 struct qla_hw_data *ha = vha->hw;
882 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
883 uint32_t aenmbx, aenmbx7 = 0;
884 uint32_t pseudo_aen;
885 uint32_t state[5];
886 bool done = false;
887
888 /* 30 seconds wait - Adjust if required */
889 wait_time = 30;
890
891 pseudo_aen = rd_reg_dword(&reg->pseudoaen);
892 if (pseudo_aen == 1) {
893 aenmbx7 = rd_reg_dword(&reg->initval7);
894 ha->mbx_intr_code = MSW(aenmbx7);
895 ha->rqstq_intr_code = LSW(aenmbx7);
896 rval = qlafx00_driver_shutdown(vha, 10);
897 if (rval != QLA_SUCCESS)
898 qlafx00_soft_reset(vha);
899 }
900
901 /* wait time before firmware ready */
902 wtime = jiffies + (wait_time * HZ);
903 do {
904 aenmbx = rd_reg_dword(&reg->aenmailbox0);
905 barrier();
906 ql_dbg(ql_dbg_mbx, vha, 0x0133,
907 "aenmbx: 0x%x\n", aenmbx);
908
909 switch (aenmbx) {
910 case MBA_FW_NOT_STARTED:
911 case MBA_FW_STARTING:
912 break;
913
914 case MBA_SYSTEM_ERR:
915 case MBA_REQ_TRANSFER_ERR:
916 case MBA_RSP_TRANSFER_ERR:
917 case MBA_FW_INIT_FAILURE:
918 qlafx00_soft_reset(vha);
919 break;
920
921 case MBA_FW_RESTART_CMPLT:
922 /* Set the mbx and rqstq intr code */
923 aenmbx7 = rd_reg_dword(&reg->aenmailbox7);
924 ha->mbx_intr_code = MSW(aenmbx7);
925 ha->rqstq_intr_code = LSW(aenmbx7);
926 ha->req_que_off = rd_reg_dword(&reg->aenmailbox1);
927 ha->rsp_que_off = rd_reg_dword(&reg->aenmailbox3);
928 ha->req_que_len = rd_reg_dword(&reg->aenmailbox5);
929 ha->rsp_que_len = rd_reg_dword(&reg->aenmailbox6);
930 wrt_reg_dword(&reg->aenmailbox0, 0);
931 rd_reg_dword_relaxed(&reg->aenmailbox0);
932 ql_dbg(ql_dbg_init, vha, 0x0134,
933 "f/w returned mbx_intr_code: 0x%x, "
934 "rqstq_intr_code: 0x%x\n",
935 ha->mbx_intr_code, ha->rqstq_intr_code);
936 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
937 rval = QLA_SUCCESS;
938 done = true;
939 break;
940
941 default:
942 if ((aenmbx & 0xFF00) == MBA_FW_INIT_INPROGRESS)
943 break;
944
945 /* If fw is apparently not ready. In order to continue,
946 * we might need to issue Mbox cmd, but the problem is
947 * that the DoorBell vector values that come with the
948 * 8060 AEN are most likely gone by now (and thus no
949 * bell would be rung on the fw side when mbox cmd is
950 * issued). We have to therefore grab the 8060 AEN
951 * shadow regs (filled in by FW when the last 8060
952 * AEN was being posted).
953 * Do the following to determine what is needed in
954 * order to get the FW ready:
955 * 1. reload the 8060 AEN values from the shadow regs
956 * 2. clear int status to get rid of possible pending
957 * interrupts
958 * 3. issue Get FW State Mbox cmd to determine fw state
959 * Set the mbx and rqstq intr code from Shadow Regs
960 */
961 aenmbx7 = rd_reg_dword(&reg->initval7);
962 ha->mbx_intr_code = MSW(aenmbx7);
963 ha->rqstq_intr_code = LSW(aenmbx7);
964 ha->req_que_off = rd_reg_dword(&reg->initval1);
965 ha->rsp_que_off = rd_reg_dword(&reg->initval3);
966 ha->req_que_len = rd_reg_dword(&reg->initval5);
967 ha->rsp_que_len = rd_reg_dword(&reg->initval6);
968 ql_dbg(ql_dbg_init, vha, 0x0135,
969 "f/w returned mbx_intr_code: 0x%x, "
970 "rqstq_intr_code: 0x%x\n",
971 ha->mbx_intr_code, ha->rqstq_intr_code);
972 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
973
974 /* Get the FW state */
975 rval = qlafx00_get_firmware_state(vha, state);
976 if (rval != QLA_SUCCESS) {
977 /* Retry if timer has not expired */
978 break;
979 }
980
981 if (state[0] == FSTATE_FX00_CONFIG_WAIT) {
982 /* Firmware is waiting to be
983 * initialized by driver
984 */
985 rval = QLA_SUCCESS;
986 done = true;
987 break;
988 }
989
990 /* Issue driver shutdown and wait until f/w recovers.
991 * Driver should continue to poll until 8060 AEN is
992 * received indicating firmware recovery.
993 */
994 ql_dbg(ql_dbg_init, vha, 0x0136,
995 "Sending Driver shutdown fw_state 0x%x\n",
996 state[0]);
997
998 rval = qlafx00_driver_shutdown(vha, 10);
999 if (rval != QLA_SUCCESS) {
1000 rval = QLA_FUNCTION_FAILED;
1001 break;
1002 }
1003 msleep(500);
1004
1005 wtime = jiffies + (wait_time * HZ);
1006 break;
1007 }
1008
1009 if (!done) {
1010 if (time_after_eq(jiffies, wtime)) {
1011 ql_dbg(ql_dbg_init, vha, 0x0137,
1012 "Init f/w failed: aen[7]: 0x%x\n",
1013 rd_reg_dword(&reg->aenmailbox7));
1014 rval = QLA_FUNCTION_FAILED;
1015 done = true;
1016 break;
1017 }
1018 /* Delay for a while */
1019 msleep(500);
1020 }
1021 } while (!done);
1022
1023 if (rval)
1024 ql_dbg(ql_dbg_init, vha, 0x0138,
1025 "%s **** FAILED ****.\n", __func__);
1026 else
1027 ql_dbg(ql_dbg_init, vha, 0x0139,
1028 "%s **** SUCCESS ****.\n", __func__);
1029
1030 return rval;
1031 }
1032
1033 /*
1034 * qlafx00_fw_ready() - Waits for firmware ready.
1035 * @ha: HA context
1036 *
1037 * Returns 0 on success.
1038 */
1039 int
1040 qlafx00_fw_ready(scsi_qla_host_t *vha)
1041 {
1042 int rval;
1043 unsigned long wtime;
1044 uint16_t wait_time; /* Wait time if loop is coming ready */
1045 uint32_t state[5];
1046
1047 rval = QLA_SUCCESS;
1048
1049 wait_time = 10;
1050
1051 /* wait time before firmware ready */
1052 wtime = jiffies + (wait_time * HZ);
1053
1054 /* Wait for ISP to finish init */
1055 if (!vha->flags.init_done)
1056 ql_dbg(ql_dbg_init, vha, 0x013a,
1057 "Waiting for init to complete...\n");
1058
1059 do {
1060 rval = qlafx00_get_firmware_state(vha, state);
1061
1062 if (rval == QLA_SUCCESS) {
1063 if (state[0] == FSTATE_FX00_INITIALIZED) {
1064 ql_dbg(ql_dbg_init, vha, 0x013b,
1065 "fw_state=%x\n", state[0]);
1066 rval = QLA_SUCCESS;
1067 break;
1068 }
1069 }
1070 rval = QLA_FUNCTION_FAILED;
1071
1072 if (time_after_eq(jiffies, wtime))
1073 break;
1074
1075 /* Delay for a while */
1076 msleep(500);
1077
1078 ql_dbg(ql_dbg_init, vha, 0x013c,
1079 "fw_state=%x curr time=%lx.\n", state[0], jiffies);
1080 } while (1);
1081
1082
1083 if (rval)
1084 ql_dbg(ql_dbg_init, vha, 0x013d,
1085 "Firmware ready **** FAILED ****.\n");
1086 else
1087 ql_dbg(ql_dbg_init, vha, 0x013e,
1088 "Firmware ready **** SUCCESS ****.\n");
1089
1090 return rval;
1091 }
1092
1093 static int
1094 qlafx00_find_all_targets(scsi_qla_host_t *vha,
1095 struct list_head *new_fcports)
1096 {
1097 int rval;
1098 uint16_t tgt_id;
1099 fc_port_t *fcport, *new_fcport;
1100 int found;
1101 struct qla_hw_data *ha = vha->hw;
1102
1103 rval = QLA_SUCCESS;
1104
1105 if (!test_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags))
1106 return QLA_FUNCTION_FAILED;
1107
1108 if ((atomic_read(&vha->loop_down_timer) ||
1109 STATE_TRANSITION(vha))) {
1110 atomic_set(&vha->loop_down_timer, 0);
1111 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1112 return QLA_FUNCTION_FAILED;
1113 }
1114
1115 ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x2088,
1116 "Listing Target bit map...\n");
1117 ql_dump_buffer(ql_dbg_disc + ql_dbg_init, vha, 0x2089,
1118 ha->gid_list, 32);
1119
1120 /* Allocate temporary rmtport for any new rmtports discovered. */
1121 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1122 if (new_fcport == NULL)
1123 return QLA_MEMORY_ALLOC_FAILED;
1124
1125 for_each_set_bit(tgt_id, (void *)ha->gid_list,
1126 QLAFX00_TGT_NODE_LIST_SIZE) {
1127
1128 /* Send get target node info */
1129 new_fcport->tgt_id = tgt_id;
1130 rval = qlafx00_fx_disc(vha, new_fcport,
1131 FXDISC_GET_TGT_NODE_INFO);
1132 if (rval != QLA_SUCCESS) {
1133 ql_log(ql_log_warn, vha, 0x208a,
1134 "Target info scan failed -- assuming zero-entry "
1135 "result...\n");
1136 continue;
1137 }
1138
1139 /* Locate matching device in database. */
1140 found = 0;
1141 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1142 if (memcmp(new_fcport->port_name,
1143 fcport->port_name, WWN_SIZE))
1144 continue;
1145
1146 found++;
1147
1148 /*
1149 * If tgt_id is same and state FCS_ONLINE, nothing
1150 * changed.
1151 */
1152 if (fcport->tgt_id == new_fcport->tgt_id &&
1153 atomic_read(&fcport->state) == FCS_ONLINE)
1154 break;
1155
1156 /*
1157 * Tgt ID changed or device was marked to be updated.
1158 */
1159 ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x208b,
1160 "TGT-ID Change(%s): Present tgt id: "
1161 "0x%x state: 0x%x "
1162 "wwnn = %llx wwpn = %llx.\n",
1163 __func__, fcport->tgt_id,
1164 atomic_read(&fcport->state),
1165 (unsigned long long)wwn_to_u64(fcport->node_name),
1166 (unsigned long long)wwn_to_u64(fcport->port_name));
1167
1168 ql_log(ql_log_info, vha, 0x208c,
1169 "TGT-ID Announce(%s): Discovered tgt "
1170 "id 0x%x wwnn = %llx "
1171 "wwpn = %llx.\n", __func__, new_fcport->tgt_id,
1172 (unsigned long long)
1173 wwn_to_u64(new_fcport->node_name),
1174 (unsigned long long)
1175 wwn_to_u64(new_fcport->port_name));
1176
1177 if (atomic_read(&fcport->state) != FCS_ONLINE) {
1178 fcport->old_tgt_id = fcport->tgt_id;
1179 fcport->tgt_id = new_fcport->tgt_id;
1180 ql_log(ql_log_info, vha, 0x208d,
1181 "TGT-ID: New fcport Added: %p\n", fcport);
1182 qla2x00_update_fcport(vha, fcport);
1183 } else {
1184 ql_log(ql_log_info, vha, 0x208e,
1185 " Existing TGT-ID %x did not get "
1186 " offline event from firmware.\n",
1187 fcport->old_tgt_id);
1188 qla2x00_mark_device_lost(vha, fcport, 0);
1189 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1190 qla2x00_free_fcport(new_fcport);
1191 return rval;
1192 }
1193 break;
1194 }
1195
1196 if (found)
1197 continue;
1198
1199 /* If device was not in our fcports list, then add it. */
1200 list_add_tail(&new_fcport->list, new_fcports);
1201
1202 /* Allocate a new replacement fcport. */
1203 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1204 if (new_fcport == NULL)
1205 return QLA_MEMORY_ALLOC_FAILED;
1206 }
1207
1208 qla2x00_free_fcport(new_fcport);
1209 return rval;
1210 }
1211
1212 /*
1213 * qlafx00_configure_all_targets
1214 * Setup target devices with node ID's.
1215 *
1216 * Input:
1217 * ha = adapter block pointer.
1218 *
1219 * Returns:
1220 * 0 = success.
1221 * BIT_0 = error
1222 */
1223 static int
1224 qlafx00_configure_all_targets(scsi_qla_host_t *vha)
1225 {
1226 int rval;
1227 fc_port_t *fcport, *rmptemp;
1228 LIST_HEAD(new_fcports);
1229
1230 rval = qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
1231 FXDISC_GET_TGT_NODE_LIST);
1232 if (rval != QLA_SUCCESS) {
1233 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1234 return rval;
1235 }
1236
1237 rval = qlafx00_find_all_targets(vha, &new_fcports);
1238 if (rval != QLA_SUCCESS) {
1239 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1240 return rval;
1241 }
1242
1243 /*
1244 * Delete all previous devices marked lost.
1245 */
1246 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1247 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1248 break;
1249
1250 if (atomic_read(&fcport->state) == FCS_DEVICE_LOST) {
1251 if (fcport->port_type != FCT_INITIATOR)
1252 qla2x00_mark_device_lost(vha, fcport, 0);
1253 }
1254 }
1255
1256 /*
1257 * Add the new devices to our devices list.
1258 */
1259 list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
1260 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1261 break;
1262
1263 qla2x00_update_fcport(vha, fcport);
1264 list_move_tail(&fcport->list, &vha->vp_fcports);
1265 ql_log(ql_log_info, vha, 0x208f,
1266 "Attach new target id 0x%x wwnn = %llx "
1267 "wwpn = %llx.\n",
1268 fcport->tgt_id,
1269 (unsigned long long)wwn_to_u64(fcport->node_name),
1270 (unsigned long long)wwn_to_u64(fcport->port_name));
1271 }
1272
1273 /* Free all new device structures not processed. */
1274 list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
1275 list_del(&fcport->list);
1276 qla2x00_free_fcport(fcport);
1277 }
1278
1279 return rval;
1280 }
1281
1282 /*
1283 * qlafx00_configure_devices
1284 * Updates Fibre Channel Device Database with what is actually on loop.
1285 *
1286 * Input:
1287 * ha = adapter block pointer.
1288 *
1289 * Returns:
1290 * 0 = success.
1291 * 1 = error.
1292 * 2 = database was full and device was not configured.
1293 */
1294 int
1295 qlafx00_configure_devices(scsi_qla_host_t *vha)
1296 {
1297 int rval;
1298 unsigned long flags;
1299
1300 rval = QLA_SUCCESS;
1301
1302 flags = vha->dpc_flags;
1303
1304 ql_dbg(ql_dbg_disc, vha, 0x2090,
1305 "Configure devices -- dpc flags =0x%lx\n", flags);
1306
1307 rval = qlafx00_configure_all_targets(vha);
1308
1309 if (rval == QLA_SUCCESS) {
1310 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1311 rval = QLA_FUNCTION_FAILED;
1312 } else {
1313 atomic_set(&vha->loop_state, LOOP_READY);
1314 ql_log(ql_log_info, vha, 0x2091,
1315 "Device Ready\n");
1316 }
1317 }
1318
1319 if (rval) {
1320 ql_dbg(ql_dbg_disc, vha, 0x2092,
1321 "%s *** FAILED ***.\n", __func__);
1322 } else {
1323 ql_dbg(ql_dbg_disc, vha, 0x2093,
1324 "%s: exiting normally.\n", __func__);
1325 }
1326 return rval;
1327 }
1328
1329 static void
1330 qlafx00_abort_isp_cleanup(scsi_qla_host_t *vha, bool critemp)
1331 {
1332 struct qla_hw_data *ha = vha->hw;
1333 fc_port_t *fcport;
1334
1335 vha->flags.online = 0;
1336 ha->mr.fw_hbt_en = 0;
1337
1338 if (!critemp) {
1339 ha->flags.chip_reset_done = 0;
1340 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1341 vha->qla_stats.total_isp_aborts++;
1342 ql_log(ql_log_info, vha, 0x013f,
1343 "Performing ISP error recovery - ha = %p.\n", ha);
1344 ha->isp_ops->reset_chip(vha);
1345 }
1346
1347 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
1348 atomic_set(&vha->loop_state, LOOP_DOWN);
1349 atomic_set(&vha->loop_down_timer,
1350 QLAFX00_LOOP_DOWN_TIME);
1351 } else {
1352 if (!atomic_read(&vha->loop_down_timer))
1353 atomic_set(&vha->loop_down_timer,
1354 QLAFX00_LOOP_DOWN_TIME);
1355 }
1356
1357 /* Clear all async request states across all VPs. */
1358 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1359 fcport->flags = 0;
1360 if (atomic_read(&fcport->state) == FCS_ONLINE)
1361 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1362 }
1363
1364 if (!ha->flags.eeh_busy) {
1365 if (critemp) {
1366 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
1367 } else {
1368 /* Requeue all commands in outstanding command list. */
1369 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
1370 }
1371 }
1372
1373 qla2x00_free_irqs(vha);
1374 if (critemp)
1375 set_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags);
1376 else
1377 set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
1378
1379 /* Clear the Interrupts */
1380 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
1381
1382 ql_log(ql_log_info, vha, 0x0140,
1383 "%s Done done - ha=%p.\n", __func__, ha);
1384 }
1385
1386 /**
1387 * qlafx00_init_response_q_entries() - Initializes response queue entries.
1388 * @rsp: response queue
1389 *
1390 * Beginning of request ring has initialization control block already built
1391 * by nvram config routine.
1392 *
1393 * Returns 0 on success.
1394 */
1395 void
1396 qlafx00_init_response_q_entries(struct rsp_que *rsp)
1397 {
1398 uint16_t cnt;
1399 response_t *pkt;
1400
1401 rsp->ring_ptr = rsp->ring;
1402 rsp->ring_index = 0;
1403 rsp->status_srb = NULL;
1404 pkt = rsp->ring_ptr;
1405 for (cnt = 0; cnt < rsp->length; cnt++) {
1406 pkt->signature = RESPONSE_PROCESSED;
1407 wrt_reg_dword((void __force __iomem *)&pkt->signature,
1408 RESPONSE_PROCESSED);
1409 pkt++;
1410 }
1411 }
1412
1413 int
1414 qlafx00_rescan_isp(scsi_qla_host_t *vha)
1415 {
1416 uint32_t status = QLA_FUNCTION_FAILED;
1417 struct qla_hw_data *ha = vha->hw;
1418 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
1419 uint32_t aenmbx7;
1420
1421 qla2x00_request_irqs(ha, ha->rsp_q_map[0]);
1422
1423 aenmbx7 = rd_reg_dword(&reg->aenmailbox7);
1424 ha->mbx_intr_code = MSW(aenmbx7);
1425 ha->rqstq_intr_code = LSW(aenmbx7);
1426 ha->req_que_off = rd_reg_dword(&reg->aenmailbox1);
1427 ha->rsp_que_off = rd_reg_dword(&reg->aenmailbox3);
1428 ha->req_que_len = rd_reg_dword(&reg->aenmailbox5);
1429 ha->rsp_que_len = rd_reg_dword(&reg->aenmailbox6);
1430
1431 ql_dbg(ql_dbg_disc, vha, 0x2094,
1432 "fw returned mbx_intr_code: 0x%x, rqstq_intr_code: 0x%x "
1433 " Req que offset 0x%x Rsp que offset 0x%x\n",
1434 ha->mbx_intr_code, ha->rqstq_intr_code,
1435 ha->req_que_off, ha->rsp_que_len);
1436
1437 /* Clear the Interrupts */
1438 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
1439
1440 status = qla2x00_init_rings(vha);
1441 if (!status) {
1442 vha->flags.online = 1;
1443
1444 /* if no cable then assume it's good */
1445 if ((vha->device_flags & DFLG_NO_CABLE))
1446 status = 0;
1447 /* Register system information */
1448 if (qlafx00_fx_disc(vha,
1449 &vha->hw->mr.fcport, FXDISC_REG_HOST_INFO))
1450 ql_dbg(ql_dbg_disc, vha, 0x2095,
1451 "failed to register host info\n");
1452 }
1453 scsi_unblock_requests(vha->host);
1454 return status;
1455 }
1456
1457 void
1458 qlafx00_timer_routine(scsi_qla_host_t *vha)
1459 {
1460 struct qla_hw_data *ha = vha->hw;
1461 uint32_t fw_heart_beat;
1462 uint32_t aenmbx0;
1463 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
1464 uint32_t tempc;
1465
1466 /* Check firmware health */
1467 if (ha->mr.fw_hbt_cnt)
1468 ha->mr.fw_hbt_cnt--;
1469 else {
1470 if ((!ha->flags.mr_reset_hdlr_active) &&
1471 (!test_bit(UNLOADING, &vha->dpc_flags)) &&
1472 (!test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
1473 (ha->mr.fw_hbt_en)) {
1474 fw_heart_beat = rd_reg_dword(&reg->fwheartbeat);
1475 if (fw_heart_beat != ha->mr.old_fw_hbt_cnt) {
1476 ha->mr.old_fw_hbt_cnt = fw_heart_beat;
1477 ha->mr.fw_hbt_miss_cnt = 0;
1478 } else {
1479 ha->mr.fw_hbt_miss_cnt++;
1480 if (ha->mr.fw_hbt_miss_cnt ==
1481 QLAFX00_HEARTBEAT_MISS_CNT) {
1482 set_bit(ISP_ABORT_NEEDED,
1483 &vha->dpc_flags);
1484 qla2xxx_wake_dpc(vha);
1485 ha->mr.fw_hbt_miss_cnt = 0;
1486 }
1487 }
1488 }
1489 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
1490 }
1491
1492 if (test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags)) {
1493 /* Reset recovery to be performed in timer routine */
1494 aenmbx0 = rd_reg_dword(&reg->aenmailbox0);
1495 if (ha->mr.fw_reset_timer_exp) {
1496 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1497 qla2xxx_wake_dpc(vha);
1498 ha->mr.fw_reset_timer_exp = 0;
1499 } else if (aenmbx0 == MBA_FW_RESTART_CMPLT) {
1500 /* Wake up DPC to rescan the targets */
1501 set_bit(FX00_TARGET_SCAN, &vha->dpc_flags);
1502 clear_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
1503 qla2xxx_wake_dpc(vha);
1504 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
1505 } else if ((aenmbx0 == MBA_FW_STARTING) &&
1506 (!ha->mr.fw_hbt_en)) {
1507 ha->mr.fw_hbt_en = 1;
1508 } else if (!ha->mr.fw_reset_timer_tick) {
1509 if (aenmbx0 == ha->mr.old_aenmbx0_state)
1510 ha->mr.fw_reset_timer_exp = 1;
1511 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
1512 } else if (aenmbx0 == 0xFFFFFFFF) {
1513 uint32_t data0, data1;
1514
1515 data0 = QLAFX00_RD_REG(ha,
1516 QLAFX00_BAR1_BASE_ADDR_REG);
1517 data1 = QLAFX00_RD_REG(ha,
1518 QLAFX00_PEX0_WIN0_BASE_ADDR_REG);
1519
1520 data0 &= 0xffff0000;
1521 data1 &= 0x0000ffff;
1522
1523 QLAFX00_WR_REG(ha,
1524 QLAFX00_PEX0_WIN0_BASE_ADDR_REG,
1525 (data0 | data1));
1526 } else if ((aenmbx0 & 0xFF00) == MBA_FW_POLL_STATE) {
1527 ha->mr.fw_reset_timer_tick =
1528 QLAFX00_MAX_RESET_INTERVAL;
1529 } else if (aenmbx0 == MBA_FW_RESET_FCT) {
1530 ha->mr.fw_reset_timer_tick =
1531 QLAFX00_MAX_RESET_INTERVAL;
1532 }
1533 if (ha->mr.old_aenmbx0_state != aenmbx0) {
1534 ha->mr.old_aenmbx0_state = aenmbx0;
1535 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
1536 }
1537 ha->mr.fw_reset_timer_tick--;
1538 }
1539 if (test_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags)) {
1540 /*
1541 * Critical temperature recovery to be
1542 * performed in timer routine
1543 */
1544 if (ha->mr.fw_critemp_timer_tick == 0) {
1545 tempc = QLAFX00_GET_TEMPERATURE(ha);
1546 ql_dbg(ql_dbg_timer, vha, 0x6012,
1547 "ISPFx00(%s): Critical temp timer, "
1548 "current SOC temperature: %d\n",
1549 __func__, tempc);
1550 if (tempc < ha->mr.critical_temperature) {
1551 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1552 clear_bit(FX00_CRITEMP_RECOVERY,
1553 &vha->dpc_flags);
1554 qla2xxx_wake_dpc(vha);
1555 }
1556 ha->mr.fw_critemp_timer_tick =
1557 QLAFX00_CRITEMP_INTERVAL;
1558 } else {
1559 ha->mr.fw_critemp_timer_tick--;
1560 }
1561 }
1562 if (ha->mr.host_info_resend) {
1563 /*
1564 * Incomplete host info might be sent to firmware
1565 * durinng system boot - info should be resend
1566 */
1567 if (ha->mr.hinfo_resend_timer_tick == 0) {
1568 ha->mr.host_info_resend = false;
1569 set_bit(FX00_HOST_INFO_RESEND, &vha->dpc_flags);
1570 ha->mr.hinfo_resend_timer_tick =
1571 QLAFX00_HINFO_RESEND_INTERVAL;
1572 qla2xxx_wake_dpc(vha);
1573 } else {
1574 ha->mr.hinfo_resend_timer_tick--;
1575 }
1576 }
1577
1578 }
1579
1580 /*
1581 * qlfx00a_reset_initialize
1582 * Re-initialize after a iSA device reset.
1583 *
1584 * Input:
1585 * ha = adapter block pointer.
1586 *
1587 * Returns:
1588 * 0 = success
1589 */
1590 int
1591 qlafx00_reset_initialize(scsi_qla_host_t *vha)
1592 {
1593 struct qla_hw_data *ha = vha->hw;
1594
1595 if (vha->device_flags & DFLG_DEV_FAILED) {
1596 ql_dbg(ql_dbg_init, vha, 0x0142,
1597 "Device in failed state\n");
1598 return QLA_SUCCESS;
1599 }
1600
1601 ha->flags.mr_reset_hdlr_active = 1;
1602
1603 if (vha->flags.online) {
1604 scsi_block_requests(vha->host);
1605 qlafx00_abort_isp_cleanup(vha, false);
1606 }
1607
1608 ql_log(ql_log_info, vha, 0x0143,
1609 "(%s): succeeded.\n", __func__);
1610 ha->flags.mr_reset_hdlr_active = 0;
1611 return QLA_SUCCESS;
1612 }
1613
1614 /*
1615 * qlafx00_abort_isp
1616 * Resets ISP and aborts all outstanding commands.
1617 *
1618 * Input:
1619 * ha = adapter block pointer.
1620 *
1621 * Returns:
1622 * 0 = success
1623 */
1624 int
1625 qlafx00_abort_isp(scsi_qla_host_t *vha)
1626 {
1627 struct qla_hw_data *ha = vha->hw;
1628
1629 if (vha->flags.online) {
1630 if (unlikely(pci_channel_offline(ha->pdev) &&
1631 ha->flags.pci_channel_io_perm_failure)) {
1632 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1633 return QLA_SUCCESS;
1634 }
1635
1636 scsi_block_requests(vha->host);
1637 qlafx00_abort_isp_cleanup(vha, false);
1638 } else {
1639 scsi_block_requests(vha->host);
1640 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1641 vha->qla_stats.total_isp_aborts++;
1642 ha->isp_ops->reset_chip(vha);
1643 set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
1644 /* Clear the Interrupts */
1645 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
1646 }
1647
1648 ql_log(ql_log_info, vha, 0x0145,
1649 "(%s): succeeded.\n", __func__);
1650
1651 return QLA_SUCCESS;
1652 }
1653
1654 static inline fc_port_t*
1655 qlafx00_get_fcport(struct scsi_qla_host *vha, int tgt_id)
1656 {
1657 fc_port_t *fcport;
1658
1659 /* Check for matching device in remote port list. */
1660 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1661 if (fcport->tgt_id == tgt_id) {
1662 ql_dbg(ql_dbg_async, vha, 0x5072,
1663 "Matching fcport(%p) found with TGT-ID: 0x%x "
1664 "and Remote TGT_ID: 0x%x\n",
1665 fcport, fcport->tgt_id, tgt_id);
1666 return fcport;
1667 }
1668 }
1669 return NULL;
1670 }
1671
1672 static void
1673 qlafx00_tgt_detach(struct scsi_qla_host *vha, int tgt_id)
1674 {
1675 fc_port_t *fcport;
1676
1677 ql_log(ql_log_info, vha, 0x5073,
1678 "Detach TGT-ID: 0x%x\n", tgt_id);
1679
1680 fcport = qlafx00_get_fcport(vha, tgt_id);
1681 if (!fcport)
1682 return;
1683
1684 qla2x00_mark_device_lost(vha, fcport, 0);
1685
1686 return;
1687 }
1688
1689 void
1690 qlafx00_process_aen(struct scsi_qla_host *vha, struct qla_work_evt *evt)
1691 {
1692 uint32_t aen_code, aen_data;
1693
1694 aen_code = FCH_EVT_VENDOR_UNIQUE;
1695 aen_data = evt->u.aenfx.evtcode;
1696
1697 switch (evt->u.aenfx.evtcode) {
1698 case QLAFX00_MBA_PORT_UPDATE: /* Port database update */
1699 if (evt->u.aenfx.mbx[1] == 0) {
1700 if (evt->u.aenfx.mbx[2] == 1) {
1701 if (!vha->flags.fw_tgt_reported)
1702 vha->flags.fw_tgt_reported = 1;
1703 atomic_set(&vha->loop_down_timer, 0);
1704 atomic_set(&vha->loop_state, LOOP_UP);
1705 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1706 qla2xxx_wake_dpc(vha);
1707 } else if (evt->u.aenfx.mbx[2] == 2) {
1708 qlafx00_tgt_detach(vha, evt->u.aenfx.mbx[3]);
1709 }
1710 } else if (evt->u.aenfx.mbx[1] == 0xffff) {
1711 if (evt->u.aenfx.mbx[2] == 1) {
1712 if (!vha->flags.fw_tgt_reported)
1713 vha->flags.fw_tgt_reported = 1;
1714 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1715 } else if (evt->u.aenfx.mbx[2] == 2) {
1716 vha->device_flags |= DFLG_NO_CABLE;
1717 qla2x00_mark_all_devices_lost(vha);
1718 }
1719 }
1720 break;
1721 case QLAFX00_MBA_LINK_UP:
1722 aen_code = FCH_EVT_LINKUP;
1723 aen_data = 0;
1724 break;
1725 case QLAFX00_MBA_LINK_DOWN:
1726 aen_code = FCH_EVT_LINKDOWN;
1727 aen_data = 0;
1728 break;
1729 case QLAFX00_MBA_TEMP_CRIT: /* Critical temperature event */
1730 ql_log(ql_log_info, vha, 0x5082,
1731 "Process critical temperature event "
1732 "aenmb[0]: %x\n",
1733 evt->u.aenfx.evtcode);
1734 scsi_block_requests(vha->host);
1735 qlafx00_abort_isp_cleanup(vha, true);
1736 scsi_unblock_requests(vha->host);
1737 break;
1738 }
1739
1740 fc_host_post_event(vha->host, fc_get_event_number(),
1741 aen_code, aen_data);
1742 }
1743
1744 static void
1745 qlafx00_update_host_attr(scsi_qla_host_t *vha, struct port_info_data *pinfo)
1746 {
1747 u64 port_name = 0, node_name = 0;
1748
1749 port_name = (unsigned long long)wwn_to_u64(pinfo->port_name);
1750 node_name = (unsigned long long)wwn_to_u64(pinfo->node_name);
1751
1752 fc_host_node_name(vha->host) = node_name;
1753 fc_host_port_name(vha->host) = port_name;
1754 if (!pinfo->port_type)
1755 vha->hw->current_topology = ISP_CFG_F;
1756 if (pinfo->link_status == QLAFX00_LINK_STATUS_UP)
1757 atomic_set(&vha->loop_state, LOOP_READY);
1758 else if (pinfo->link_status == QLAFX00_LINK_STATUS_DOWN)
1759 atomic_set(&vha->loop_state, LOOP_DOWN);
1760 vha->hw->link_data_rate = (uint16_t)pinfo->link_config;
1761 }
1762
1763 static void
1764 qla2x00_fxdisc_iocb_timeout(void *data)
1765 {
1766 srb_t *sp = data;
1767 struct srb_iocb *lio = &sp->u.iocb_cmd;
1768
1769 complete(&lio->u.fxiocb.fxiocb_comp);
1770 }
1771
1772 static void qla2x00_fxdisc_sp_done(srb_t *sp, int res)
1773 {
1774 struct srb_iocb *lio = &sp->u.iocb_cmd;
1775
1776 complete(&lio->u.fxiocb.fxiocb_comp);
1777 }
1778
1779 int
1780 qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type)
1781 {
1782 srb_t *sp;
1783 struct srb_iocb *fdisc;
1784 int rval = QLA_FUNCTION_FAILED;
1785 struct qla_hw_data *ha = vha->hw;
1786 struct host_system_info *phost_info;
1787 struct register_host_info *preg_hsi;
1788 struct new_utsname *p_sysid = NULL;
1789
1790 /* ref: INIT */
1791 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1792 if (!sp)
1793 goto done;
1794
1795 sp->type = SRB_FXIOCB_DCMD;
1796 sp->name = "fxdisc";
1797 qla2x00_init_async_sp(sp, FXDISC_TIMEOUT,
1798 qla2x00_fxdisc_sp_done);
1799 sp->u.iocb_cmd.timeout = qla2x00_fxdisc_iocb_timeout;
1800
1801 fdisc = &sp->u.iocb_cmd;
1802 switch (fx_type) {
1803 case FXDISC_GET_CONFIG_INFO:
1804 fdisc->u.fxiocb.flags =
1805 SRB_FXDISC_RESP_DMA_VALID;
1806 fdisc->u.fxiocb.rsp_len = sizeof(struct config_info_data);
1807 break;
1808 case FXDISC_GET_PORT_INFO:
1809 fdisc->u.fxiocb.flags =
1810 SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
1811 fdisc->u.fxiocb.rsp_len = QLAFX00_PORT_DATA_INFO;
1812 fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->port_id);
1813 break;
1814 case FXDISC_GET_TGT_NODE_INFO:
1815 fdisc->u.fxiocb.flags =
1816 SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
1817 fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_INFO;
1818 fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->tgt_id);
1819 break;
1820 case FXDISC_GET_TGT_NODE_LIST:
1821 fdisc->u.fxiocb.flags =
1822 SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
1823 fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_LIST_SIZE;
1824 break;
1825 case FXDISC_REG_HOST_INFO:
1826 fdisc->u.fxiocb.flags = SRB_FXDISC_REQ_DMA_VALID;
1827 fdisc->u.fxiocb.req_len = sizeof(struct register_host_info);
1828 p_sysid = utsname();
1829 if (!p_sysid) {
1830 ql_log(ql_log_warn, vha, 0x303c,
1831 "Not able to get the system information\n");
1832 goto done_free_sp;
1833 }
1834 break;
1835 case FXDISC_ABORT_IOCTL:
1836 default:
1837 break;
1838 }
1839
1840 if (fdisc->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
1841 fdisc->u.fxiocb.req_addr = dma_alloc_coherent(&ha->pdev->dev,
1842 fdisc->u.fxiocb.req_len,
1843 &fdisc->u.fxiocb.req_dma_handle, GFP_KERNEL);
1844 if (!fdisc->u.fxiocb.req_addr)
1845 goto done_free_sp;
1846
1847 if (fx_type == FXDISC_REG_HOST_INFO) {
1848 preg_hsi = (struct register_host_info *)
1849 fdisc->u.fxiocb.req_addr;
1850 phost_info = &preg_hsi->hsi;
1851 memset(preg_hsi, 0, sizeof(struct register_host_info));
1852 phost_info->os_type = OS_TYPE_LINUX;
1853 strscpy(phost_info->sysname, p_sysid->sysname,
1854 sizeof(phost_info->sysname));
1855 strscpy(phost_info->nodename, p_sysid->nodename,
1856 sizeof(phost_info->nodename));
1857 if (!strcmp(phost_info->nodename, "(none)"))
1858 ha->mr.host_info_resend = true;
1859 strscpy(phost_info->release, p_sysid->release,
1860 sizeof(phost_info->release));
1861 strscpy(phost_info->version, p_sysid->version,
1862 sizeof(phost_info->version));
1863 strscpy(phost_info->machine, p_sysid->machine,
1864 sizeof(phost_info->machine));
1865 strscpy(phost_info->domainname, p_sysid->domainname,
1866 sizeof(phost_info->domainname));
1867 strscpy(phost_info->hostdriver, QLA2XXX_VERSION,
1868 sizeof(phost_info->hostdriver));
1869 preg_hsi->utc = (uint64_t)ktime_get_real_seconds();
1870 ql_dbg(ql_dbg_init, vha, 0x0149,
1871 "ISP%04X: Host registration with firmware\n",
1872 ha->pdev->device);
1873 ql_dbg(ql_dbg_init, vha, 0x014a,
1874 "os_type = '%d', sysname = '%s', nodname = '%s'\n",
1875 phost_info->os_type,
1876 phost_info->sysname,
1877 phost_info->nodename);
1878 ql_dbg(ql_dbg_init, vha, 0x014b,
1879 "release = '%s', version = '%s'\n",
1880 phost_info->release,
1881 phost_info->version);
1882 ql_dbg(ql_dbg_init, vha, 0x014c,
1883 "machine = '%s' "
1884 "domainname = '%s', hostdriver = '%s'\n",
1885 phost_info->machine,
1886 phost_info->domainname,
1887 phost_info->hostdriver);
1888 ql_dump_buffer(ql_dbg_init + ql_dbg_disc, vha, 0x014d,
1889 phost_info, sizeof(*phost_info));
1890 }
1891 }
1892
1893 if (fdisc->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
1894 fdisc->u.fxiocb.rsp_addr = dma_alloc_coherent(&ha->pdev->dev,
1895 fdisc->u.fxiocb.rsp_len,
1896 &fdisc->u.fxiocb.rsp_dma_handle, GFP_KERNEL);
1897 if (!fdisc->u.fxiocb.rsp_addr)
1898 goto done_unmap_req;
1899 }
1900
1901 fdisc->u.fxiocb.req_func_type = cpu_to_le16(fx_type);
1902
1903 rval = qla2x00_start_sp(sp);
1904 if (rval != QLA_SUCCESS)
1905 goto done_unmap_dma;
1906
1907 wait_for_completion(&fdisc->u.fxiocb.fxiocb_comp);
1908
1909 if (fx_type == FXDISC_GET_CONFIG_INFO) {
1910 struct config_info_data *pinfo =
1911 (struct config_info_data *) fdisc->u.fxiocb.rsp_addr;
1912 memtostr(vha->hw->model_number, pinfo->model_num);
1913 memtostr(vha->hw->model_desc, pinfo->model_description);
1914 memcpy(&vha->hw->mr.symbolic_name, pinfo->symbolic_name,
1915 sizeof(vha->hw->mr.symbolic_name));
1916 memcpy(&vha->hw->mr.serial_num, pinfo->serial_num,
1917 sizeof(vha->hw->mr.serial_num));
1918 memcpy(&vha->hw->mr.hw_version, pinfo->hw_version,
1919 sizeof(vha->hw->mr.hw_version));
1920 memcpy(&vha->hw->mr.fw_version, pinfo->fw_version,
1921 sizeof(vha->hw->mr.fw_version));
1922 strim(vha->hw->mr.fw_version);
1923 memcpy(&vha->hw->mr.uboot_version, pinfo->uboot_version,
1924 sizeof(vha->hw->mr.uboot_version));
1925 memcpy(&vha->hw->mr.fru_serial_num, pinfo->fru_serial_num,
1926 sizeof(vha->hw->mr.fru_serial_num));
1927 vha->hw->mr.critical_temperature =
1928 (pinfo->nominal_temp_value) ?
1929 pinfo->nominal_temp_value : QLAFX00_CRITEMP_THRSHLD;
1930 ha->mr.extended_io_enabled = (pinfo->enabled_capabilities &
1931 QLAFX00_EXTENDED_IO_EN_MASK) != 0;
1932 } else if (fx_type == FXDISC_GET_PORT_INFO) {
1933 struct port_info_data *pinfo =
1934 (struct port_info_data *) fdisc->u.fxiocb.rsp_addr;
1935 memcpy(vha->node_name, pinfo->node_name, WWN_SIZE);
1936 memcpy(vha->port_name, pinfo->port_name, WWN_SIZE);
1937 vha->d_id.b.domain = pinfo->port_id[0];
1938 vha->d_id.b.area = pinfo->port_id[1];
1939 vha->d_id.b.al_pa = pinfo->port_id[2];
1940 qlafx00_update_host_attr(vha, pinfo);
1941 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0141,
1942 pinfo, 16);
1943 } else if (fx_type == FXDISC_GET_TGT_NODE_INFO) {
1944 struct qlafx00_tgt_node_info *pinfo =
1945 (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
1946 memcpy(fcport->node_name, pinfo->tgt_node_wwnn, WWN_SIZE);
1947 memcpy(fcport->port_name, pinfo->tgt_node_wwpn, WWN_SIZE);
1948 fcport->port_type = FCT_TARGET;
1949 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0144,
1950 pinfo, 16);
1951 } else if (fx_type == FXDISC_GET_TGT_NODE_LIST) {
1952 struct qlafx00_tgt_node_info *pinfo =
1953 (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
1954 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0146,
1955 pinfo, 16);
1956 memcpy(vha->hw->gid_list, pinfo, QLAFX00_TGT_NODE_LIST_SIZE);
1957 } else if (fx_type == FXDISC_ABORT_IOCTL)
1958 fdisc->u.fxiocb.result =
1959 (fdisc->u.fxiocb.result ==
1960 cpu_to_le32(QLAFX00_IOCTL_ICOB_ABORT_SUCCESS)) ?
1961 cpu_to_le32(QLA_SUCCESS) : cpu_to_le32(QLA_FUNCTION_FAILED);
1962
1963 rval = le32_to_cpu(fdisc->u.fxiocb.result);
1964
1965 done_unmap_dma:
1966 if (fdisc->u.fxiocb.rsp_addr)
1967 dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.rsp_len,
1968 fdisc->u.fxiocb.rsp_addr, fdisc->u.fxiocb.rsp_dma_handle);
1969
1970 done_unmap_req:
1971 if (fdisc->u.fxiocb.req_addr)
1972 dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.req_len,
1973 fdisc->u.fxiocb.req_addr, fdisc->u.fxiocb.req_dma_handle);
1974 done_free_sp:
1975 /* ref: INIT */
1976 kref_put(&sp->cmd_kref, qla2x00_sp_release);
1977 done:
1978 return rval;
1979 }
1980
1981 /*
1982 * qlafx00_initialize_adapter
1983 * Initialize board.
1984 *
1985 * Input:
1986 * ha = adapter block pointer.
1987 *
1988 * Returns:
1989 * 0 = success
1990 */
1991 int
1992 qlafx00_initialize_adapter(scsi_qla_host_t *vha)
1993 {
1994 int rval;
1995 struct qla_hw_data *ha = vha->hw;
1996 uint32_t tempc;
1997
1998 /* Clear adapter flags. */
1999 vha->flags.online = 0;
2000 ha->flags.chip_reset_done = 0;
2001 vha->flags.reset_active = 0;
2002 ha->flags.pci_channel_io_perm_failure = 0;
2003 ha->flags.eeh_busy = 0;
2004 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
2005 atomic_set(&vha->loop_state, LOOP_DOWN);
2006 vha->device_flags = DFLG_NO_CABLE;
2007 vha->dpc_flags = 0;
2008 vha->flags.management_server_logged_in = 0;
2009 ha->isp_abort_cnt = 0;
2010 ha->beacon_blink_led = 0;
2011
2012 set_bit(0, ha->req_qid_map);
2013 set_bit(0, ha->rsp_qid_map);
2014
2015 ql_dbg(ql_dbg_init, vha, 0x0147,
2016 "Configuring PCI space...\n");
2017
2018 rval = ha->isp_ops->pci_config(vha);
2019 if (rval) {
2020 ql_log(ql_log_warn, vha, 0x0148,
2021 "Unable to configure PCI space.\n");
2022 return rval;
2023 }
2024
2025 rval = qlafx00_init_fw_ready(vha);
2026 if (rval != QLA_SUCCESS)
2027 return rval;
2028
2029 qlafx00_save_queue_ptrs(vha);
2030
2031 rval = qlafx00_config_queues(vha);
2032 if (rval != QLA_SUCCESS)
2033 return rval;
2034
2035 /*
2036 * Allocate the array of outstanding commands
2037 * now that we know the firmware resources.
2038 */
2039 rval = qla2x00_alloc_outstanding_cmds(ha, vha->req);
2040 if (rval != QLA_SUCCESS)
2041 return rval;
2042
2043 rval = qla2x00_init_rings(vha);
2044 ha->flags.chip_reset_done = 1;
2045
2046 tempc = QLAFX00_GET_TEMPERATURE(ha);
2047 ql_dbg(ql_dbg_init, vha, 0x0152,
2048 "ISPFx00(%s): Critical temp timer, current SOC temperature: 0x%x\n",
2049 __func__, tempc);
2050
2051 return rval;
2052 }
2053
2054 uint32_t
2055 qlafx00_fw_state_show(struct device *dev, struct device_attribute *attr,
2056 char *buf)
2057 {
2058 scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
2059 int rval = QLA_FUNCTION_FAILED;
2060 uint32_t state[1];
2061
2062 if (qla2x00_reset_active(vha))
2063 ql_log(ql_log_warn, vha, 0x70ce,
2064 "ISP reset active.\n");
2065 else if (!vha->hw->flags.eeh_busy) {
2066 rval = qlafx00_get_firmware_state(vha, state);
2067 }
2068 if (rval != QLA_SUCCESS)
2069 memset(state, -1, sizeof(state));
2070
2071 return state[0];
2072 }
2073
2074 void
2075 qlafx00_get_host_speed(struct Scsi_Host *shost)
2076 {
2077 struct qla_hw_data *ha = ((struct scsi_qla_host *)
2078 (shost_priv(shost)))->hw;
2079 u32 speed = FC_PORTSPEED_UNKNOWN;
2080
2081 switch (ha->link_data_rate) {
2082 case QLAFX00_PORT_SPEED_2G:
2083 speed = FC_PORTSPEED_2GBIT;
2084 break;
2085 case QLAFX00_PORT_SPEED_4G:
2086 speed = FC_PORTSPEED_4GBIT;
2087 break;
2088 case QLAFX00_PORT_SPEED_8G:
2089 speed = FC_PORTSPEED_8GBIT;
2090 break;
2091 case QLAFX00_PORT_SPEED_10G:
2092 speed = FC_PORTSPEED_10GBIT;
2093 break;
2094 }
2095 fc_host_speed(shost) = speed;
2096 }
2097
2098 /** QLAFX00 specific ISR implementation functions */
2099
2100 static inline void
2101 qlafx00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
2102 uint32_t sense_len, struct rsp_que *rsp, int res)
2103 {
2104 struct scsi_qla_host *vha = sp->vha;
2105 struct scsi_cmnd *cp = GET_CMD_SP(sp);
2106 uint32_t track_sense_len;
2107
2108 SET_FW_SENSE_LEN(sp, sense_len);
2109
2110 if (sense_len >= SCSI_SENSE_BUFFERSIZE)
2111 sense_len = SCSI_SENSE_BUFFERSIZE;
2112
2113 SET_CMD_SENSE_LEN(sp, sense_len);
2114 SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
2115 track_sense_len = sense_len;
2116
2117 if (sense_len > par_sense_len)
2118 sense_len = par_sense_len;
2119
2120 memcpy(cp->sense_buffer, sense_data, sense_len);
2121
2122 SET_FW_SENSE_LEN(sp, GET_FW_SENSE_LEN(sp) - sense_len);
2123
2124 SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
2125 track_sense_len -= sense_len;
2126 SET_CMD_SENSE_LEN(sp, track_sense_len);
2127
2128 ql_dbg(ql_dbg_io, vha, 0x304d,
2129 "sense_len=0x%x par_sense_len=0x%x track_sense_len=0x%x.\n",
2130 sense_len, par_sense_len, track_sense_len);
2131 if (GET_FW_SENSE_LEN(sp) > 0) {
2132 rsp->status_srb = sp;
2133 cp->result = res;
2134 }
2135
2136 if (sense_len) {
2137 ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x3039,
2138 "Check condition Sense data, nexus%ld:%d:%llu cmd=%p.\n",
2139 sp->vha->host_no, cp->device->id, cp->device->lun,
2140 cp);
2141 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3049,
2142 cp->sense_buffer, sense_len);
2143 }
2144 }
2145
2146 static void
2147 qlafx00_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
2148 struct tsk_mgmt_entry_fx00 *pkt, srb_t *sp,
2149 __le16 sstatus, __le16 cpstatus)
2150 {
2151 struct srb_iocb *tmf;
2152
2153 tmf = &sp->u.iocb_cmd;
2154 if (cpstatus != cpu_to_le16((uint16_t)CS_COMPLETE) ||
2155 (sstatus & cpu_to_le16((uint16_t)SS_RESPONSE_INFO_LEN_VALID)))
2156 cpstatus = cpu_to_le16((uint16_t)CS_INCOMPLETE);
2157 tmf->u.tmf.comp_status = cpstatus;
2158 sp->done(sp, 0);
2159 }
2160
2161 static void
2162 qlafx00_abort_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
2163 struct abort_iocb_entry_fx00 *pkt)
2164 {
2165 const char func[] = "ABT_IOCB";
2166 srb_t *sp;
2167 struct srb_iocb *abt;
2168
2169 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2170 if (!sp)
2171 return;
2172
2173 abt = &sp->u.iocb_cmd;
2174 abt->u.abt.comp_status = pkt->tgt_id_sts;
2175 sp->done(sp, 0);
2176 }
2177
2178 static void
2179 qlafx00_ioctl_iosb_entry(scsi_qla_host_t *vha, struct req_que *req,
2180 struct ioctl_iocb_entry_fx00 *pkt)
2181 {
2182 const char func[] = "IOSB_IOCB";
2183 srb_t *sp;
2184 struct bsg_job *bsg_job;
2185 struct fc_bsg_reply *bsg_reply;
2186 struct srb_iocb *iocb_job;
2187 int res = 0;
2188 struct qla_mt_iocb_rsp_fx00 fstatus;
2189 uint8_t *fw_sts_ptr;
2190
2191 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2192 if (!sp)
2193 return;
2194
2195 if (sp->type == SRB_FXIOCB_DCMD) {
2196 iocb_job = &sp->u.iocb_cmd;
2197 iocb_job->u.fxiocb.seq_number = pkt->seq_no;
2198 iocb_job->u.fxiocb.fw_flags = pkt->fw_iotcl_flags;
2199 iocb_job->u.fxiocb.result = pkt->status;
2200 if (iocb_job->u.fxiocb.flags & SRB_FXDISC_RSP_DWRD_VALID)
2201 iocb_job->u.fxiocb.req_data =
2202 pkt->dataword_r;
2203 } else {
2204 bsg_job = sp->u.bsg_job;
2205 bsg_reply = bsg_job->reply;
2206
2207 memset(&fstatus, 0, sizeof(struct qla_mt_iocb_rsp_fx00));
2208
2209 fstatus.reserved_1 = pkt->reserved_0;
2210 fstatus.func_type = pkt->comp_func_num;
2211 fstatus.ioctl_flags = pkt->fw_iotcl_flags;
2212 fstatus.ioctl_data = pkt->dataword_r;
2213 fstatus.adapid = pkt->adapid;
2214 fstatus.reserved_2 = pkt->dataword_r_extra;
2215 fstatus.res_count = pkt->residuallen;
2216 fstatus.status = pkt->status;
2217 fstatus.seq_number = pkt->seq_no;
2218 memcpy(fstatus.reserved_3,
2219 pkt->reserved_2, 20 * sizeof(uint8_t));
2220
2221 fw_sts_ptr = bsg_job->reply + sizeof(struct fc_bsg_reply);
2222
2223 memcpy(fw_sts_ptr, &fstatus, sizeof(fstatus));
2224 bsg_job->reply_len = sizeof(struct fc_bsg_reply) +
2225 sizeof(struct qla_mt_iocb_rsp_fx00) + sizeof(uint8_t);
2226
2227 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
2228 sp->vha, 0x5080, pkt, sizeof(*pkt));
2229
2230 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
2231 sp->vha, 0x5074,
2232 fw_sts_ptr, sizeof(fstatus));
2233
2234 res = bsg_reply->result = DID_OK << 16;
2235 bsg_reply->reply_payload_rcv_len =
2236 bsg_job->reply_payload.payload_len;
2237 }
2238 sp->done(sp, res);
2239 }
2240
2241 /**
2242 * qlafx00_status_entry() - Process a Status IOCB entry.
2243 * @vha: SCSI driver HA context
2244 * @rsp: response queue
2245 * @pkt: Entry pointer
2246 */
2247 static void
2248 qlafx00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
2249 {
2250 srb_t *sp;
2251 fc_port_t *fcport;
2252 struct scsi_cmnd *cp;
2253 struct sts_entry_fx00 *sts;
2254 __le16 comp_status;
2255 __le16 scsi_status;
2256 __le16 lscsi_status;
2257 int32_t resid;
2258 uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
2259 fw_resid_len;
2260 uint8_t *rsp_info = NULL, *sense_data = NULL;
2261 struct qla_hw_data *ha = vha->hw;
2262 uint32_t hindex, handle;
2263 uint16_t que;
2264 struct req_que *req;
2265 int logit = 1;
2266 int res = 0;
2267
2268 sts = (struct sts_entry_fx00 *) pkt;
2269
2270 comp_status = sts->comp_status;
2271 scsi_status = sts->scsi_status & cpu_to_le16((uint16_t)SS_MASK);
2272 hindex = sts->handle;
2273 handle = LSW(hindex);
2274
2275 que = MSW(hindex);
2276 req = ha->req_q_map[que];
2277
2278 /* Validate handle. */
2279 if (handle < req->num_outstanding_cmds)
2280 sp = req->outstanding_cmds[handle];
2281 else
2282 sp = NULL;
2283
2284 if (sp == NULL) {
2285 ql_dbg(ql_dbg_io, vha, 0x3034,
2286 "Invalid status handle (0x%x).\n", handle);
2287
2288 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2289 qla2xxx_wake_dpc(vha);
2290 return;
2291 }
2292
2293 if (sp->type == SRB_TM_CMD) {
2294 req->outstanding_cmds[handle] = NULL;
2295 qlafx00_tm_iocb_entry(vha, req, pkt, sp,
2296 scsi_status, comp_status);
2297 return;
2298 }
2299
2300 /* Fast path completion. */
2301 if (comp_status == CS_COMPLETE && scsi_status == 0) {
2302 qla2x00_process_completed_request(vha, req, handle);
2303 return;
2304 }
2305
2306 req->outstanding_cmds[handle] = NULL;
2307 cp = GET_CMD_SP(sp);
2308 if (cp == NULL) {
2309 ql_dbg(ql_dbg_io, vha, 0x3048,
2310 "Command already returned (0x%x/%p).\n",
2311 handle, sp);
2312
2313 return;
2314 }
2315
2316 lscsi_status = scsi_status & cpu_to_le16((uint16_t)STATUS_MASK);
2317
2318 fcport = sp->fcport;
2319
2320 sense_len = par_sense_len = rsp_info_len = resid_len =
2321 fw_resid_len = 0;
2322 if (scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID))
2323 sense_len = sts->sense_len;
2324 if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
2325 | (uint16_t)SS_RESIDUAL_OVER)))
2326 resid_len = le32_to_cpu(sts->residual_len);
2327 if (comp_status == cpu_to_le16((uint16_t)CS_DATA_UNDERRUN))
2328 fw_resid_len = le32_to_cpu(sts->residual_len);
2329 rsp_info = sense_data = sts->data;
2330 par_sense_len = sizeof(sts->data);
2331
2332 /* Check for overrun. */
2333 if (comp_status == CS_COMPLETE &&
2334 scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_OVER))
2335 comp_status = cpu_to_le16((uint16_t)CS_DATA_OVERRUN);
2336
2337 /*
2338 * Based on Host and scsi status generate status code for Linux
2339 */
2340 switch (le16_to_cpu(comp_status)) {
2341 case CS_COMPLETE:
2342 case CS_QUEUE_FULL:
2343 if (scsi_status == 0) {
2344 res = DID_OK << 16;
2345 break;
2346 }
2347 if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
2348 | (uint16_t)SS_RESIDUAL_OVER))) {
2349 resid = resid_len;
2350 scsi_set_resid(cp, resid);
2351
2352 if (!lscsi_status &&
2353 ((unsigned)(scsi_bufflen(cp) - resid) <
2354 cp->underflow)) {
2355 ql_dbg(ql_dbg_io, fcport->vha, 0x3050,
2356 "Mid-layer underflow "
2357 "detected (0x%x of 0x%x bytes).\n",
2358 resid, scsi_bufflen(cp));
2359
2360 res = DID_ERROR << 16;
2361 break;
2362 }
2363 }
2364 res = DID_OK << 16 | le16_to_cpu(lscsi_status);
2365
2366 if (lscsi_status ==
2367 cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
2368 ql_dbg(ql_dbg_io, fcport->vha, 0x3051,
2369 "QUEUE FULL detected.\n");
2370 break;
2371 }
2372 logit = 0;
2373 if (lscsi_status != cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
2374 break;
2375
2376 memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
2377 if (!(scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
2378 break;
2379
2380 qlafx00_handle_sense(sp, sense_data, par_sense_len, sense_len,
2381 rsp, res);
2382 break;
2383
2384 case CS_DATA_UNDERRUN:
2385 /* Use F/W calculated residual length. */
2386 if (IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
2387 resid = fw_resid_len;
2388 else
2389 resid = resid_len;
2390 scsi_set_resid(cp, resid);
2391 if (scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_UNDER)) {
2392 if ((IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
2393 && fw_resid_len != resid_len) {
2394 ql_dbg(ql_dbg_io, fcport->vha, 0x3052,
2395 "Dropped frame(s) detected "
2396 "(0x%x of 0x%x bytes).\n",
2397 resid, scsi_bufflen(cp));
2398
2399 res = DID_ERROR << 16 |
2400 le16_to_cpu(lscsi_status);
2401 goto check_scsi_status;
2402 }
2403
2404 if (!lscsi_status &&
2405 ((unsigned)(scsi_bufflen(cp) - resid) <
2406 cp->underflow)) {
2407 ql_dbg(ql_dbg_io, fcport->vha, 0x3053,
2408 "Mid-layer underflow "
2409 "detected (0x%x of 0x%x bytes, "
2410 "cp->underflow: 0x%x).\n",
2411 resid, scsi_bufflen(cp), cp->underflow);
2412
2413 res = DID_ERROR << 16;
2414 break;
2415 }
2416 } else if (lscsi_status !=
2417 cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL) &&
2418 lscsi_status != cpu_to_le16((uint16_t)SAM_STAT_BUSY)) {
2419 /*
2420 * scsi status of task set and busy are considered
2421 * to be task not completed.
2422 */
2423
2424 ql_dbg(ql_dbg_io, fcport->vha, 0x3054,
2425 "Dropped frame(s) detected (0x%x "
2426 "of 0x%x bytes).\n", resid,
2427 scsi_bufflen(cp));
2428
2429 res = DID_ERROR << 16 | le16_to_cpu(lscsi_status);
2430 goto check_scsi_status;
2431 } else {
2432 ql_dbg(ql_dbg_io, fcport->vha, 0x3055,
2433 "scsi_status: 0x%x, lscsi_status: 0x%x\n",
2434 scsi_status, lscsi_status);
2435 }
2436
2437 res = DID_OK << 16 | le16_to_cpu(lscsi_status);
2438 logit = 0;
2439
2440 check_scsi_status:
2441 /*
2442 * Check to see if SCSI Status is non zero. If so report SCSI
2443 * Status.
2444 */
2445 if (lscsi_status != 0) {
2446 if (lscsi_status ==
2447 cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
2448 ql_dbg(ql_dbg_io, fcport->vha, 0x3056,
2449 "QUEUE FULL detected.\n");
2450 logit = 1;
2451 break;
2452 }
2453 if (lscsi_status !=
2454 cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
2455 break;
2456
2457 memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
2458 if (!(scsi_status &
2459 cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
2460 break;
2461
2462 qlafx00_handle_sense(sp, sense_data, par_sense_len,
2463 sense_len, rsp, res);
2464 }
2465 break;
2466
2467 case CS_PORT_LOGGED_OUT:
2468 case CS_PORT_CONFIG_CHG:
2469 case CS_PORT_BUSY:
2470 case CS_INCOMPLETE:
2471 case CS_PORT_UNAVAILABLE:
2472 case CS_TIMEOUT:
2473 case CS_RESET:
2474
2475 /*
2476 * We are going to have the fc class block the rport
2477 * while we try to recover so instruct the mid layer
2478 * to requeue until the class decides how to handle this.
2479 */
2480 res = DID_TRANSPORT_DISRUPTED << 16;
2481
2482 ql_dbg(ql_dbg_io, fcport->vha, 0x3057,
2483 "Port down status: port-state=0x%x.\n",
2484 atomic_read(&fcport->state));
2485
2486 if (atomic_read(&fcport->state) == FCS_ONLINE)
2487 qla2x00_mark_device_lost(fcport->vha, fcport, 1);
2488 break;
2489
2490 case CS_ABORTED:
2491 res = DID_RESET << 16;
2492 break;
2493
2494 default:
2495 res = DID_ERROR << 16;
2496 break;
2497 }
2498
2499 if (logit)
2500 ql_dbg(ql_dbg_io, fcport->vha, 0x3058,
2501 "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%llu "
2502 "tgt_id: 0x%x lscsi_status: 0x%x cdb=%10phN len=0x%x "
2503 "rsp_info=%p resid=0x%x fw_resid=0x%x sense_len=0x%x, "
2504 "par_sense_len=0x%x, rsp_info_len=0x%x\n",
2505 comp_status, scsi_status, res, vha->host_no,
2506 cp->device->id, cp->device->lun, fcport->tgt_id,
2507 lscsi_status, cp->cmnd, scsi_bufflen(cp),
2508 rsp_info, resid_len, fw_resid_len, sense_len,
2509 par_sense_len, rsp_info_len);
2510
2511 if (rsp->status_srb == NULL)
2512 sp->done(sp, res);
2513 else
2514 WARN_ON_ONCE(true);
2515 }
2516
2517 /**
2518 * qlafx00_status_cont_entry() - Process a Status Continuations entry.
2519 * @rsp: response queue
2520 * @pkt: Entry pointer
2521 *
2522 * Extended sense data.
2523 */
2524 static void
2525 qlafx00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
2526 {
2527 uint8_t sense_sz = 0;
2528 struct qla_hw_data *ha = rsp->hw;
2529 struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
2530 srb_t *sp = rsp->status_srb;
2531 struct scsi_cmnd *cp;
2532 uint32_t sense_len;
2533 uint8_t *sense_ptr;
2534
2535 if (!sp) {
2536 ql_dbg(ql_dbg_io, vha, 0x3037,
2537 "no SP, sp = %p\n", sp);
2538 return;
2539 }
2540
2541 if (!GET_FW_SENSE_LEN(sp)) {
2542 ql_dbg(ql_dbg_io, vha, 0x304b,
2543 "no fw sense data, sp = %p\n", sp);
2544 return;
2545 }
2546 cp = GET_CMD_SP(sp);
2547 if (cp == NULL) {
2548 ql_log(ql_log_warn, vha, 0x303b,
2549 "cmd is NULL: already returned to OS (sp=%p).\n", sp);
2550
2551 rsp->status_srb = NULL;
2552 return;
2553 }
2554
2555 if (!GET_CMD_SENSE_LEN(sp)) {
2556 ql_dbg(ql_dbg_io, vha, 0x304c,
2557 "no sense data, sp = %p\n", sp);
2558 } else {
2559 sense_len = GET_CMD_SENSE_LEN(sp);
2560 sense_ptr = GET_CMD_SENSE_PTR(sp);
2561 ql_dbg(ql_dbg_io, vha, 0x304f,
2562 "sp=%p sense_len=0x%x sense_ptr=%p.\n",
2563 sp, sense_len, sense_ptr);
2564
2565 if (sense_len > sizeof(pkt->data))
2566 sense_sz = sizeof(pkt->data);
2567 else
2568 sense_sz = sense_len;
2569
2570 /* Move sense data. */
2571 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304e,
2572 pkt, sizeof(*pkt));
2573 memcpy(sense_ptr, pkt->data, sense_sz);
2574 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304a,
2575 sense_ptr, sense_sz);
2576
2577 sense_len -= sense_sz;
2578 sense_ptr += sense_sz;
2579
2580 SET_CMD_SENSE_PTR(sp, sense_ptr);
2581 SET_CMD_SENSE_LEN(sp, sense_len);
2582 }
2583 sense_len = GET_FW_SENSE_LEN(sp);
2584 sense_len = (sense_len > sizeof(pkt->data)) ?
2585 (sense_len - sizeof(pkt->data)) : 0;
2586 SET_FW_SENSE_LEN(sp, sense_len);
2587
2588 /* Place command on done queue. */
2589 if (sense_len == 0) {
2590 rsp->status_srb = NULL;
2591 sp->done(sp, cp->result);
2592 } else {
2593 WARN_ON_ONCE(true);
2594 }
2595 }
2596
2597 /**
2598 * qlafx00_multistatus_entry() - Process Multi response queue entries.
2599 * @vha: SCSI driver HA context
2600 * @rsp: response queue
2601 * @pkt: received packet
2602 */
2603 static void
2604 qlafx00_multistatus_entry(struct scsi_qla_host *vha,
2605 struct rsp_que *rsp, void *pkt)
2606 {
2607 srb_t *sp;
2608 struct multi_sts_entry_fx00 *stsmfx;
2609 struct qla_hw_data *ha = vha->hw;
2610 uint32_t handle, hindex, handle_count, i;
2611 uint16_t que;
2612 struct req_que *req;
2613 __le32 *handle_ptr;
2614
2615 stsmfx = (struct multi_sts_entry_fx00 *) pkt;
2616
2617 handle_count = stsmfx->handle_count;
2618
2619 if (handle_count > MAX_HANDLE_COUNT) {
2620 ql_dbg(ql_dbg_io, vha, 0x3035,
2621 "Invalid handle count (0x%x).\n", handle_count);
2622 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2623 qla2xxx_wake_dpc(vha);
2624 return;
2625 }
2626
2627 handle_ptr = &stsmfx->handles[0];
2628
2629 for (i = 0; i < handle_count; i++) {
2630 hindex = le32_to_cpu(*handle_ptr);
2631 handle = LSW(hindex);
2632 que = MSW(hindex);
2633 req = ha->req_q_map[que];
2634
2635 /* Validate handle. */
2636 if (handle < req->num_outstanding_cmds)
2637 sp = req->outstanding_cmds[handle];
2638 else
2639 sp = NULL;
2640
2641 if (sp == NULL) {
2642 ql_dbg(ql_dbg_io, vha, 0x3044,
2643 "Invalid status handle (0x%x).\n", handle);
2644 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2645 qla2xxx_wake_dpc(vha);
2646 return;
2647 }
2648 qla2x00_process_completed_request(vha, req, handle);
2649 handle_ptr++;
2650 }
2651 }
2652
2653 /**
2654 * qlafx00_error_entry() - Process an error entry.
2655 * @vha: SCSI driver HA context
2656 * @rsp: response queue
2657 * @pkt: Entry pointer
2658 */
2659 static void
2660 qlafx00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp,
2661 struct sts_entry_fx00 *pkt)
2662 {
2663 srb_t *sp;
2664 struct qla_hw_data *ha = vha->hw;
2665 const char func[] = "ERROR-IOCB";
2666 uint16_t que = 0;
2667 struct req_que *req = NULL;
2668 int res = DID_ERROR << 16;
2669
2670 req = ha->req_q_map[que];
2671
2672 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2673 if (sp) {
2674 sp->done(sp, res);
2675 return;
2676 }
2677
2678 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2679 qla2xxx_wake_dpc(vha);
2680 }
2681
2682 /**
2683 * qlafx00_process_response_queue() - Process response queue entries.
2684 * @vha: SCSI driver HA context
2685 * @rsp: response queue
2686 */
2687 static void
2688 qlafx00_process_response_queue(struct scsi_qla_host *vha,
2689 struct rsp_que *rsp)
2690 {
2691 struct sts_entry_fx00 *pkt;
2692 response_t *lptr;
2693 uint16_t lreq_q_in = 0;
2694 uint16_t lreq_q_out = 0;
2695
2696 lreq_q_in = rd_reg_dword(rsp->rsp_q_in);
2697 lreq_q_out = rsp->ring_index;
2698
2699 while (lreq_q_in != lreq_q_out) {
2700 lptr = rsp->ring_ptr;
2701 memcpy_fromio(rsp->rsp_pkt, (void __iomem *)lptr,
2702 sizeof(rsp->rsp_pkt));
2703 pkt = (struct sts_entry_fx00 *)rsp->rsp_pkt;
2704
2705 rsp->ring_index++;
2706 lreq_q_out++;
2707 if (rsp->ring_index == rsp->length) {
2708 lreq_q_out = 0;
2709 rsp->ring_index = 0;
2710 rsp->ring_ptr = rsp->ring;
2711 } else {
2712 rsp->ring_ptr++;
2713 }
2714
2715 if (pkt->entry_status != 0 &&
2716 pkt->entry_type != IOCTL_IOSB_TYPE_FX00) {
2717 ql_dbg(ql_dbg_async, vha, 0x507f,
2718 "type of error status in response: 0x%x\n",
2719 pkt->entry_status);
2720 qlafx00_error_entry(vha, rsp,
2721 (struct sts_entry_fx00 *)pkt);
2722 continue;
2723 }
2724
2725 switch (pkt->entry_type) {
2726 case STATUS_TYPE_FX00:
2727 qlafx00_status_entry(vha, rsp, pkt);
2728 break;
2729
2730 case STATUS_CONT_TYPE_FX00:
2731 qlafx00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
2732 break;
2733
2734 case MULTI_STATUS_TYPE_FX00:
2735 qlafx00_multistatus_entry(vha, rsp, pkt);
2736 break;
2737
2738 case ABORT_IOCB_TYPE_FX00:
2739 qlafx00_abort_iocb_entry(vha, rsp->req,
2740 (struct abort_iocb_entry_fx00 *)pkt);
2741 break;
2742
2743 case IOCTL_IOSB_TYPE_FX00:
2744 qlafx00_ioctl_iosb_entry(vha, rsp->req,
2745 (struct ioctl_iocb_entry_fx00 *)pkt);
2746 break;
2747 default:
2748 /* Type Not Supported. */
2749 ql_dbg(ql_dbg_async, vha, 0x5081,
2750 "Received unknown response pkt type %x "
2751 "entry status=%x.\n",
2752 pkt->entry_type, pkt->entry_status);
2753 break;
2754 }
2755 }
2756
2757 /* Adjust ring index */
2758 wrt_reg_dword(rsp->rsp_q_out, rsp->ring_index);
2759 }
2760
2761 /**
2762 * qlafx00_async_event() - Process aynchronous events.
2763 * @vha: SCSI driver HA context
2764 */
2765 static void
2766 qlafx00_async_event(scsi_qla_host_t *vha)
2767 {
2768 struct qla_hw_data *ha = vha->hw;
2769 struct device_reg_fx00 __iomem *reg;
2770 int data_size = 1;
2771
2772 reg = &ha->iobase->ispfx00;
2773 /* Setup to process RIO completion. */
2774 switch (ha->aenmb[0]) {
2775 case QLAFX00_MBA_SYSTEM_ERR: /* System Error */
2776 ql_log(ql_log_warn, vha, 0x5079,
2777 "ISP System Error - mbx1=%x\n", ha->aenmb[0]);
2778 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2779 break;
2780
2781 case QLAFX00_MBA_SHUTDOWN_RQSTD: /* Shutdown requested */
2782 ql_dbg(ql_dbg_async, vha, 0x5076,
2783 "Asynchronous FW shutdown requested.\n");
2784 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2785 qla2xxx_wake_dpc(vha);
2786 break;
2787
2788 case QLAFX00_MBA_PORT_UPDATE: /* Port database update */
2789 ha->aenmb[1] = rd_reg_dword(&reg->aenmailbox1);
2790 ha->aenmb[2] = rd_reg_dword(&reg->aenmailbox2);
2791 ha->aenmb[3] = rd_reg_dword(&reg->aenmailbox3);
2792 ql_dbg(ql_dbg_async, vha, 0x5077,
2793 "Asynchronous port Update received "
2794 "aenmb[0]: %x, aenmb[1]: %x, aenmb[2]: %x, aenmb[3]: %x\n",
2795 ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3]);
2796 data_size = 4;
2797 break;
2798
2799 case QLAFX00_MBA_TEMP_OVER: /* Over temperature event */
2800 ql_log(ql_log_info, vha, 0x5085,
2801 "Asynchronous over temperature event received "
2802 "aenmb[0]: %x\n",
2803 ha->aenmb[0]);
2804 break;
2805
2806 case QLAFX00_MBA_TEMP_NORM: /* Normal temperature event */
2807 ql_log(ql_log_info, vha, 0x5086,
2808 "Asynchronous normal temperature event received "
2809 "aenmb[0]: %x\n",
2810 ha->aenmb[0]);
2811 break;
2812
2813 case QLAFX00_MBA_TEMP_CRIT: /* Critical temperature event */
2814 ql_log(ql_log_info, vha, 0x5083,
2815 "Asynchronous critical temperature event received "
2816 "aenmb[0]: %x\n",
2817 ha->aenmb[0]);
2818 break;
2819
2820 default:
2821 ha->aenmb[1] = rd_reg_dword(&reg->aenmailbox1);
2822 ha->aenmb[2] = rd_reg_dword(&reg->aenmailbox2);
2823 ha->aenmb[3] = rd_reg_dword(&reg->aenmailbox3);
2824 ha->aenmb[4] = rd_reg_dword(&reg->aenmailbox4);
2825 ha->aenmb[5] = rd_reg_dword(&reg->aenmailbox5);
2826 ha->aenmb[6] = rd_reg_dword(&reg->aenmailbox6);
2827 ha->aenmb[7] = rd_reg_dword(&reg->aenmailbox7);
2828 ql_dbg(ql_dbg_async, vha, 0x5078,
2829 "AEN:%04x %04x %04x %04x :%04x %04x %04x %04x\n",
2830 ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3],
2831 ha->aenmb[4], ha->aenmb[5], ha->aenmb[6], ha->aenmb[7]);
2832 break;
2833 }
2834 qlafx00_post_aenfx_work(vha, ha->aenmb[0],
2835 (uint32_t *)ha->aenmb, data_size);
2836 }
2837
2838 /**
2839 * qlafx00_mbx_completion() - Process mailbox command completions.
2840 * @vha: SCSI driver HA context
2841 * @mb0: value to be written into mailbox register 0
2842 */
2843 static void
2844 qlafx00_mbx_completion(scsi_qla_host_t *vha, uint32_t mb0)
2845 {
2846 uint16_t cnt;
2847 __le32 __iomem *wptr;
2848 struct qla_hw_data *ha = vha->hw;
2849 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
2850
2851 if (!ha->mcp32)
2852 ql_dbg(ql_dbg_async, vha, 0x507e, "MBX pointer ERROR.\n");
2853
2854 /* Load return mailbox registers. */
2855 ha->flags.mbox_int = 1;
2856 ha->mailbox_out32[0] = mb0;
2857 wptr = &reg->mailbox17;
2858
2859 for (cnt = 1; cnt < ha->mbx_count; cnt++) {
2860 ha->mailbox_out32[cnt] = rd_reg_dword(wptr);
2861 wptr++;
2862 }
2863 }
2864
2865 /**
2866 * qlafx00_intr_handler() - Process interrupts for the ISPFX00.
2867 * @irq: interrupt number
2868 * @dev_id: SCSI driver HA context
2869 *
2870 * Called by system whenever the host adapter generates an interrupt.
2871 *
2872 * Returns handled flag.
2873 */
2874 irqreturn_t
2875 qlafx00_intr_handler(int irq, void *dev_id)
2876 {
2877 scsi_qla_host_t *vha;
2878 struct qla_hw_data *ha;
2879 struct device_reg_fx00 __iomem *reg;
2880 int status;
2881 unsigned long iter;
2882 uint32_t stat;
2883 uint32_t mb[8];
2884 struct rsp_que *rsp;
2885 unsigned long flags;
2886 uint32_t clr_intr = 0;
2887 uint32_t intr_stat = 0;
2888
2889 rsp = (struct rsp_que *) dev_id;
2890 if (!rsp) {
2891 ql_log(ql_log_info, NULL, 0x507d,
2892 "%s: NULL response queue pointer.\n", __func__);
2893 return IRQ_NONE;
2894 }
2895
2896 ha = rsp->hw;
2897 reg = &ha->iobase->ispfx00;
2898 status = 0;
2899
2900 if (unlikely(pci_channel_offline(ha->pdev)))
2901 return IRQ_HANDLED;
2902
2903 spin_lock_irqsave(&ha->hardware_lock, flags);
2904 vha = pci_get_drvdata(ha->pdev);
2905 for (iter = 50; iter--; clr_intr = 0) {
2906 stat = QLAFX00_RD_INTR_REG(ha);
2907 if (qla2x00_check_reg32_for_disconnect(vha, stat))
2908 break;
2909 intr_stat = stat & QLAFX00_HST_INT_STS_BITS;
2910 if (!intr_stat)
2911 break;
2912
2913 if (stat & QLAFX00_INTR_MB_CMPLT) {
2914 mb[0] = rd_reg_dword(&reg->mailbox16);
2915 qlafx00_mbx_completion(vha, mb[0]);
2916 status |= MBX_INTERRUPT;
2917 clr_intr |= QLAFX00_INTR_MB_CMPLT;
2918 }
2919 if (intr_stat & QLAFX00_INTR_ASYNC_CMPLT) {
2920 ha->aenmb[0] = rd_reg_dword(&reg->aenmailbox0);
2921 qlafx00_async_event(vha);
2922 clr_intr |= QLAFX00_INTR_ASYNC_CMPLT;
2923 }
2924 if (intr_stat & QLAFX00_INTR_RSP_CMPLT) {
2925 qlafx00_process_response_queue(vha, rsp);
2926 clr_intr |= QLAFX00_INTR_RSP_CMPLT;
2927 }
2928
2929 QLAFX00_CLR_INTR_REG(ha, clr_intr);
2930 QLAFX00_RD_INTR_REG(ha);
2931 }
2932
2933 qla2x00_handle_mbx_completion(ha, status);
2934 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2935
2936 return IRQ_HANDLED;
2937 }
2938
2939 /** QLAFX00 specific IOCB implementation functions */
2940
2941 static inline cont_a64_entry_t *
2942 qlafx00_prep_cont_type1_iocb(struct req_que *req,
2943 cont_a64_entry_t *lcont_pkt)
2944 {
2945 cont_a64_entry_t *cont_pkt;
2946
2947 /* Adjust ring index. */
2948 req->ring_index++;
2949 if (req->ring_index == req->length) {
2950 req->ring_index = 0;
2951 req->ring_ptr = req->ring;
2952 } else {
2953 req->ring_ptr++;
2954 }
2955
2956 cont_pkt = (cont_a64_entry_t *)req->ring_ptr;
2957
2958 /* Load packet defaults. */
2959 lcont_pkt->entry_type = CONTINUE_A64_TYPE_FX00;
2960
2961 return cont_pkt;
2962 }
2963
2964 static inline void
2965 qlafx00_build_scsi_iocbs(srb_t *sp, struct cmd_type_7_fx00 *cmd_pkt,
2966 uint16_t tot_dsds, struct cmd_type_7_fx00 *lcmd_pkt)
2967 {
2968 uint16_t avail_dsds;
2969 struct dsd64 *cur_dsd;
2970 scsi_qla_host_t *vha;
2971 struct scsi_cmnd *cmd;
2972 struct scatterlist *sg;
2973 int i, cont;
2974 struct req_que *req;
2975 cont_a64_entry_t lcont_pkt;
2976 cont_a64_entry_t *cont_pkt;
2977
2978 vha = sp->vha;
2979 req = vha->req;
2980
2981 cmd = GET_CMD_SP(sp);
2982 cont = 0;
2983 cont_pkt = NULL;
2984
2985 /* Update entry type to indicate Command Type 3 IOCB */
2986 lcmd_pkt->entry_type = FX00_COMMAND_TYPE_7;
2987
2988 /* No data transfer */
2989 if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) {
2990 lcmd_pkt->byte_count = cpu_to_le32(0);
2991 return;
2992 }
2993
2994 /* Set transfer direction */
2995 if (cmd->sc_data_direction == DMA_TO_DEVICE) {
2996 lcmd_pkt->cntrl_flags = TMF_WRITE_DATA;
2997 vha->qla_stats.output_bytes += scsi_bufflen(cmd);
2998 } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) {
2999 lcmd_pkt->cntrl_flags = TMF_READ_DATA;
3000 vha->qla_stats.input_bytes += scsi_bufflen(cmd);
3001 }
3002
3003 /* One DSD is available in the Command Type 3 IOCB */
3004 avail_dsds = 1;
3005 cur_dsd = &lcmd_pkt->dsd;
3006
3007 /* Load data segments */
3008 scsi_for_each_sg(cmd, sg, tot_dsds, i) {
3009 /* Allocate additional continuation packets? */
3010 if (avail_dsds == 0) {
3011 /*
3012 * Five DSDs are available in the Continuation
3013 * Type 1 IOCB.
3014 */
3015 memset(&lcont_pkt, 0, REQUEST_ENTRY_SIZE);
3016 cont_pkt =
3017 qlafx00_prep_cont_type1_iocb(req, &lcont_pkt);
3018 cur_dsd = lcont_pkt.dsd;
3019 avail_dsds = 5;
3020 cont = 1;
3021 }
3022
3023 append_dsd64(&cur_dsd, sg);
3024 avail_dsds--;
3025 if (avail_dsds == 0 && cont == 1) {
3026 cont = 0;
3027 memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
3028 sizeof(lcont_pkt));
3029 }
3030
3031 }
3032 if (avail_dsds != 0 && cont == 1) {
3033 memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
3034 sizeof(lcont_pkt));
3035 }
3036 }
3037
3038 /**
3039 * qlafx00_start_scsi() - Send a SCSI command to the ISP
3040 * @sp: command to send to the ISP
3041 *
3042 * Returns non-zero if a failure occurred, else zero.
3043 */
3044 int
3045 qlafx00_start_scsi(srb_t *sp)
3046 {
3047 int nseg;
3048 unsigned long flags;
3049 uint32_t handle;
3050 uint16_t cnt;
3051 uint16_t req_cnt;
3052 uint16_t tot_dsds;
3053 struct req_que *req = NULL;
3054 struct rsp_que *rsp = NULL;
3055 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
3056 struct scsi_qla_host *vha = sp->vha;
3057 struct qla_hw_data *ha = vha->hw;
3058 struct cmd_type_7_fx00 *cmd_pkt;
3059 struct cmd_type_7_fx00 lcmd_pkt;
3060 struct scsi_lun llun;
3061
3062 /* Setup device pointers. */
3063 rsp = ha->rsp_q_map[0];
3064 req = vha->req;
3065
3066 /* So we know we haven't pci_map'ed anything yet */
3067 tot_dsds = 0;
3068
3069 /* Acquire ring specific lock */
3070 spin_lock_irqsave(&ha->hardware_lock, flags);
3071
3072 handle = qla2xxx_get_next_handle(req);
3073 if (handle == 0)
3074 goto queuing_error;
3075
3076 /* Map the sg table so we have an accurate count of sg entries needed */
3077 if (scsi_sg_count(cmd)) {
3078 nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd),
3079 scsi_sg_count(cmd), cmd->sc_data_direction);
3080 if (unlikely(!nseg))
3081 goto queuing_error;
3082 } else
3083 nseg = 0;
3084
3085 tot_dsds = nseg;
3086 req_cnt = qla24xx_calc_iocbs(vha, tot_dsds);
3087 if (req->cnt < (req_cnt + 2)) {
3088 cnt = rd_reg_dword_relaxed(req->req_q_out);
3089
3090 if (req->ring_index < cnt)
3091 req->cnt = cnt - req->ring_index;
3092 else
3093 req->cnt = req->length -
3094 (req->ring_index - cnt);
3095 if (req->cnt < (req_cnt + 2))
3096 goto queuing_error;
3097 }
3098
3099 /* Build command packet. */
3100 req->current_outstanding_cmd = handle;
3101 req->outstanding_cmds[handle] = sp;
3102 sp->handle = handle;
3103 cmd->host_scribble = (unsigned char *)(unsigned long)handle;
3104 req->cnt -= req_cnt;
3105
3106 cmd_pkt = (struct cmd_type_7_fx00 *)req->ring_ptr;
3107
3108 memset(&lcmd_pkt, 0, REQUEST_ENTRY_SIZE);
3109
3110 lcmd_pkt.handle = make_handle(req->id, sp->handle);
3111 lcmd_pkt.reserved_0 = 0;
3112 lcmd_pkt.port_path_ctrl = 0;
3113 lcmd_pkt.reserved_1 = 0;
3114 lcmd_pkt.dseg_count = cpu_to_le16(tot_dsds);
3115 lcmd_pkt.tgt_idx = cpu_to_le16(sp->fcport->tgt_id);
3116
3117 int_to_scsilun(cmd->device->lun, &llun);
3118 host_to_adap((uint8_t *)&llun, (uint8_t *)&lcmd_pkt.lun,
3119 sizeof(lcmd_pkt.lun));
3120
3121 /* Load SCSI command packet. */
3122 host_to_adap(cmd->cmnd, lcmd_pkt.fcp_cdb, sizeof(lcmd_pkt.fcp_cdb));
3123 lcmd_pkt.byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd));
3124
3125 /* Build IOCB segments */
3126 qlafx00_build_scsi_iocbs(sp, cmd_pkt, tot_dsds, &lcmd_pkt);
3127
3128 /* Set total data segment count. */
3129 lcmd_pkt.entry_count = (uint8_t)req_cnt;
3130
3131 /* Specify response queue number where completion should happen */
3132 lcmd_pkt.entry_status = (uint8_t) rsp->id;
3133
3134 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302e,
3135 cmd->cmnd, cmd->cmd_len);
3136 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3032,
3137 &lcmd_pkt, sizeof(lcmd_pkt));
3138
3139 memcpy_toio((void __iomem *)cmd_pkt, &lcmd_pkt, REQUEST_ENTRY_SIZE);
3140 wmb();
3141
3142 /* Adjust ring index. */
3143 req->ring_index++;
3144 if (req->ring_index == req->length) {
3145 req->ring_index = 0;
3146 req->ring_ptr = req->ring;
3147 } else
3148 req->ring_ptr++;
3149
3150 sp->flags |= SRB_DMA_VALID;
3151
3152 /* Set chip new ring index. */
3153 wrt_reg_dword(req->req_q_in, req->ring_index);
3154 QLAFX00_SET_HST_INTR(ha, ha->rqstq_intr_code);
3155
3156 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3157 return QLA_SUCCESS;
3158
3159 queuing_error:
3160 if (tot_dsds)
3161 scsi_dma_unmap(cmd);
3162
3163 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3164
3165 return QLA_FUNCTION_FAILED;
3166 }
3167
3168 void
3169 qlafx00_tm_iocb(srb_t *sp, struct tsk_mgmt_entry_fx00 *ptm_iocb)
3170 {
3171 struct srb_iocb *fxio = &sp->u.iocb_cmd;
3172 scsi_qla_host_t *vha = sp->vha;
3173 struct req_que *req = vha->req;
3174 struct tsk_mgmt_entry_fx00 tm_iocb;
3175 struct scsi_lun llun;
3176
3177 memset(&tm_iocb, 0, sizeof(struct tsk_mgmt_entry_fx00));
3178 tm_iocb.entry_type = TSK_MGMT_IOCB_TYPE_FX00;
3179 tm_iocb.entry_count = 1;
3180 tm_iocb.handle = make_handle(req->id, sp->handle);
3181 tm_iocb.reserved_0 = 0;
3182 tm_iocb.tgt_id = cpu_to_le16(sp->fcport->tgt_id);
3183 tm_iocb.control_flags = cpu_to_le32(fxio->u.tmf.flags);
3184 if (tm_iocb.control_flags == cpu_to_le32((uint32_t)TCF_LUN_RESET)) {
3185 int_to_scsilun(fxio->u.tmf.lun, &llun);
3186 host_to_adap((uint8_t *)&llun, (uint8_t *)&tm_iocb.lun,
3187 sizeof(struct scsi_lun));
3188 }
3189
3190 memcpy(ptm_iocb, &tm_iocb,
3191 sizeof(struct tsk_mgmt_entry_fx00));
3192 wmb();
3193 }
3194
3195 void
3196 qlafx00_abort_iocb(srb_t *sp, struct abort_iocb_entry_fx00 *pabt_iocb)
3197 {
3198 struct srb_iocb *fxio = &sp->u.iocb_cmd;
3199 scsi_qla_host_t *vha = sp->vha;
3200 struct req_que *req = vha->req;
3201 struct abort_iocb_entry_fx00 abt_iocb;
3202
3203 memset(&abt_iocb, 0, sizeof(struct abort_iocb_entry_fx00));
3204 abt_iocb.entry_type = ABORT_IOCB_TYPE_FX00;
3205 abt_iocb.entry_count = 1;
3206 abt_iocb.handle = make_handle(req->id, sp->handle);
3207 abt_iocb.abort_handle = make_handle(req->id, fxio->u.abt.cmd_hndl);
3208 abt_iocb.tgt_id_sts = cpu_to_le16(sp->fcport->tgt_id);
3209 abt_iocb.req_que_no = cpu_to_le16(req->id);
3210
3211 memcpy(pabt_iocb, &abt_iocb,
3212 sizeof(struct abort_iocb_entry_fx00));
3213 wmb();
3214 }
3215
3216 void
3217 qlafx00_fxdisc_iocb(srb_t *sp, struct fxdisc_entry_fx00 *pfxiocb)
3218 {
3219 struct srb_iocb *fxio = &sp->u.iocb_cmd;
3220 struct qla_mt_iocb_rqst_fx00 *piocb_rqst;
3221 struct bsg_job *bsg_job;
3222 struct fc_bsg_request *bsg_request;
3223 struct fxdisc_entry_fx00 fx_iocb;
3224 uint8_t entry_cnt = 1;
3225
3226 memset(&fx_iocb, 0, sizeof(struct fxdisc_entry_fx00));
3227 fx_iocb.entry_type = FX00_IOCB_TYPE;
3228 fx_iocb.handle = sp->handle;
3229 fx_iocb.entry_count = entry_cnt;
3230
3231 if (sp->type == SRB_FXIOCB_DCMD) {
3232 fx_iocb.func_num =
3233 sp->u.iocb_cmd.u.fxiocb.req_func_type;
3234 fx_iocb.adapid = fxio->u.fxiocb.adapter_id;
3235 fx_iocb.adapid_hi = fxio->u.fxiocb.adapter_id_hi;
3236 fx_iocb.reserved_0 = fxio->u.fxiocb.reserved_0;
3237 fx_iocb.reserved_1 = fxio->u.fxiocb.reserved_1;
3238 fx_iocb.dataword_extra = fxio->u.fxiocb.req_data_extra;
3239
3240 if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
3241 fx_iocb.req_dsdcnt = cpu_to_le16(1);
3242 fx_iocb.req_xfrcnt =
3243 cpu_to_le16(fxio->u.fxiocb.req_len);
3244 put_unaligned_le64(fxio->u.fxiocb.req_dma_handle,
3245 &fx_iocb.dseg_rq[0].address);
3246 fx_iocb.dseg_rq[0].length =
3247 cpu_to_le32(fxio->u.fxiocb.req_len);
3248 }
3249
3250 if (fxio->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
3251 fx_iocb.rsp_dsdcnt = cpu_to_le16(1);
3252 fx_iocb.rsp_xfrcnt =
3253 cpu_to_le16(fxio->u.fxiocb.rsp_len);
3254 put_unaligned_le64(fxio->u.fxiocb.rsp_dma_handle,
3255 &fx_iocb.dseg_rsp[0].address);
3256 fx_iocb.dseg_rsp[0].length =
3257 cpu_to_le32(fxio->u.fxiocb.rsp_len);
3258 }
3259
3260 if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DWRD_VALID) {
3261 fx_iocb.dataword = fxio->u.fxiocb.req_data;
3262 }
3263 fx_iocb.flags = fxio->u.fxiocb.flags;
3264 } else {
3265 struct scatterlist *sg;
3266
3267 bsg_job = sp->u.bsg_job;
3268 bsg_request = bsg_job->request;
3269 piocb_rqst = (struct qla_mt_iocb_rqst_fx00 *)
3270 &bsg_request->rqst_data.h_vendor.vendor_cmd[1];
3271
3272 fx_iocb.func_num = piocb_rqst->func_type;
3273 fx_iocb.adapid = piocb_rqst->adapid;
3274 fx_iocb.adapid_hi = piocb_rqst->adapid_hi;
3275 fx_iocb.reserved_0 = piocb_rqst->reserved_0;
3276 fx_iocb.reserved_1 = piocb_rqst->reserved_1;
3277 fx_iocb.dataword_extra = piocb_rqst->dataword_extra;
3278 fx_iocb.dataword = piocb_rqst->dataword;
3279 fx_iocb.req_xfrcnt = piocb_rqst->req_len;
3280 fx_iocb.rsp_xfrcnt = piocb_rqst->rsp_len;
3281
3282 if (piocb_rqst->flags & SRB_FXDISC_REQ_DMA_VALID) {
3283 int avail_dsds, tot_dsds;
3284 cont_a64_entry_t lcont_pkt;
3285 cont_a64_entry_t *cont_pkt = NULL;
3286 struct dsd64 *cur_dsd;
3287 int index = 0, cont = 0;
3288
3289 fx_iocb.req_dsdcnt =
3290 cpu_to_le16(bsg_job->request_payload.sg_cnt);
3291 tot_dsds =
3292 bsg_job->request_payload.sg_cnt;
3293 cur_dsd = &fx_iocb.dseg_rq[0];
3294 avail_dsds = 1;
3295 for_each_sg(bsg_job->request_payload.sg_list, sg,
3296 tot_dsds, index) {
3297 /* Allocate additional continuation packets? */
3298 if (avail_dsds == 0) {
3299 /*
3300 * Five DSDs are available in the Cont.
3301 * Type 1 IOCB.
3302 */
3303 memset(&lcont_pkt, 0,
3304 REQUEST_ENTRY_SIZE);
3305 cont_pkt =
3306 qlafx00_prep_cont_type1_iocb(
3307 sp->vha->req, &lcont_pkt);
3308 cur_dsd = lcont_pkt.dsd;
3309 avail_dsds = 5;
3310 cont = 1;
3311 entry_cnt++;
3312 }
3313
3314 append_dsd64(&cur_dsd, sg);
3315 avail_dsds--;
3316
3317 if (avail_dsds == 0 && cont == 1) {
3318 cont = 0;
3319 memcpy_toio(
3320 (void __iomem *)cont_pkt,
3321 &lcont_pkt, REQUEST_ENTRY_SIZE);
3322 ql_dump_buffer(
3323 ql_dbg_user + ql_dbg_verbose,
3324 sp->vha, 0x3042,
3325 (uint8_t *)&lcont_pkt,
3326 REQUEST_ENTRY_SIZE);
3327 }
3328 }
3329 if (avail_dsds != 0 && cont == 1) {
3330 memcpy_toio((void __iomem *)cont_pkt,
3331 &lcont_pkt, REQUEST_ENTRY_SIZE);
3332 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
3333 sp->vha, 0x3043,
3334 (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
3335 }
3336 }
3337
3338 if (piocb_rqst->flags & SRB_FXDISC_RESP_DMA_VALID) {
3339 int avail_dsds, tot_dsds;
3340 cont_a64_entry_t lcont_pkt;
3341 cont_a64_entry_t *cont_pkt = NULL;
3342 struct dsd64 *cur_dsd;
3343 int index = 0, cont = 0;
3344
3345 fx_iocb.rsp_dsdcnt =
3346 cpu_to_le16(bsg_job->reply_payload.sg_cnt);
3347 tot_dsds = bsg_job->reply_payload.sg_cnt;
3348 cur_dsd = &fx_iocb.dseg_rsp[0];
3349 avail_dsds = 1;
3350
3351 for_each_sg(bsg_job->reply_payload.sg_list, sg,
3352 tot_dsds, index) {
3353 /* Allocate additional continuation packets? */
3354 if (avail_dsds == 0) {
3355 /*
3356 * Five DSDs are available in the Cont.
3357 * Type 1 IOCB.
3358 */
3359 memset(&lcont_pkt, 0,
3360 REQUEST_ENTRY_SIZE);
3361 cont_pkt =
3362 qlafx00_prep_cont_type1_iocb(
3363 sp->vha->req, &lcont_pkt);
3364 cur_dsd = lcont_pkt.dsd;
3365 avail_dsds = 5;
3366 cont = 1;
3367 entry_cnt++;
3368 }
3369
3370 append_dsd64(&cur_dsd, sg);
3371 avail_dsds--;
3372
3373 if (avail_dsds == 0 && cont == 1) {
3374 cont = 0;
3375 memcpy_toio((void __iomem *)cont_pkt,
3376 &lcont_pkt,
3377 REQUEST_ENTRY_SIZE);
3378 ql_dump_buffer(
3379 ql_dbg_user + ql_dbg_verbose,
3380 sp->vha, 0x3045,
3381 (uint8_t *)&lcont_pkt,
3382 REQUEST_ENTRY_SIZE);
3383 }
3384 }
3385 if (avail_dsds != 0 && cont == 1) {
3386 memcpy_toio((void __iomem *)cont_pkt,
3387 &lcont_pkt, REQUEST_ENTRY_SIZE);
3388 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
3389 sp->vha, 0x3046,
3390 (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
3391 }
3392 }
3393
3394 if (piocb_rqst->flags & SRB_FXDISC_REQ_DWRD_VALID)
3395 fx_iocb.dataword = piocb_rqst->dataword;
3396 fx_iocb.flags = piocb_rqst->flags;
3397 fx_iocb.entry_count = entry_cnt;
3398 }
3399
3400 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
3401 sp->vha, 0x3047, &fx_iocb, sizeof(fx_iocb));
3402
3403 memcpy_toio((void __iomem *)pfxiocb, &fx_iocb, sizeof(fx_iocb));
3404 wmb();
3405 }
Kernel DRM miscellaneous fixes and cross-tree changes