1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright 2014 Cisco Systems, Inc. All rights reserved.
4 #include <linux/kernel.h>
5 #include <linux/errno.h>
6 #include <linux/types.h>
8 #include <linux/delay.h>
9 #include <linux/if_ether.h>
10 #include <linux/slab.h>
11 #include "vnic_resource.h"
12 #include "vnic_devcmd.h"
14 #include "vnic_stats.h"
17 #define VNIC_DVCMD_TMO 10000 /* Devcmd Timeout value */
18 #define VNIC_NOTIFY_INTR_MASK 0x0000ffff00000000ULL
20 struct devcmd2_controller
{
21 struct vnic_wq_ctrl __iomem
*wq_ctrl
;
22 struct vnic_dev_ring results_ring
;
24 struct vnic_devcmd2
*cmd_ring
;
25 struct devcmd2_result
*result
;
39 struct vnic_res res
[RES_TYPE_MAX
];
40 enum vnic_dev_intr_mode intr_mode
;
41 struct vnic_devcmd __iomem
*devcmd
;
42 struct vnic_devcmd_notify
*notify
;
43 struct vnic_devcmd_notify notify_copy
;
46 dma_addr_t linkstatus_pa
;
47 struct vnic_stats
*stats
;
49 struct vnic_devcmd_fw_info
*fw_info
;
50 dma_addr_t fw_info_pa
;
51 u64 args
[VNIC_DEVCMD_NARGS
];
52 struct devcmd2_controller
*devcmd2
;
54 int (*devcmd_rtn
)(struct vnic_dev
*vdev
, enum vnic_devcmd_cmd cmd
,
58 #define VNIC_MAX_RES_HDR_SIZE \
59 (sizeof(struct vnic_resource_header) + \
60 sizeof(struct vnic_resource) * RES_TYPE_MAX)
61 #define VNIC_RES_STRIDE 128
63 void *svnic_dev_priv(struct vnic_dev
*vdev
)
68 static int vnic_dev_discover_res(struct vnic_dev
*vdev
,
69 struct vnic_dev_bar
*bar
, unsigned int num_bars
)
71 struct vnic_resource_header __iomem
*rh
;
72 struct vnic_resource __iomem
*r
;
78 if (bar
->len
< VNIC_MAX_RES_HDR_SIZE
) {
79 pr_err("vNIC BAR0 res hdr length error\n");
86 pr_err("vNIC BAR0 res hdr not mem-mapped\n");
91 if (ioread32(&rh
->magic
) != VNIC_RES_MAGIC
||
92 ioread32(&rh
->version
) != VNIC_RES_VERSION
) {
93 pr_err("vNIC BAR0 res magic/version error exp (%lx/%lx) curr (%x/%x)\n",
94 VNIC_RES_MAGIC
, VNIC_RES_VERSION
,
95 ioread32(&rh
->magic
), ioread32(&rh
->version
));
100 r
= (struct vnic_resource __iomem
*)(rh
+ 1);
102 while ((type
= ioread8(&r
->type
)) != RES_TYPE_EOL
) {
104 u8 bar_num
= ioread8(&r
->bar
);
105 u32 bar_offset
= ioread32(&r
->bar_offset
);
106 u32 count
= ioread32(&r
->count
);
111 if (bar_num
>= num_bars
)
114 if (!bar
[bar_num
].len
|| !bar
[bar_num
].vaddr
)
121 case RES_TYPE_INTR_CTRL
:
122 /* each count is stride bytes long */
123 len
= count
* VNIC_RES_STRIDE
;
124 if (len
+ bar_offset
> bar
->len
) {
125 pr_err("vNIC BAR0 resource %d out-of-bounds, offset 0x%x + size 0x%x > bar len 0x%lx\n",
134 case RES_TYPE_INTR_PBA_LEGACY
:
135 case RES_TYPE_DEVCMD
:
136 case RES_TYPE_DEVCMD2
:
144 vdev
->res
[type
].count
= count
;
145 vdev
->res
[type
].vaddr
= (char __iomem
*)bar
->vaddr
+ bar_offset
;
151 unsigned int svnic_dev_get_res_count(struct vnic_dev
*vdev
,
152 enum vnic_res_type type
)
154 return vdev
->res
[type
].count
;
157 void __iomem
*svnic_dev_get_res(struct vnic_dev
*vdev
, enum vnic_res_type type
,
160 if (!vdev
->res
[type
].vaddr
)
167 case RES_TYPE_INTR_CTRL
:
168 return (char __iomem
*)vdev
->res
[type
].vaddr
+
169 index
* VNIC_RES_STRIDE
;
172 return (char __iomem
*)vdev
->res
[type
].vaddr
;
176 unsigned int svnic_dev_desc_ring_size(struct vnic_dev_ring
*ring
,
177 unsigned int desc_count
,
178 unsigned int desc_size
)
180 /* The base address of the desc rings must be 512 byte aligned.
181 * Descriptor count is aligned to groups of 32 descriptors. A
182 * count of 0 means the maximum 4096 descriptors. Descriptor
183 * size is aligned to 16 bytes.
186 unsigned int count_align
= 32;
187 unsigned int desc_align
= 16;
189 ring
->base_align
= 512;
194 ring
->desc_count
= ALIGN(desc_count
, count_align
);
196 ring
->desc_size
= ALIGN(desc_size
, desc_align
);
198 ring
->size
= ring
->desc_count
* ring
->desc_size
;
199 ring
->size_unaligned
= ring
->size
+ ring
->base_align
;
201 return ring
->size_unaligned
;
204 void svnic_dev_clear_desc_ring(struct vnic_dev_ring
*ring
)
206 memset(ring
->descs
, 0, ring
->size
);
209 int svnic_dev_alloc_desc_ring(struct vnic_dev
*vdev
, struct vnic_dev_ring
*ring
,
210 unsigned int desc_count
, unsigned int desc_size
)
212 svnic_dev_desc_ring_size(ring
, desc_count
, desc_size
);
214 ring
->descs_unaligned
= dma_alloc_coherent(&vdev
->pdev
->dev
,
215 ring
->size_unaligned
, &ring
->base_addr_unaligned
,
217 if (!ring
->descs_unaligned
) {
218 pr_err("Failed to allocate ring (size=%d), aborting\n",
224 ring
->base_addr
= ALIGN(ring
->base_addr_unaligned
,
226 ring
->descs
= (u8
*)ring
->descs_unaligned
+
227 (ring
->base_addr
- ring
->base_addr_unaligned
);
229 svnic_dev_clear_desc_ring(ring
);
231 ring
->desc_avail
= ring
->desc_count
- 1;
236 void svnic_dev_free_desc_ring(struct vnic_dev
*vdev
, struct vnic_dev_ring
*ring
)
239 dma_free_coherent(&vdev
->pdev
->dev
,
240 ring
->size_unaligned
,
241 ring
->descs_unaligned
,
242 ring
->base_addr_unaligned
);
247 static int _svnic_dev_cmd2(struct vnic_dev
*vdev
, enum vnic_devcmd_cmd cmd
,
250 struct devcmd2_controller
*dc2c
= vdev
->devcmd2
;
251 struct devcmd2_result
*result
= NULL
;
260 fetch_idx
= ioread32(&dc2c
->wq_ctrl
->fetch_index
);
261 if (fetch_idx
== 0xFFFFFFFF) { /* check for hardware gone */
262 /* Hardware surprise removal: return error */
266 posted
= ioread32(&dc2c
->wq_ctrl
->posted_index
);
268 if (posted
== 0xFFFFFFFF) { /* check for hardware gone */
269 /* Hardware surprise removal: return error */
273 new_posted
= (posted
+ 1) % DEVCMD2_RING_SIZE
;
274 if (new_posted
== fetch_idx
) {
275 pr_err("%s: wq is full while issuing devcmd2 command %d, fetch index: %u, posted index: %u\n",
276 pci_name(vdev
->pdev
), _CMD_N(cmd
), fetch_idx
, posted
);
281 dc2c
->cmd_ring
[posted
].cmd
= cmd
;
282 dc2c
->cmd_ring
[posted
].flags
= 0;
284 if ((_CMD_FLAGS(cmd
) & _CMD_FLAGS_NOWAIT
))
285 dc2c
->cmd_ring
[posted
].flags
|= DEVCMD2_FNORESULT
;
287 if (_CMD_DIR(cmd
) & _CMD_DIR_WRITE
) {
288 for (i
= 0; i
< VNIC_DEVCMD_NARGS
; i
++)
289 dc2c
->cmd_ring
[posted
].args
[i
] = vdev
->args
[i
];
291 /* Adding write memory barrier prevents compiler and/or CPU
292 * reordering, thus avoiding descriptor posting before
293 * descriptor is initialized. Otherwise, hardware can read
294 * stale descriptor fields.
297 iowrite32(new_posted
, &dc2c
->wq_ctrl
->posted_index
);
299 if (dc2c
->cmd_ring
[posted
].flags
& DEVCMD2_FNORESULT
)
302 result
= dc2c
->result
+ dc2c
->next_result
;
306 * Increment next_result, after posting the devcmd, irrespective of
307 * devcmd result, and it should be done only once.
310 if (dc2c
->next_result
== dc2c
->result_size
) {
311 dc2c
->next_result
= 0;
312 dc2c
->color
= dc2c
->color
? 0 : 1;
315 for (delay
= 0; delay
< wait
; delay
++) {
317 if (result
->color
== color
) {
319 err
= (int) result
->error
;
320 if (err
!= ERR_ECMDUNKNOWN
||
321 cmd
!= CMD_CAPABILITY
)
322 pr_err("Error %d devcmd %d\n",
327 if (_CMD_DIR(cmd
) & _CMD_DIR_READ
) {
328 for (i
= 0; i
< VNIC_DEVCMD_NARGS
; i
++)
329 vdev
->args
[i
] = result
->results
[i
];
336 pr_err("Timed out devcmd %d\n", _CMD_N(cmd
));
341 static int svnic_dev_init_devcmd2(struct vnic_dev
*vdev
)
343 struct devcmd2_controller
*dc2c
= NULL
;
344 unsigned int fetch_idx
;
351 p
= svnic_dev_get_res(vdev
, RES_TYPE_DEVCMD2
, 0);
355 dc2c
= kzalloc(sizeof(*dc2c
), GFP_ATOMIC
);
359 vdev
->devcmd2
= dc2c
;
362 dc2c
->result_size
= DEVCMD2_RING_SIZE
;
364 ret
= vnic_wq_devcmd2_alloc(vdev
,
369 goto err_free_devcmd2
;
371 fetch_idx
= ioread32(&dc2c
->wq
.ctrl
->fetch_index
);
372 if (fetch_idx
== 0xFFFFFFFF) { /* check for hardware gone */
373 /* Hardware surprise removal: reset fetch_index */
378 * Don't change fetch_index ever and
379 * set posted_index same as fetch_index
380 * when setting up the WQ for devcmd2.
382 vnic_wq_init_start(&dc2c
->wq
, 0, fetch_idx
, fetch_idx
, 0, 0);
383 svnic_wq_enable(&dc2c
->wq
);
384 ret
= svnic_dev_alloc_desc_ring(vdev
,
391 dc2c
->result
= (struct devcmd2_result
*) dc2c
->results_ring
.descs
;
392 dc2c
->cmd_ring
= (struct vnic_devcmd2
*) dc2c
->wq
.ring
.descs
;
393 dc2c
->wq_ctrl
= dc2c
->wq
.ctrl
;
394 vdev
->args
[0] = (u64
) dc2c
->results_ring
.base_addr
| VNIC_PADDR_TARGET
;
395 vdev
->args
[1] = DEVCMD2_RING_SIZE
;
397 ret
= _svnic_dev_cmd2(vdev
, CMD_INITIALIZE_DEVCMD2
, VNIC_DVCMD_TMO
);
399 goto err_free_desc_ring
;
401 vdev
->devcmd_rtn
= &_svnic_dev_cmd2
;
402 pr_info("DEVCMD2 Initialized.\n");
407 svnic_dev_free_desc_ring(vdev
, &dc2c
->results_ring
);
410 svnic_wq_disable(&dc2c
->wq
);
411 svnic_wq_free(&dc2c
->wq
);
415 vdev
->devcmd2
= NULL
;
418 } /* end of svnic_dev_init_devcmd2 */
420 static void vnic_dev_deinit_devcmd2(struct vnic_dev
*vdev
)
422 struct devcmd2_controller
*dc2c
= vdev
->devcmd2
;
424 vdev
->devcmd2
= NULL
;
425 vdev
->devcmd_rtn
= NULL
;
427 svnic_dev_free_desc_ring(vdev
, &dc2c
->results_ring
);
428 svnic_wq_disable(&dc2c
->wq
);
429 svnic_wq_free(&dc2c
->wq
);
433 int svnic_dev_cmd(struct vnic_dev
*vdev
, enum vnic_devcmd_cmd cmd
,
434 u64
*a0
, u64
*a1
, int wait
)
438 memset(vdev
->args
, 0, sizeof(vdev
->args
));
442 err
= (*vdev
->devcmd_rtn
)(vdev
, cmd
, wait
);
450 int svnic_dev_fw_info(struct vnic_dev
*vdev
,
451 struct vnic_devcmd_fw_info
**fw_info
)
454 int wait
= VNIC_DVCMD_TMO
;
457 if (!vdev
->fw_info
) {
458 vdev
->fw_info
= dma_alloc_coherent(&vdev
->pdev
->dev
,
459 sizeof(struct vnic_devcmd_fw_info
),
460 &vdev
->fw_info_pa
, GFP_KERNEL
);
464 a0
= vdev
->fw_info_pa
;
466 /* only get fw_info once and cache it */
467 err
= svnic_dev_cmd(vdev
, CMD_MCPU_FW_INFO
, &a0
, &a1
, wait
);
470 *fw_info
= vdev
->fw_info
;
475 int svnic_dev_spec(struct vnic_dev
*vdev
, unsigned int offset
,
476 unsigned int size
, void *value
)
479 int wait
= VNIC_DVCMD_TMO
;
485 err
= svnic_dev_cmd(vdev
, CMD_DEV_SPEC
, &a0
, &a1
, wait
);
489 *(u8
*)value
= (u8
)a0
;
492 *(u16
*)value
= (u16
)a0
;
495 *(u32
*)value
= (u32
)a0
;
508 int svnic_dev_stats_clear(struct vnic_dev
*vdev
)
511 int wait
= VNIC_DVCMD_TMO
;
513 return svnic_dev_cmd(vdev
, CMD_STATS_CLEAR
, &a0
, &a1
, wait
);
516 int svnic_dev_stats_dump(struct vnic_dev
*vdev
, struct vnic_stats
**stats
)
519 int wait
= VNIC_DVCMD_TMO
;
522 vdev
->stats
= dma_alloc_coherent(&vdev
->pdev
->dev
,
523 sizeof(struct vnic_stats
), &vdev
->stats_pa
, GFP_KERNEL
);
528 *stats
= vdev
->stats
;
530 a1
= sizeof(struct vnic_stats
);
532 return svnic_dev_cmd(vdev
, CMD_STATS_DUMP
, &a0
, &a1
, wait
);
535 int svnic_dev_close(struct vnic_dev
*vdev
)
538 int wait
= VNIC_DVCMD_TMO
;
540 return svnic_dev_cmd(vdev
, CMD_CLOSE
, &a0
, &a1
, wait
);
543 int svnic_dev_enable_wait(struct vnic_dev
*vdev
)
546 int wait
= VNIC_DVCMD_TMO
;
549 err
= svnic_dev_cmd(vdev
, CMD_ENABLE_WAIT
, &a0
, &a1
, wait
);
550 if (err
== ERR_ECMDUNKNOWN
)
551 return svnic_dev_cmd(vdev
, CMD_ENABLE
, &a0
, &a1
, wait
);
556 int svnic_dev_disable(struct vnic_dev
*vdev
)
559 int wait
= VNIC_DVCMD_TMO
;
561 return svnic_dev_cmd(vdev
, CMD_DISABLE
, &a0
, &a1
, wait
);
564 int svnic_dev_open(struct vnic_dev
*vdev
, int arg
)
566 u64 a0
= (u32
)arg
, a1
= 0;
567 int wait
= VNIC_DVCMD_TMO
;
569 return svnic_dev_cmd(vdev
, CMD_OPEN
, &a0
, &a1
, wait
);
572 int svnic_dev_open_done(struct vnic_dev
*vdev
, int *done
)
575 int wait
= VNIC_DVCMD_TMO
;
580 err
= svnic_dev_cmd(vdev
, CMD_OPEN_STATUS
, &a0
, &a1
, wait
);
589 int svnic_dev_notify_set(struct vnic_dev
*vdev
, u16 intr
)
592 int wait
= VNIC_DVCMD_TMO
;
595 vdev
->notify
= dma_alloc_coherent(&vdev
->pdev
->dev
,
596 sizeof(struct vnic_devcmd_notify
),
597 &vdev
->notify_pa
, GFP_KERNEL
);
602 a0
= vdev
->notify_pa
;
603 a1
= ((u64
)intr
<< 32) & VNIC_NOTIFY_INTR_MASK
;
604 a1
+= sizeof(struct vnic_devcmd_notify
);
606 return svnic_dev_cmd(vdev
, CMD_NOTIFY
, &a0
, &a1
, wait
);
609 void svnic_dev_notify_unset(struct vnic_dev
*vdev
)
612 int wait
= VNIC_DVCMD_TMO
;
614 a0
= 0; /* paddr = 0 to unset notify buffer */
615 a1
= VNIC_NOTIFY_INTR_MASK
; /* intr num = -1 to unreg for intr */
616 a1
+= sizeof(struct vnic_devcmd_notify
);
618 svnic_dev_cmd(vdev
, CMD_NOTIFY
, &a0
, &a1
, wait
);
621 static int vnic_dev_notify_ready(struct vnic_dev
*vdev
)
624 unsigned int nwords
= sizeof(struct vnic_devcmd_notify
) / 4;
633 memcpy(&vdev
->notify_copy
, vdev
->notify
,
634 sizeof(struct vnic_devcmd_notify
));
635 words
= (u32
*)&vdev
->notify_copy
;
636 for (i
= 1; i
< nwords
; i
++)
638 } while (csum
!= words
[0]);
643 int svnic_dev_init(struct vnic_dev
*vdev
, int arg
)
645 u64 a0
= (u32
)arg
, a1
= 0;
646 int wait
= VNIC_DVCMD_TMO
;
648 return svnic_dev_cmd(vdev
, CMD_INIT
, &a0
, &a1
, wait
);
651 int svnic_dev_link_status(struct vnic_dev
*vdev
)
653 if (vdev
->linkstatus
)
654 return *vdev
->linkstatus
;
656 if (!vnic_dev_notify_ready(vdev
))
659 return vdev
->notify_copy
.link_state
;
662 u32
svnic_dev_link_down_cnt(struct vnic_dev
*vdev
)
664 if (!vnic_dev_notify_ready(vdev
))
667 return vdev
->notify_copy
.link_down_cnt
;
670 void svnic_dev_set_intr_mode(struct vnic_dev
*vdev
,
671 enum vnic_dev_intr_mode intr_mode
)
673 vdev
->intr_mode
= intr_mode
;
676 enum vnic_dev_intr_mode
svnic_dev_get_intr_mode(struct vnic_dev
*vdev
)
678 return vdev
->intr_mode
;
681 void svnic_dev_unregister(struct vnic_dev
*vdev
)
685 dma_free_coherent(&vdev
->pdev
->dev
,
686 sizeof(struct vnic_devcmd_notify
),
689 if (vdev
->linkstatus
)
690 dma_free_coherent(&vdev
->pdev
->dev
,
693 vdev
->linkstatus_pa
);
695 dma_free_coherent(&vdev
->pdev
->dev
,
696 sizeof(struct vnic_stats
),
697 vdev
->stats
, vdev
->stats_pa
);
699 dma_free_coherent(&vdev
->pdev
->dev
,
700 sizeof(struct vnic_devcmd_fw_info
),
701 vdev
->fw_info
, vdev
->fw_info_pa
);
703 vnic_dev_deinit_devcmd2(vdev
);
708 struct vnic_dev
*svnic_dev_alloc_discover(struct vnic_dev
*vdev
,
710 struct pci_dev
*pdev
,
711 struct vnic_dev_bar
*bar
,
712 unsigned int num_bars
)
715 vdev
= kzalloc(sizeof(struct vnic_dev
), GFP_ATOMIC
);
723 if (vnic_dev_discover_res(vdev
, bar
, num_bars
))
729 svnic_dev_unregister(vdev
);
732 } /* end of svnic_dev_alloc_discover */
735 * fallback option is left to keep the interface common for other vnics.
737 int svnic_dev_cmd_init(struct vnic_dev
*vdev
, int fallback
)
742 p
= svnic_dev_get_res(vdev
, RES_TYPE_DEVCMD2
, 0);
744 err
= svnic_dev_init_devcmd2(vdev
);
746 pr_err("DEVCMD2 resource not found.\n");
749 } /* end of svnic_dev_cmd_init */