1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright 2014 Cisco Systems, Inc. All rights reserved. */
11 /* Work queue control */
13 u64 ring_base
; /* 0x00 */
14 u32 ring_size
; /* 0x08 */
16 u32 posted_index
; /* 0x10 */
18 u32 cq_index
; /* 0x18 */
20 u32 enable
; /* 0x20 */
22 u32 running
; /* 0x28 */
24 u32 fetch_index
; /* 0x30 */
26 u32 dca_value
; /* 0x38 */
28 u32 error_interrupt_enable
; /* 0x40 */
30 u32 error_interrupt_offset
; /* 0x48 */
32 u32 error_status
; /* 0x50 */
37 struct vnic_wq_buf
*next
;
46 /* Break the vnic_wq_buf allocations into blocks of 64 entries */
47 #define VNIC_WQ_BUF_MIN_BLK_ENTRIES 32
48 #define VNIC_WQ_BUF_DFLT_BLK_ENTRIES 64
49 #define VNIC_WQ_BUF_BLK_ENTRIES(entries) \
50 ((unsigned int)(entries < VNIC_WQ_BUF_DFLT_BLK_ENTRIES) ? \
51 VNIC_WQ_BUF_MIN_BLK_ENTRIES : VNIC_WQ_BUF_DFLT_BLK_ENTRIES)
52 #define VNIC_WQ_BUF_BLK_SZ \
53 (VNIC_WQ_BUF_DFLT_BLK_ENTRIES * sizeof(struct vnic_wq_buf))
54 #define VNIC_WQ_BUF_BLKS_NEEDED(entries) \
55 DIV_ROUND_UP(entries, VNIC_WQ_BUF_DFLT_BLK_ENTRIES)
56 #define VNIC_WQ_BUF_BLKS_NEEDED(entries) \
57 DIV_ROUND_UP(entries, VNIC_WQ_BUF_DFLT_BLK_ENTRIES)
58 #define VNIC_WQ_BUF_BLKS_MAX VNIC_WQ_BUF_BLKS_NEEDED(4096)
62 struct vnic_dev
*vdev
;
63 struct vnic_wq_ctrl __iomem
*ctrl
; /* memory-mapped */
64 struct vnic_dev_ring ring
;
65 struct vnic_wq_buf
*bufs
[VNIC_WQ_BUF_BLKS_MAX
];
66 struct vnic_wq_buf
*to_use
;
67 struct vnic_wq_buf
*to_clean
;
68 unsigned int pkts_outstanding
;
71 static inline unsigned int svnic_wq_desc_avail(struct vnic_wq
*wq
)
73 /* how many does SW own? */
74 return wq
->ring
.desc_avail
;
77 static inline unsigned int svnic_wq_desc_used(struct vnic_wq
*wq
)
79 /* how many does HW own? */
80 return wq
->ring
.desc_count
- wq
->ring
.desc_avail
- 1;
83 static inline void *svnic_wq_next_desc(struct vnic_wq
*wq
)
85 return wq
->to_use
->desc
;
88 static inline void svnic_wq_post(struct vnic_wq
*wq
,
89 void *os_buf
, dma_addr_t dma_addr
,
90 unsigned int len
, int sop
, int eop
)
92 struct vnic_wq_buf
*buf
= wq
->to_use
;
95 buf
->os_buf
= eop
? os_buf
: NULL
;
96 buf
->dma_addr
= dma_addr
;
101 /* Adding write memory barrier prevents compiler and/or CPU
102 * reordering, thus avoiding descriptor posting before
103 * descriptor is initialized. Otherwise, hardware can read
104 * stale descriptor fields.
107 iowrite32(buf
->index
, &wq
->ctrl
->posted_index
);
111 wq
->ring
.desc_avail
--;
114 static inline void svnic_wq_service(struct vnic_wq
*wq
,
115 struct cq_desc
*cq_desc
, u16 completed_index
,
116 void (*buf_service
)(struct vnic_wq
*wq
,
117 struct cq_desc
*cq_desc
, struct vnic_wq_buf
*buf
, void *opaque
),
120 struct vnic_wq_buf
*buf
;
125 (*buf_service
)(wq
, cq_desc
, buf
, opaque
);
127 wq
->ring
.desc_avail
++;
129 wq
->to_clean
= buf
->next
;
131 if (buf
->index
== completed_index
)
138 void svnic_wq_free(struct vnic_wq
*wq
);
139 int svnic_wq_alloc(struct vnic_dev
*vdev
, struct vnic_wq
*wq
,
140 unsigned int index
, unsigned int desc_count
, unsigned int desc_size
);
141 int vnic_wq_devcmd2_alloc(struct vnic_dev
*vdev
, struct vnic_wq
*wq
,
142 unsigned int desc_count
, unsigned int desc_size
);
143 void vnic_wq_init_start(struct vnic_wq
*wq
, unsigned int cq_index
,
144 unsigned int fetch_index
, unsigned int post_index
,
145 unsigned int error_interrupt_enable
,
146 unsigned int error_interrupt_offset
);
148 void svnic_wq_init(struct vnic_wq
*wq
, unsigned int cq_index
,
149 unsigned int error_interrupt_enable
,
150 unsigned int error_interrupt_offset
);
151 unsigned int svnic_wq_error_status(struct vnic_wq
*wq
);
152 void svnic_wq_enable(struct vnic_wq
*wq
);
153 int svnic_wq_disable(struct vnic_wq
*wq
);
154 void svnic_wq_clean(struct vnic_wq
*wq
,
155 void (*buf_clean
)(struct vnic_wq
*wq
, struct vnic_wq_buf
*buf
));
156 #endif /* _VNIC_WQ_H_ */