1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/renesas,du.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Display Unit (DU)
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 These DT bindings describe the Display Unit embedded in the Renesas R-Car
14 Gen1, R-Car Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.
19 - renesas,du-r8a7742 # for RZ/G1H compatible DU
20 - renesas,du-r8a7743 # for RZ/G1M compatible DU
21 - renesas,du-r8a7744 # for RZ/G1N compatible DU
22 - renesas,du-r8a7745 # for RZ/G1E compatible DU
23 - renesas,du-r8a77470 # for RZ/G1C compatible DU
24 - renesas,du-r8a774a1 # for RZ/G2M compatible DU
25 - renesas,du-r8a774b1 # for RZ/G2N compatible DU
26 - renesas,du-r8a774c0 # for RZ/G2E compatible DU
27 - renesas,du-r8a774e1 # for RZ/G2H compatible DU
28 - renesas,du-r8a7779 # for R-Car H1 compatible DU
29 - renesas,du-r8a7790 # for R-Car H2 compatible DU
30 - renesas,du-r8a7791 # for R-Car M2-W compatible DU
31 - renesas,du-r8a7792 # for R-Car V2H compatible DU
32 - renesas,du-r8a7793 # for R-Car M2-N compatible DU
33 - renesas,du-r8a7794 # for R-Car E2 compatible DU
34 - renesas,du-r8a7795 # for R-Car H3 compatible DU
35 - renesas,du-r8a7796 # for R-Car M3-W compatible DU
36 - renesas,du-r8a77961 # for R-Car M3-W+ compatible DU
37 - renesas,du-r8a77965 # for R-Car M3-N compatible DU
38 - renesas,du-r8a77970 # for R-Car V3M compatible DU
39 - renesas,du-r8a77980 # for R-Car V3H compatible DU
40 - renesas,du-r8a77990 # for R-Car E3 compatible DU
41 - renesas,du-r8a77995 # for R-Car D3 compatible DU
42 - renesas,du-r8a779a0 # for R-Car V3U compatible DU
43 - renesas,du-r8a779g0 # for R-Car V4H compatible DU
48 # See compatible-specific constraints below.
52 description: Interrupt specifiers, one per DU channel
60 $ref: /schemas/graph.yaml#/properties/ports
62 The connections to the DU output video ports are modeled using the OF
63 graph bindings specified in Documentation/devicetree/bindings/graph.txt.
64 The number of ports and their assignment are model-dependent. Each port
65 shall have a single endpoint.
69 $ref: /schemas/graph.yaml#/properties/port
70 unevaluatedProperties: false
76 unevaluatedProperties: false
79 $ref: /schemas/types.yaml#/definitions/phandle-array
83 A list of phandles to the CMM instances present in the SoC, one for each
87 $ref: /schemas/types.yaml#/definitions/phandle-array
90 - description: phandle to VSP instance that serves the DU channel
91 - description: Channel index identifying the LIF instance in that VSP
93 A list of phandle and channel index tuples to the VSPs that handle the
94 memory interfaces for the DU channels.
108 const: renesas,du-r8a7779
114 - description: Functional clock
115 - description: DU_DOTCLKIN0 input clock
116 - description: DU_DOTCLKIN1 input clock
122 - pattern: '^dclkin\.[01]$'
123 - pattern: '^dclkin\.[01]$'
137 # port@2 is TCON, not supported yet
162 - description: Functional clock for DU0
163 - description: Functional clock for DU1
164 - description: DU_DOTCLKIN0 input clock
165 - description: DU_DOTCLKIN1 input clock
172 - pattern: '^dclkin\.[01]$'
173 - pattern: '^dclkin\.[01]$'
191 # port@2 is TCON, not supported yet
217 - description: Functional clock for DU0
218 - description: Functional clock for DU1
219 - description: DU_DOTCLKIN0 input clock
220 - description: DU_DOTCLKIN1 input clock
227 - pattern: '^dclkin\.[01]$'
228 - pattern: '^dclkin\.[01]$'
270 - description: Functional clock for DU0
271 - description: Functional clock for DU1
272 - description: DU_DOTCLKIN0 input clock
273 - description: DU_DOTCLKIN1 input clock
280 - pattern: '^dclkin\.[01]$'
281 - pattern: '^dclkin\.[01]$'
299 # port@2 is TCON, not supported yet
318 - renesas,du-r8a77470
324 - description: Functional clock for DU0
325 - description: Functional clock for DU1
326 - description: DU_DOTCLKIN0 input clock
327 - description: DU_DOTCLKIN1 input clock
334 - pattern: '^dclkin\.[01]$'
335 - pattern: '^dclkin\.[01]$'
355 # port@3 is DVENC, not supported yet
381 - description: Functional clock for DU0
382 - description: Functional clock for DU1
383 - description: Functional clock for DU2
384 - description: DU_DOTCLKIN0 input clock
385 - description: DU_DOTCLKIN1 input clock
386 - description: DU_DOTCLKIN2 input clock
394 - pattern: '^dclkin\.[012]$'
395 - pattern: '^dclkin\.[012]$'
396 - pattern: '^dclkin\.[012]$'
416 # port@3 is TCON, not supported yet
441 - description: Functional clock for DU0
442 - description: Functional clock for DU1
443 - description: Functional clock for DU2
444 - description: Functional clock for DU4
445 - description: DU_DOTCLKIN0 input clock
446 - description: DU_DOTCLKIN1 input clock
447 - description: DU_DOTCLKIN2 input clock
448 - description: DU_DOTCLKIN3 input clock
457 - pattern: '^dclkin\.[0123]$'
458 - pattern: '^dclkin\.[0123]$'
459 - pattern: '^dclkin\.[0123]$'
460 - pattern: '^dclkin\.[0123]$'
508 - renesas,du-r8a774a1
510 - renesas,du-r8a77961
516 - description: Functional clock for DU0
517 - description: Functional clock for DU1
518 - description: Functional clock for DU2
519 - description: DU_DOTCLKIN0 input clock
520 - description: DU_DOTCLKIN1 input clock
521 - description: DU_DOTCLKIN2 input clock
529 - pattern: '^dclkin\.[012]$'
530 - pattern: '^dclkin\.[012]$'
531 - pattern: '^dclkin\.[012]$'
577 - renesas,du-r8a774b1
578 - renesas,du-r8a774e1
579 - renesas,du-r8a77965
585 - description: Functional clock for DU0
586 - description: Functional clock for DU1
587 - description: Functional clock for DU3
588 - description: DU_DOTCLKIN0 input clock
589 - description: DU_DOTCLKIN1 input clock
590 - description: DU_DOTCLKIN3 input clock
598 - pattern: '^dclkin\.[013]$'
599 - pattern: '^dclkin\.[013]$'
600 - pattern: '^dclkin\.[013]$'
646 - renesas,du-r8a77970
647 - renesas,du-r8a77980
653 - description: Functional clock for DU0
654 - description: DU_DOTCLKIN0 input clock
700 - renesas,du-r8a774c0
701 - renesas,du-r8a77990
702 - renesas,du-r8a77995
708 - description: Functional clock for DU0
709 - description: Functional clock for DU1
710 - description: DU_DOTCLKIN0 input clock
711 - description: DU_DOTCLKIN1 input clock
718 - pattern: '^dclkin\.[01]$'
719 - pattern: '^dclkin\.[01]$'
739 # port@3 is TCON, not supported yet
765 - renesas,du-r8a779a0
766 - renesas,du-r8a779g0
771 - description: Functional clock
810 additionalProperties: false
815 #include <dt-bindings/clock/renesas-cpg-mssr.h>
816 #include <dt-bindings/interrupt-controller/arm-gic.h>
819 compatible = "renesas,du-r8a7795";
820 reg = <0xfeb00000 0x80000>;
821 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
822 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
824 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
825 clocks = <&cpg CPG_MOD 724>,
829 clock-names = "du.0", "du.1", "du.2", "du.3";
830 resets = <&cpg 724>, <&cpg 722>;
831 reset-names = "du.0", "du.2";
833 renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>;
834 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
837 #address-cells = <1>;
843 remote-endpoint = <&adv7123_in>;
849 remote-endpoint = <&dw_hdmi0_in>;
855 remote-endpoint = <&dw_hdmi1_in>;
861 remote-endpoint = <&lvds0_in>;