1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 (and later) Display Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^display@[0-9a-f]+$"
30 - description: display controller pixel clock
38 - description: display controller reset
51 description: Description of the interconnect paths for the
52 display controller; see ../interconnect/interconnect.txt
57 - const: dma-mem # read-0
61 description: A list of phandles of outputs that this display
63 $ref: /schemas/types.yaml#/definitions/phandle-array
66 description: The number of the display controller head. This
67 is used to setup the various types of output to receive
68 video data from the given head.
69 $ref: /schemas/types.yaml#/definitions/uint32
71 additionalProperties: false
85 # see nvidia,tegra186-display.yaml for examples