Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-epp.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: NVIDIA Tegra Encoder Pre-Processor
   8
   9 maintainers:
  10   - Thierry Reding <thierry.reding@gmail.com>
  11   - Jon Hunter <jonathanh@nvidia.com>
  12
  13 properties:
  14   $nodename:
  15     pattern: "^epp@[0-9a-f]+$"
  16
  17   compatible:
  18     enum:
  19       - nvidia,tegra20-epp
  20       - nvidia,tegra30-epp
  21       - nvidia,tegra114-epp
  22
  23   reg:
  24     maxItems: 1
  25
  26   interrupts:
  27     maxItems: 1
  28
  29   clocks:
  30     maxItems: 1
  31
  32   resets:
  33     items:
  34       - description: module reset
  35
  36   reset-names:
  37     items:
  38       - const: epp
  39
  40   iommus:
  41     maxItems: 1
  42
  43   interconnects:
  44     maxItems: 4
  45
  46   interconnect-names:
  47     maxItems: 4
  48
  49   operating-points-v2: true
  50
  51   power-domains:
  52     items:
  53       - description: phandle to the core power domain
  54
  55 additionalProperties: false
  56
  57 examples:
  58   - |
  59     #include <dt-bindings/clock/tegra20-car.h>
  60     #include <dt-bindings/interrupt-controller/arm-gic.h>
  61
  62     epp@540c0000 {
  63         compatible = "nvidia,tegra20-epp";
  64         reg = <0x540c0000 0x00040000>;
  65         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
  66         clocks = <&tegra_car TEGRA20_CLK_EPP>;
  67         resets = <&tegra_car 19>;
  68         reset-names = "epp";
  69     };