1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/interconnect/qcom,sm6115.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM6115 Network-On-Chip interconnect
10 - Konrad Dybcio <konradybcio@kernel.org>
13 The Qualcomm SM6115 interconnect providers support adjusting the
14 bandwidth requirements between the various NoC fabrics.
34 # Child node's properties
36 '^interconnect-[a-z0-9]+$':
39 The interconnect providers do not have a separate QoS register space,
40 but share parent's space.
42 $ref: qcom,rpm-common.yaml#
47 - qcom,sm6115-clk-virt
48 - qcom,sm6115-mmrt-virt
49 - qcom,sm6115-mmnrt-virt
54 unevaluatedProperties: false
61 - $ref: qcom,rpm-common.yaml#
65 const: qcom,sm6115-cnoc
71 - description: USB-NoC AXI clock
80 const: qcom,sm6115-snoc
86 - description: CPU-NoC AXI clock.
87 - description: UFS-NoC AXI clock.
88 - description: USB-NoC AXI clock.
89 - description: IPA clock.
103 - qcom,sm6115-clk-virt
104 - qcom,sm6115-mmrt-virt
105 - qcom,sm6115-mmnrt-virt
112 unevaluatedProperties: false
116 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
117 #include <dt-bindings/clock/qcom,rpmcc.h>
119 snoc: interconnect@1880000 {
120 compatible = "qcom,sm6115-snoc";
121 reg = <0x01880000 0x60200>;
122 clocks = <&gcc GCC_SYS_NOC_CPUSS_AHB_CLK>,
123 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
124 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
125 <&rpmcc RPM_SMD_IPA_CLK>;
126 clock-names = "cpu_axi",
130 #interconnect-cells = <1>;
132 qup_virt: interconnect-clk {
133 compatible = "qcom,sm6115-clk-virt";
134 #interconnect-cells = <1>;
137 mmnrt_virt: interconnect-mmnrt {
138 compatible = "qcom,sm6115-mmnrt-virt";
139 #interconnect-cells = <1>;
142 mmrt_virt: interconnect-mmrt {
143 compatible = "qcom,sm6115-mmrt-virt";
144 #interconnect-cells = <1>;
148 cnoc: interconnect@1900000 {
149 compatible = "qcom,sm6115-cnoc";
150 reg = <0x01900000 0x8200>;
151 #interconnect-cells = <1>;