Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2
   3 %YAML 1.2
   4 ---
   5 $id: http://devicetree.org/schemas/media/mediatek,vcodec-encoder.yaml#
   6 $schema: http://devicetree.org/meta-schemas/core.yaml#
   7
   8 title: Mediatek Video Encode Accelerator
   9
  10 maintainers:
  11   - Yunfei Dong <yunfei.dong@mediatek.com>
  12
  13 description: |+
  14   Mediatek Video Encode is the video encode hardware present in Mediatek
  15   SoCs which supports high resolution encoding functionalities.
  16
  17 properties:
  18   compatible:
  19     oneOf:
  20       - items:
  21           - enum:
  22               - mediatek,mt8173-vcodec-enc-vp8
  23               - mediatek,mt8173-vcodec-enc
  24               - mediatek,mt8183-vcodec-enc
  25               - mediatek,mt8188-vcodec-enc
  26               - mediatek,mt8192-vcodec-enc
  27               - mediatek,mt8195-vcodec-enc
  28       - items:
  29           - const: mediatek,mt8186-vcodec-enc
  30           - const: mediatek,mt8183-vcodec-enc
  31   reg:
  32     maxItems: 1
  33
  34   interrupts:
  35     maxItems: 1
  36
  37   clocks:
  38     minItems: 1
  39     maxItems: 5
  40
  41   clock-names:
  42     minItems: 1
  43     maxItems: 5
  44
  45   assigned-clocks: true
  46
  47   assigned-clock-parents: true
  48
  49   iommus:
  50     minItems: 1
  51     maxItems: 32
  52     description: |
  53       List of the hardware port in respective IOMMU block for current Socs.
  54       Refer to bindings/iommu/mediatek,iommu.yaml.
  55
  56   mediatek,vpu:
  57     $ref: /schemas/types.yaml#/definitions/phandle
  58     description:
  59       Describes point to vpu.
  60
  61   mediatek,scp:
  62     $ref: /schemas/types.yaml#/definitions/phandle
  63     description:
  64       Describes point to scp.
  65
  66   power-domains:
  67     maxItems: 1
  68
  69   "#address-cells":
  70     const: 2
  71
  72   "#size-cells":
  73     const: 2
  74
  75 required:
  76   - compatible
  77   - reg
  78   - interrupts
  79   - clocks
  80   - clock-names
  81   - iommus
  82   - assigned-clocks
  83   - assigned-clock-parents
  84
  85 allOf:
  86   - if:
  87       properties:
  88         compatible:
  89           contains:
  90             enum:
  91               - mediatek,mt8183-vcodec-enc
  92               - mediatek,mt8188-vcodec-enc
  93               - mediatek,mt8192-vcodec-enc
  94               - mediatek,mt8195-vcodec-enc
  95
  96     then:
  97       required:
  98         - mediatek,scp
  99
 100   - if:
 101       properties:
 102         compatible:
 103           contains:
 104             enum:
 105               - mediatek,mt8173-vcodec-enc-vp8
 106               - mediatek,mt8173-vcodec-enc
 107
 108     then:
 109       required:
 110         - mediatek,vpu
 111
 112   - if:
 113       properties:
 114         compatible:
 115           enum:
 116             - mediatek,mt8173-vcodec-enc-vp8
 117
 118     then:
 119       properties:
 120         clock:
 121           items:
 122             minItems: 1
 123             maxItems: 1
 124         clock-names:
 125           items:
 126             - const: venc_lt_sel
 127     else:
 128       properties:
 129         clock:
 130           items:
 131             minItems: 1
 132             maxItems: 1
 133         clock-names:
 134           items:
 135             - const: venc_sel
 136
 137 additionalProperties: false
 138
 139 examples:
 140   - |
 141     #include <dt-bindings/interrupt-controller/arm-gic.h>
 142     #include <dt-bindings/clock/mt8173-clk.h>
 143     #include <dt-bindings/memory/mt8173-larb-port.h>
 144     #include <dt-bindings/interrupt-controller/irq.h>
 145
 146     vcodec_enc_avc: vcodec@18002000 {
 147       compatible = "mediatek,mt8173-vcodec-enc";
 148       reg = <0x18002000 0x1000>;
 149       interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
 150       iommus = <&iommu M4U_PORT_VENC_RCPU>,
 151              <&iommu M4U_PORT_VENC_REC>,
 152              <&iommu M4U_PORT_VENC_BSDMA>,
 153              <&iommu M4U_PORT_VENC_SV_COMV>,
 154              <&iommu M4U_PORT_VENC_RD_COMV>,
 155              <&iommu M4U_PORT_VENC_CUR_LUMA>,
 156              <&iommu M4U_PORT_VENC_CUR_CHROMA>,
 157              <&iommu M4U_PORT_VENC_REF_LUMA>,
 158              <&iommu M4U_PORT_VENC_REF_CHROMA>,
 159              <&iommu M4U_PORT_VENC_NBM_RDMA>,
 160              <&iommu M4U_PORT_VENC_NBM_WDMA>;
 161       mediatek,vpu = <&vpu>;
 162       clocks = <&topckgen CLK_TOP_VENC_SEL>;
 163       clock-names = "venc_sel";
 164       assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
 165       assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
 166     };
 167
 168     vcodec_enc_vp8: vcodec@19002000 {
 169       compatible = "mediatek,mt8173-vcodec-enc-vp8";
 170       reg =  <0x19002000 0x1000>;       /* VENC_LT_SYS */
 171       interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
 172       iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
 173              <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
 174              <&iommu M4U_PORT_VENC_BSDMA_SET2>,
 175              <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
 176              <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
 177              <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
 178              <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
 179              <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
 180              <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
 181       mediatek,vpu = <&vpu>;
 182       clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
 183       clock-names = "venc_lt_sel";
 184       assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
 185       assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
 186     };