Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/media/nxp,imx8-jpeg.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: i.MX8QXP/QM JPEG decoder/encoder
   8
   9 maintainers:
  10   - Mirela Rabulea <mirela.rabulea@nxp.com>
  11
  12 description: |-
  13   The JPEG decoder/encoder present in iMX8QXP and iMX8QM SoCs is an
  14   ISO/IEC 10918-1 JPEG standard compliant decoder/encoder, for Baseline
  15   and Extended Sequential DCT modes.
  16
  17 properties:
  18   compatible:
  19     oneOf:
  20       - items:
  21           enum:
  22             - nxp,imx8qxp-jpgdec
  23             - nxp,imx8qxp-jpgenc
  24       - items:
  25           - const: nxp,imx8qm-jpgdec
  26           - const: nxp,imx8qxp-jpgdec
  27       - items:
  28           - const: nxp,imx8qm-jpgenc
  29           - const: nxp,imx8qxp-jpgenc
  30
  31   reg:
  32     maxItems: 1
  33
  34   clocks:
  35     items:
  36       - description: AXI DMA engine clock for fetching JPEG bitstream from memory (per)
  37       - description: IP bus clock for register access (ipg)
  38
  39   interrupts:
  40     description: |
  41       There are 4 slots available in the IP, which the driver may use
  42       If a certain slot is used, it should have an associated interrupt
  43       The interrupt with index i is assumed to be for slot i
  44     minItems: 1               # At least one slot is needed by the driver
  45     maxItems: 4               # The IP has 4 slots available for use
  46
  47   power-domains:
  48     description:
  49       List of phandle and PM domain specifier as documented in
  50       Documentation/devicetree/bindings/power/power_domain.txt
  51     minItems: 2               # Wrapper and 1 slot
  52     maxItems: 5               # Wrapper and 4 slots
  53
  54 required:
  55   - compatible
  56   - reg
  57   - clocks
  58   - interrupts
  59   - power-domains
  60
  61 additionalProperties: false
  62
  63 examples:
  64   - |
  65     #include <dt-bindings/clock/imx8-lpcg.h>
  66     #include <dt-bindings/interrupt-controller/arm-gic.h>
  67     #include <dt-bindings/firmware/imx/rsrc.h>
  68
  69     jpegdec: jpegdec@58400000 {
  70         compatible = "nxp,imx8qxp-jpgdec";
  71         reg = <0x58400000 0x00050000 >;
  72         clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
  73                  <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
  74         interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
  75                      <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
  76                      <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
  77                      <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
  78         power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
  79                         <&pd IMX_SC_R_MJPEG_DEC_S0>,
  80                         <&pd IMX_SC_R_MJPEG_DEC_S1>,
  81                         <&pd IMX_SC_R_MJPEG_DEC_S2>,
  82                         <&pd IMX_SC_R_MJPEG_DEC_S3>;
  83     };
  84
  85     jpegenc: jpegenc@58450000 {
  86         compatible = "nxp,imx8qm-jpgenc", "nxp,imx8qxp-jpgenc";
  87         reg = <0x58450000 0x00050000 >;
  88         clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
  89                  <&img_jpeg__lpcg IMX_LPCG_CLK_4>;
  90         interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
  91                      <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
  92                      <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
  93                      <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
  94         power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
  95                         <&pd IMX_SC_R_MJPEG_ENC_S0>,
  96                         <&pd IMX_SC_R_MJPEG_ENC_S1>,
  97                         <&pd IMX_SC_R_MJPEG_ENC_S2>,
  98                         <&pd IMX_SC_R_MJPEG_ENC_S3>;
  99     };
 100 ...