1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
5 $id: http://devicetree.org/schemas/media/qcom,msm8916-camss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Qualcomm CAMSS ISP
11 - Robert Foss <robert.foss@linaro.org>
12 - Todor Tomov <todor.too@gmail.com>
15 The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms
19 const: qcom,msm8916-camss
29 - const: csiphy0_timer
30 - const: csiphy1_timer
65 - description: VFE GDSC - Video Front End, Global Distributed Switch Controller.
68 $ref: /schemas/graph.yaml#/properties/ports
75 $ref: /schemas/graph.yaml#/$defs/port-base
76 unevaluatedProperties: false
78 Input port for receiving CSI data.
82 $ref: video-interfaces.yaml#
83 unevaluatedProperties: false
88 An array of physical data lanes indexes.
89 Position of an entry determines the logical
90 lane number, while the value of an entry
91 indicates physical lane index. Lane swapping
92 is supported. Physical lane indexes;
101 $ref: /schemas/graph.yaml#/$defs/port-base
102 unevaluatedProperties: false
104 Input port for receiving CSI data.
108 $ref: video-interfaces.yaml#
109 unevaluatedProperties: false
126 - const: csiphy0_clk_mux
128 - const: csiphy1_clk_mux
137 Definition of the regulator used as analog power supply.
151 additionalProperties: false
155 #include <dt-bindings/interrupt-controller/arm-gic.h>
156 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
158 camss: camss@1b0ac00 {
159 compatible = "qcom,msm8916-camss";
161 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
162 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
163 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
164 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
165 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
166 <&gcc GCC_CAMSS_CSI0_CLK>,
167 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
168 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
169 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
170 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
171 <&gcc GCC_CAMSS_CSI1_CLK>,
172 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
173 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
174 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
175 <&gcc GCC_CAMSS_AHB_CLK>,
176 <&gcc GCC_CAMSS_VFE0_CLK>,
177 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
178 <&gcc GCC_CAMSS_VFE_AHB_CLK>,
179 <&gcc GCC_CAMSS_VFE_AXI_CLK>;
181 clock-names = "top_ahb",
201 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
202 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
203 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
204 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
205 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
206 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
208 interrupt-names = "csiphy0",
215 iommus = <&apps_iommu 3>;
217 power-domains = <&gcc VFE_GDSC>;
219 reg = <0x01b0ac00 0x200>,
229 reg-names = "csiphy0",
239 vdda-supply = <®_2v8>;
242 #address-cells = <1>;