1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/media/qcom,msm8953-camss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm MSM8953 Camera Subsystem (CAMSS)
10 - Barnabas Czeman <barnabas.czeman@mainlining.org>
13 The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms
17 const: qcom,msm8953-camss
43 - const: csiphy0_timer
44 - const: csiphy1_timer
45 - const: csiphy2_timer
77 - description: VFE0 GDSC - Video Front End, Global Distributed Switch Controller.
78 - description: VFE1 GDSC - Video Front End, Global Distributed Switch Controller.
86 $ref: /schemas/graph.yaml#/properties/ports
93 $ref: /schemas/graph.yaml#/$defs/port-base
94 unevaluatedProperties: false
96 Input port for receiving CSI data.
100 $ref: video-interfaces.yaml#
101 unevaluatedProperties: false
106 An array of physical data lanes indexes.
107 Position of an entry determines the logical
108 lane number, while the value of an entry
109 indicates physical lane index. Lane swapping
110 is supported. Physical lane indexes;
119 $ref: /schemas/graph.yaml#/$defs/port-base
120 unevaluatedProperties: false
122 Input port for receiving CSI data.
126 $ref: video-interfaces.yaml#
127 unevaluatedProperties: false
138 $ref: /schemas/graph.yaml#/$defs/port-base
139 unevaluatedProperties: false
141 Input port for receiving CSI data.
145 $ref: video-interfaces.yaml#
146 unevaluatedProperties: false
167 - const: csiphy0_clk_mux
169 - const: csiphy1_clk_mux
171 - const: csiphy2_clk_mux
178 Definition of the regulator used as analog power supply.
193 additionalProperties: false
197 #include <dt-bindings/interrupt-controller/arm-gic.h>
198 #include <dt-bindings/clock/qcom,gcc-msm8953.h>
200 camss: camss@1b00020 {
201 compatible = "qcom,msm8953-camss";
203 reg = <0x1b00020 0x10>,
216 reg-names = "csi_clk_mux",
230 clocks = <&gcc GCC_CAMSS_AHB_CLK>,
231 <&gcc GCC_CAMSS_CSI0_CLK>,
232 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
233 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
234 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
235 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
236 <&gcc GCC_CAMSS_CSI1_CLK>,
237 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
238 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
239 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
240 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
241 <&gcc GCC_CAMSS_CSI2_CLK>,
242 <&gcc GCC_CAMSS_CSI2_AHB_CLK>,
243 <&gcc GCC_CAMSS_CSI2PHY_CLK>,
244 <&gcc GCC_CAMSS_CSI2PIX_CLK>,
245 <&gcc GCC_CAMSS_CSI2RDI_CLK>,
246 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
247 <&gcc GCC_CAMSS_CSI_VFE1_CLK>,
248 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
249 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
250 <&gcc GCC_CAMSS_CSI2PHYTIMER_CLK>,
251 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
252 <&gcc GCC_CAMSS_MICRO_AHB_CLK>,
253 <&gcc GCC_CAMSS_TOP_AHB_CLK>,
254 <&gcc GCC_CAMSS_VFE0_CLK>,
255 <&gcc GCC_CAMSS_VFE0_AHB_CLK>,
256 <&gcc GCC_CAMSS_VFE0_AXI_CLK>,
257 <&gcc GCC_CAMSS_VFE1_CLK>,
258 <&gcc GCC_CAMSS_VFE1_AHB_CLK>,
259 <&gcc GCC_CAMSS_VFE1_AXI_CLK>;
291 interrupts = <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
292 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
293 <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
294 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
295 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
296 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
297 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
298 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
299 <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
300 interrupt-names = "csid0",
310 iommus = <&apps_iommu 0x14>;
312 power-domains = <&gcc VFE0_GDSC>,
314 power-domain-names = "vfe0", "vfe1";
316 vdda-supply = <®_2v8>;
319 #address-cells = <1>;