Documentation/devicetree/bindings/media/samsung,fimc.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/media/samsung,fimc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Samsung S5P/Exynos SoC Camera Subsystem (FIMC)
   8
   9 maintainers:
  10   - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  11   - Sylwester Nawrocki <s.nawrocki@samsung.com>
  12
  13 description: |
  14   The S5P/Exynos SoC Camera subsystem comprises of multiple sub-devices
  15   represented by separate device tree nodes. Currently this includes: Fully
  16   Integrated Mobile Camera (FIMC, in the S5P SoCs series known as CAMIF), MIPI
  17   CSIS, FIMC-LITE and FIMC-IS (ISP).
  18
  19 properties:
  20   compatible:
  21     const: samsung,fimc
  22
  23   ranges: true
  24
  25   '#address-cells':
  26     const: 1
  27
  28   '#size-cells':
  29     const: 1
  30
  31   '#clock-cells':
  32     const: 1
  33     description: |
  34       The clock specifier cell stores an index of a clock: 0, 1 for
  35       CAM_A_CLKOUT, CAM_B_CLKOUT clocks respectively.
  36
  37   clocks:
  38     minItems: 2
  39     maxItems: 4
  40
  41   clock-names:
  42     minItems: 2
  43     items:
  44       - const: sclk_cam0
  45       - const: sclk_cam1
  46       - const: pxl_async0
  47       - const: pxl_async1
  48
  49   clock-output-names:
  50     maxItems: 2
  51
  52   parallel-ports:
  53     $ref: /schemas/graph.yaml#/properties/ports
  54     description:
  55       Active parallel video input ports.
  56
  57     patternProperties:
  58       "^port@[01]$":
  59         $ref: /schemas/graph.yaml#/$defs/port-base
  60         unevaluatedProperties: false
  61         description:
  62           Camera A and camera B inputs.
  63
  64         properties:
  65           endpoint:
  66             $ref: /schemas/media/video-interfaces.yaml#
  67             unevaluatedProperties: false
  68
  69   pinctrl-names:
  70     minItems: 1
  71     items:
  72       - const: default
  73       - const: idle
  74       - const: active_a
  75       - const: active_b
  76
  77 patternProperties:
  78   "^csis@[0-9a-f]+$":
  79     type: object
  80     $ref: samsung,exynos4210-csis.yaml#
  81     description: MIPI CSI-2 receiver.
  82
  83   "^fimc@[0-9a-f]+$":
  84     type: object
  85     $ref: samsung,exynos4210-fimc.yaml#
  86     description: Fully Integrated Mobile Camera.
  87
  88   "^fimc-is@[0-9a-f]+$":
  89     type: object
  90     $ref: samsung,exynos4212-fimc-is.yaml#
  91     description: Imaging Subsystem (FIMC-IS).
  92
  93   "^fimc-lite@[0-9a-f]+$":
  94     type: object
  95     $ref: samsung,exynos4212-fimc-lite.yaml#
  96     description: Camera host interface (FIMC-LITE).
  97
  98 required:
  99   - compatible
 100   - '#address-cells'
 101   - '#clock-cells'
 102   - clocks
 103   - clock-names
 104   - clock-output-names
 105   - ranges
 106   - '#size-cells'
 107
 108 additionalProperties: false
 109
 110 examples:
 111   - |
 112     #include <dt-bindings/clock/exynos4.h>
 113     #include <dt-bindings/gpio/gpio.h>
 114     #include <dt-bindings/interrupt-controller/arm-gic.h>
 115
 116     camera@11800000 {
 117         compatible = "samsung,fimc";
 118         #clock-cells = <1>;
 119         #address-cells = <1>;
 120         #size-cells = <1>;
 121         ranges = <0x0 0x0 0xba1000>;
 122
 123         clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
 124                  <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
 125         clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
 126         clock-output-names = "cam_a_clkout", "cam_b_clkout";
 127
 128         assigned-clocks = <&clock CLK_MOUT_CAM0>,
 129                           <&clock CLK_MOUT_CAM1>;
 130         assigned-clock-parents = <&clock CLK_XUSBXTI>,
 131                                  <&clock CLK_XUSBXTI>;
 132
 133         pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>;
 134         pinctrl-names = "default";
 135
 136         fimc@0 {
 137             compatible = "samsung,exynos4212-fimc";
 138             reg = <0x00000000 0x1000>;
 139             interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 140             clocks = <&clock CLK_FIMC0>,
 141                      <&clock CLK_SCLK_FIMC0>;
 142             clock-names = "fimc", "sclk_fimc";
 143             power-domains = <&pd_cam>;
 144             samsung,sysreg = <&sys_reg>;
 145             iommus = <&sysmmu_fimc0>;
 146
 147             samsung,pix-limits = <4224 8192 1920 4224>;
 148             samsung,mainscaler-ext;
 149             samsung,isp-wb;
 150             samsung,cam-if;
 151         };
 152
 153         /* ... FIMC 1-3 */
 154
 155         csis@80000 {
 156             compatible = "samsung,exynos4210-csis";
 157             reg = <0x00080000 0x4000>;
 158             interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 159             clocks = <&clock CLK_CSIS0>,
 160                      <&clock CLK_SCLK_CSIS0>;
 161             clock-names = "csis", "sclk_csis";
 162             assigned-clocks = <&clock CLK_MOUT_CSIS0>,
 163                               <&clock CLK_SCLK_CSIS0>;
 164             assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
 165             assigned-clock-rates = <0>, <176000000>;
 166
 167             bus-width = <4>;
 168             power-domains = <&pd_cam>;
 169             phys = <&mipi_phy 0>;
 170             phy-names = "csis";
 171             #address-cells = <1>;
 172             #size-cells = <0>;
 173
 174             vddcore-supply = <&ldo8_reg>;
 175             vddio-supply = <&ldo10_reg>;
 176
 177             /* Camera C (3) MIPI CSI-2 (CSIS0) */
 178             port@3 {
 179                 reg = <3>;
 180                 endpoint {
 181                     remote-endpoint = <&s5c73m3_ep>;
 182                     data-lanes = <1 2 3 4>;
 183                     samsung,csis-hs-settle = <12>;
 184                 };
 185             };
 186         };
 187
 188         /* ... CSIS 1 */
 189
 190         fimc-lite@b90000 {
 191               compatible = "samsung,exynos4212-fimc-lite";
 192               reg = <0xb90000 0x1000>;
 193               interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 194               power-domains = <&pd_isp>;
 195               clocks = <&isp_clock CLK_ISP_FIMC_LITE0>;
 196               clock-names = "flite";
 197               iommus = <&sysmmu_fimc_lite0>;
 198         };
 199
 200         /* ... FIMC-LITE 1 */
 201
 202         fimc-is@800000 {
 203             compatible = "samsung,exynos4212-fimc-is";
 204             reg = <0x00800000 0x260000>;
 205             interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 206                          <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 207             clocks = <&isp_clock CLK_ISP_FIMC_LITE0>,
 208                      <&isp_clock CLK_ISP_FIMC_LITE1>,
 209                      <&isp_clock CLK_ISP_PPMUISPX>,
 210                      <&isp_clock CLK_ISP_PPMUISPMX>,
 211                      <&isp_clock CLK_ISP_FIMC_ISP>,
 212                      <&isp_clock CLK_ISP_FIMC_DRC>,
 213                      <&isp_clock CLK_ISP_FIMC_FD>,
 214                      <&isp_clock CLK_ISP_MCUISP>,
 215                      <&isp_clock CLK_ISP_GICISP>,
 216                      <&isp_clock CLK_ISP_MCUCTL_ISP>,
 217                      <&isp_clock CLK_ISP_PWM_ISP>,
 218                      <&isp_clock CLK_ISP_DIV_ISP0>,
 219                      <&isp_clock CLK_ISP_DIV_ISP1>,
 220                      <&isp_clock CLK_ISP_DIV_MCUISP0>,
 221                      <&isp_clock CLK_ISP_DIV_MCUISP1>,
 222                      <&clock CLK_MOUT_MPLL_USER_T>,
 223                      <&clock CLK_ACLK200>,
 224                      <&clock CLK_ACLK400_MCUISP>,
 225                      <&clock CLK_DIV_ACLK200>,
 226                      <&clock CLK_DIV_ACLK400_MCUISP>,
 227                      <&clock CLK_UART_ISP_SCLK>;
 228             clock-names = "lite0", "lite1", "ppmuispx",
 229                           "ppmuispmx", "isp",
 230                           "drc", "fd", "mcuisp",
 231                           "gicisp", "mcuctl_isp", "pwm_isp",
 232                           "ispdiv0", "ispdiv1", "mcuispdiv0",
 233                           "mcuispdiv1", "mpll", "aclk200",
 234                           "aclk400mcuisp", "div_aclk200",
 235                           "div_aclk400mcuisp", "uart";
 236             iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
 237                      <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
 238             iommu-names = "isp", "drc", "fd", "mcuctl";
 239             power-domains = <&pd_isp>;
 240             samsung,pmu-syscon = <&pmu_system_controller>;
 241
 242             #address-cells = <1>;
 243             #size-cells = <1>;
 244             ranges;
 245
 246             i2c-isp@940000 {
 247                 compatible = "samsung,exynos4212-i2c-isp";
 248                 reg = <0x00940000 0x100>;
 249                 clocks = <&isp_clock CLK_ISP_I2C1_ISP>;
 250                 clock-names = "i2c_isp";
 251                 pinctrl-0 = <&fimc_is_i2c1>;
 252                 pinctrl-names = "default";
 253                 #address-cells = <1>;
 254                 #size-cells = <0>;
 255
 256                 image-sensor@10 {
 257                     compatible = "samsung,s5k6a3";
 258                     reg = <0x10>;
 259                     svdda-supply = <&cam_io_reg>;
 260                     svddio-supply = <&ldo19_reg>;
 261                     afvdd-supply = <&ldo19_reg>;
 262                     clock-frequency = <24000000>;
 263                     /* CAM_B_CLKOUT */
 264                     clocks = <&camera 1>;
 265                     clock-names = "extclk";
 266                     gpios = <&gpm1 6 GPIO_ACTIVE_LOW>;
 267
 268                     port {
 269                         endpoint {
 270                             remote-endpoint = <&csis1_ep>;
 271                             data-lanes = <1>;
 272                         };
 273                     };
 274                 };
 275             };
 276         };
 277     };