Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml

   1 # SPDX-License-Identifier: (GPL-2.0)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: NVIDIA Tegra124 SoC Memory Controller
   8
   9 maintainers:
  10   - Jon Hunter <jonathanh@nvidia.com>
  11   - Thierry Reding <thierry.reding@gmail.com>
  12
  13 description: |
  14   Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
  15   These are interleaved to provide high performance with the load shared across
  16   two memory channels. The Tegra124 Memory Controller handles memory requests
  17   from internal clients and arbitrates among them to allocate memory bandwidth
  18   for DDR3L and LPDDR3 SDRAMs.
  19
  20 properties:
  21   compatible:
  22     const: nvidia,tegra124-mc
  23
  24   reg:
  25     maxItems: 1
  26
  27   clocks:
  28     maxItems: 1
  29
  30   clock-names:
  31     items:
  32       - const: mc
  33
  34   interrupts:
  35     maxItems: 1
  36
  37   "#reset-cells":
  38     const: 1
  39
  40   "#iommu-cells":
  41     const: 1
  42
  43   "#interconnect-cells":
  44     const: 1
  45
  46 patternProperties:
  47   "^emc-timings-[0-9]+$":
  48     type: object
  49     properties:
  50       nvidia,ram-code:
  51         $ref: /schemas/types.yaml#/definitions/uint32
  52         description:
  53           Value of RAM_CODE this timing set is used for.
  54
  55     patternProperties:
  56       "^timing-[0-9]+$":
  57         type: object
  58         properties:
  59           clock-frequency:
  60             description:
  61               Memory clock rate in Hz.
  62             minimum: 1000000
  63             maximum: 1066000000
  64
  65           nvidia,emem-configuration:
  66             $ref: /schemas/types.yaml#/definitions/uint32-array
  67             description: |
  68               Values to be written to the EMEM register block. See section
  69               "15.6.1 MC Registers" in the TRM.
  70             items:
  71               - description: MC_EMEM_ARB_CFG
  72               - description: MC_EMEM_ARB_OUTSTANDING_REQ
  73               - description: MC_EMEM_ARB_TIMING_RCD
  74               - description: MC_EMEM_ARB_TIMING_RP
  75               - description: MC_EMEM_ARB_TIMING_RC
  76               - description: MC_EMEM_ARB_TIMING_RAS
  77               - description: MC_EMEM_ARB_TIMING_FAW
  78               - description: MC_EMEM_ARB_TIMING_RRD
  79               - description: MC_EMEM_ARB_TIMING_RAP2PRE
  80               - description: MC_EMEM_ARB_TIMING_WAP2PRE
  81               - description: MC_EMEM_ARB_TIMING_R2R
  82               - description: MC_EMEM_ARB_TIMING_W2W
  83               - description: MC_EMEM_ARB_TIMING_R2W
  84               - description: MC_EMEM_ARB_TIMING_W2R
  85               - description: MC_EMEM_ARB_DA_TURNS
  86               - description: MC_EMEM_ARB_DA_COVERS
  87               - description: MC_EMEM_ARB_MISC0
  88               - description: MC_EMEM_ARB_MISC1
  89               - description: MC_EMEM_ARB_RING1_THROTTLE
  90
  91         required:
  92           - clock-frequency
  93           - nvidia,emem-configuration
  94
  95         additionalProperties: false
  96
  97     required:
  98       - nvidia,ram-code
  99
 100     additionalProperties: false
 101
 102 required:
 103   - compatible
 104   - reg
 105   - interrupts
 106   - clocks
 107   - clock-names
 108   - "#reset-cells"
 109   - "#iommu-cells"
 110   - "#interconnect-cells"
 111
 112 additionalProperties: false
 113
 114 examples:
 115   - |
 116     memory-controller@70019000 {
 117         compatible = "nvidia,tegra124-mc";
 118         reg = <0x70019000 0x1000>;
 119         clocks = <&tegra_car 32>;
 120         clock-names = "mc";
 121
 122         interrupts = <0 77 4>;
 123
 124         #iommu-cells = <1>;
 125         #reset-cells = <1>;
 126         #interconnect-cells = <1>;
 127
 128         emc-timings-3 {
 129             nvidia,ram-code = <3>;
 130
 131             timing-12750000 {
 132                 clock-frequency = <12750000>;
 133
 134                 nvidia,emem-configuration = <
 135                     0x40040001 /* MC_EMEM_ARB_CFG */
 136                     0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
 137                     0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 138                     0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 139                     0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 140                     0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 141                     0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
 142                     0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 143                     0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 144                     0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 145                     0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
 146                     0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
 147                     0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
 148                     0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 149                     0x06030203 /* MC_EMEM_ARB_DA_TURNS */
 150                     0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
 151                     0x77e30303 /* MC_EMEM_ARB_MISC0 */
 152                     0x70000f03 /* MC_EMEM_ARB_MISC1 */
 153                     0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 154                 >;
 155             };
 156         };
 157     };