1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/mtd/marvell,nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell NAND Flash Controller (NFC)
10 - Miquel Raynal <miquel.raynal@bootlin.com>
16 - const: marvell,armada-8k-nand-controller
17 - const: marvell,armada370-nand-controller
19 - marvell,ac5-nand-controller
20 - marvell,armada370-nand-controller
21 - marvell,pxa3xx-nand-controller
22 - description: legacy bindings
25 - marvell,armada-8k-nand
26 - marvell,armada370-nand
37 Shall reference the NAND controller clocks, the second one is
38 is only needed for the Armada 7K/8K SoCs
55 marvell,system-controller:
56 $ref: /schemas/types.yaml#/definitions/phandle
57 description: Syscon node that handles NAND controller related registers
62 $ref: raw-nand-chip.yaml
78 enum: [1, 4, 8, 12, 16]
83 marvell,nand-keep-config:
84 $ref: /schemas/types.yaml#/definitions/flag
86 Orders the driver not to take the timings from the core and
87 leaving them completely untouched. Bootloader timings will then
90 marvell,nand-enable-arbiter:
91 $ref: /schemas/types.yaml#/definitions/flag
93 To enable the arbiter, all boards blindly used it,
94 this bit was set by the bootloader for many boards and even if
95 it is marked reserved in several datasheets, it might be needed to set
96 it (otherwise it is harmless).
103 unevaluatedProperties: false
112 - $ref: nand-controller.yaml#
118 const: marvell,pxa3xx-nand-controller
128 const: marvell,armada-8k-nand-controller
138 - marvell,system-controller
149 unevaluatedProperties: false
153 #include <dt-bindings/interrupt-controller/arm-gic.h>
154 nand_controller: nand-controller@d0000 {
155 compatible = "marvell,armada370-nand-controller";
156 reg = <0xd0000 0x54>;
157 #address-cells = <1>;
159 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&coredivclk 0>;
164 label = "main-storage";
166 nand-ecc-mode = "hw";
167 marvell,nand-keep-config;
169 nand-ecc-strength = <4>;
170 nand-ecc-step-size = <512>;
173 compatible = "fixed-partitions";
174 #address-cells = <1>;
179 reg = <0x00000000 0x40000000>;
186 cp0_nand_controller: nand-controller@720000 {
187 compatible = "marvell,armada-8k-nand-controller",
188 "marvell,armada370-nand-controller";
189 reg = <0x720000 0x54>;
190 #address-cells = <1>;
192 interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
193 clock-names = "core", "reg";
194 clocks = <&cp0_clk 1 2>,
196 marvell,system-controller = <&cp0_syscon0>;
200 label = "main-storage";
202 nand-ecc-mode = "hw";
203 nand-ecc-strength = <8>;
204 nand-ecc-step-size = <512>;
209 nand-controller@43100000 {
210 compatible = "marvell,pxa3xx-nand-controller";
211 reg = <0x43100000 90>;
214 clock-names = "core";
217 #address-cells = <1>;
222 nand-ecc-mode = "hw";
223 marvell,nand-keep-config;