Documentation/devicetree/bindings/pci/baikal,bt1-pcie.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Baikal-T1 PCIe Root Port Controller
   8
   9 maintainers:
  10   - Serge Semin <fancer.lancer@gmail.com>
  11
  12 description:
  13   Embedded into Baikal-T1 SoC Root Complex controller with a single port
  14   activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured
  15   to have just a single Root Port function and is capable of establishing the
  16   link up to Gen.3 speed on x4 lanes. It doesn't have embedded clock and reset
  17   control module, so the proper interface initialization is supposed to be
  18   performed by software. There four in- and four outbound iATU regions
  19   which can be used to emit all required TLP types on the PCIe bus.
  20
  21 allOf:
  22   - $ref: /schemas/pci/snps,dw-pcie.yaml#
  23
  24 properties:
  25   compatible:
  26     const: baikal,bt1-pcie
  27
  28   reg:
  29     description:
  30       DBI, DBI2 and at least 4KB outbound iATU-capable region for the
  31       peripheral devices CFG-space access.
  32     maxItems: 3
  33
  34   reg-names:
  35     items:
  36       - const: dbi
  37       - const: dbi2
  38       - const: config
  39
  40   interrupts:
  41     description:
  42       MSI, AER, PME, Hot-plug, Link Bandwidth Management, Link Equalization
  43       request and eight Read/Write eDMA IRQ lines are available.
  44     maxItems: 14
  45
  46   interrupt-names:
  47     items:
  48       - const: dma0
  49       - const: dma1
  50       - const: dma2
  51       - const: dma3
  52       - const: dma4
  53       - const: dma5
  54       - const: dma6
  55       - const: dma7
  56       - const: msi
  57       - const: aer
  58       - const: pme
  59       - const: hp
  60       - const: bw_mg
  61       - const: l_eq
  62
  63   clocks:
  64     description:
  65       DBI (attached to the APB bus), AXI-bus master and slave interfaces
  66       are fed up by the dedicated application clocks. A common reference
  67       clock signal is supposed to be attached to the corresponding Ref-pad
  68       of the SoC. It will be redistributed amongst the controller core
  69       sub-modules (pipe, core, aux, etc).
  70     maxItems: 4
  71
  72   clock-names:
  73     items:
  74       - const: dbi
  75       - const: mstr
  76       - const: slv
  77       - const: ref
  78
  79   resets:
  80     description:
  81       A comprehensive controller reset logic is supposed to be implemented
  82       by software, so almost all the possible application and core reset
  83       signals are exposed via the system CCU module.
  84     maxItems: 9
  85
  86   reset-names:
  87     items:
  88       - const: mstr
  89       - const: slv
  90       - const: pwr
  91       - const: hot
  92       - const: phy
  93       - const: core
  94       - const: pipe
  95       - const: sticky
  96       - const: non-sticky
  97
  98   baikal,bt1-syscon:
  99     $ref: /schemas/types.yaml#/definitions/phandle
 100     description:
 101       Phandle to the Baikal-T1 System Controller DT node. It's required to
 102       access some additional PM, Reset-related and LTSSM signals.
 103
 104   num-lanes:
 105     maximum: 4
 106
 107   max-link-speed:
 108     maximum: 3
 109
 110 required:
 111   - compatible
 112   - reg
 113   - reg-names
 114   - interrupts
 115   - interrupt-names
 116
 117 unevaluatedProperties: false
 118
 119 examples:
 120   - |
 121     #include <dt-bindings/interrupt-controller/mips-gic.h>
 122     #include <dt-bindings/gpio/gpio.h>
 123
 124     pcie@1f052000 {
 125       compatible = "baikal,bt1-pcie";
 126       device_type = "pci";
 127       reg = <0x1f052000 0x1000>, <0x1f053000 0x1000>, <0x1bdbf000 0x1000>;
 128       reg-names = "dbi", "dbi2", "config";
 129       #address-cells = <3>;
 130       #size-cells = <2>;
 131       ranges = <0x81000000 0 0x00000000 0x1bdb0000 0 0x00008000>,
 132                <0x82000000 0 0x20000000 0x08000000 0 0x13db0000>;
 133       bus-range = <0x0 0xff>;
 134
 135       interrupts = <GIC_SHARED 80 IRQ_TYPE_LEVEL_HIGH>,
 136                    <GIC_SHARED 81 IRQ_TYPE_LEVEL_HIGH>,
 137                    <GIC_SHARED 82 IRQ_TYPE_LEVEL_HIGH>,
 138                    <GIC_SHARED 83 IRQ_TYPE_LEVEL_HIGH>,
 139                    <GIC_SHARED 84 IRQ_TYPE_LEVEL_HIGH>,
 140                    <GIC_SHARED 85 IRQ_TYPE_LEVEL_HIGH>,
 141                    <GIC_SHARED 86 IRQ_TYPE_LEVEL_HIGH>,
 142                    <GIC_SHARED 87 IRQ_TYPE_LEVEL_HIGH>,
 143                    <GIC_SHARED 88 IRQ_TYPE_LEVEL_HIGH>,
 144                    <GIC_SHARED 89 IRQ_TYPE_LEVEL_HIGH>,
 145                    <GIC_SHARED 90 IRQ_TYPE_LEVEL_HIGH>,
 146                    <GIC_SHARED 91 IRQ_TYPE_LEVEL_HIGH>,
 147                    <GIC_SHARED 92 IRQ_TYPE_LEVEL_HIGH>,
 148                    <GIC_SHARED 93 IRQ_TYPE_LEVEL_HIGH>;
 149       interrupt-names = "dma0", "dma1", "dma2", "dma3",
 150                         "dma4", "dma5", "dma6", "dma7",
 151                         "msi", "aer", "pme", "hp", "bw_mg",
 152                         "l_eq";
 153
 154       clocks = <&ccu_sys 1>, <&ccu_axi 6>, <&ccu_axi 7>, <&clk_pcie>;
 155       clock-names = "dbi", "mstr", "slv", "ref";
 156
 157       resets = <&ccu_axi 6>, <&ccu_axi 7>, <&ccu_sys 7>, <&ccu_sys 10>,
 158                <&ccu_sys 4>, <&ccu_sys 6>, <&ccu_sys 5>, <&ccu_sys 8>,
 159                <&ccu_sys 9>;
 160       reset-names = "mstr", "slv", "pwr", "hot", "phy", "core", "pipe",
 161                     "sticky", "non-sticky";
 162
 163       reset-gpios = <&port0 0 GPIO_ACTIVE_LOW>;
 164
 165       num-lanes = <4>;
 166       max-link-speed = <3>;
 167     };
 168 ...