Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm X1E80100 PCI Express Root Complex
   8
   9 maintainers:
  10   - Bjorn Andersson <andersson@kernel.org>
  11   - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  12
  13 description:
  14   Qualcomm X1E80100 SoC (and compatible) PCIe root complex controller is based on
  15   the Synopsys DesignWare PCIe IP.
  16
  17 properties:
  18   compatible:
  19     const: qcom,pcie-x1e80100
  20
  21   reg:
  22     minItems: 6
  23     maxItems: 6
  24
  25   reg-names:
  26     items:
  27       - const: parf # Qualcomm specific registers
  28       - const: dbi # DesignWare PCIe registers
  29       - const: elbi # External local bus interface registers
  30       - const: atu # ATU address space
  31       - const: config # PCIe configuration space
  32       - const: mhi # MHI registers
  33
  34   clocks:
  35     minItems: 7
  36     maxItems: 7
  37
  38   clock-names:
  39     items:
  40       - const: aux # Auxiliary clock
  41       - const: cfg # Configuration clock
  42       - const: bus_master # Master AXI clock
  43       - const: bus_slave # Slave AXI clock
  44       - const: slave_q2a # Slave Q2A clock
  45       - const: noc_aggr # Aggre NoC PCIe AXI clock
  46       - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
  47
  48   interrupts:
  49     minItems: 8
  50     maxItems: 9
  51
  52   interrupt-names:
  53     minItems: 8
  54     items:
  55       - const: msi0
  56       - const: msi1
  57       - const: msi2
  58       - const: msi3
  59       - const: msi4
  60       - const: msi5
  61       - const: msi6
  62       - const: msi7
  63       - const: global
  64
  65   resets:
  66     minItems: 1
  67     maxItems: 2
  68
  69   reset-names:
  70     minItems: 1
  71     items:
  72       - const: pci # PCIe core reset
  73       - const: link_down # PCIe link down reset
  74
  75 allOf:
  76   - $ref: qcom,pcie-common.yaml#
  77
  78 unevaluatedProperties: false
  79
  80 examples:
  81   - |
  82     #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
  83     #include <dt-bindings/gpio/gpio.h>
  84     #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
  85     #include <dt-bindings/interrupt-controller/arm-gic.h>
  86
  87     soc {
  88         #address-cells = <2>;
  89         #size-cells = <2>;
  90
  91         pcie@1c08000 {
  92             compatible = "qcom,pcie-x1e80100";
  93             reg = <0 0x01c08000 0 0x3000>,
  94                   <0 0x7c000000 0 0xf1d>,
  95                   <0 0x7c000f40 0 0xa8>,
  96                   <0 0x7c001000 0 0x1000>,
  97                   <0 0x7c100000 0 0x100000>,
  98                   <0 0x01c0b000 0 0x1000>;
  99             reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
 100             ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
 101                      <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
 102
 103             bus-range = <0x00 0xff>;
 104             device_type = "pci";
 105             linux,pci-domain = <0>;
 106             num-lanes = <2>;
 107
 108             #address-cells = <3>;
 109             #size-cells = <2>;
 110
 111             clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
 112                      <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
 113                      <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
 114                      <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
 115                      <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
 116                      <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
 117                      <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
 118             clock-names = "aux",
 119                           "cfg",
 120                           "bus_master",
 121                           "bus_slave",
 122                           "slave_q2a",
 123                           "noc_aggr",
 124                           "cnoc_sf_axi";
 125
 126             dma-coherent;
 127
 128             interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 129                          <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 130                          <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
 131                          <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
 132                          <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 133                          <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 134                          <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 135                          <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 136                          <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 137             interrupt-names = "msi0", "msi1", "msi2", "msi3",
 138                               "msi4", "msi5", "msi6", "msi7", "global";
 139             #interrupt-cells = <1>;
 140             interrupt-map-mask = <0 0 0 0x7>;
 141             interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 142                             <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 143                             <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 144                             <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 145
 146             interconnects = <&pcie_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
 147                             <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_4 0>;
 148             interconnect-names = "pcie-mem", "cpu-pcie";
 149
 150             iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
 151                         <0x100 &apps_smmu 0x1401 0x1>;
 152
 153             phys = <&pcie4_phy>;
 154             phy-names = "pciephy";
 155
 156             pinctrl-0 = <&pcie0_default_state>;
 157             pinctrl-names = "default";
 158
 159             power-domains = <&gcc GCC_PCIE_4_GDSC>;
 160
 161             resets = <&gcc GCC_PCIE_4_BCR>;
 162             reset-names = "pci";
 163
 164             perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
 165             wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
 166         };
 167     };