Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: StarFive JH7110 PCIe host controller
   8
   9 maintainers:
  10   - Kevin Xie <kevin.xie@starfivetech.com>
  11
  12 allOf:
  13   - $ref: plda,xpressrich3-axi-common.yaml#
  14
  15 properties:
  16   compatible:
  17     const: starfive,jh7110-pcie
  18
  19
  20   reg:
  21     maxItems: 2
  22
  23   reg-names:
  24     maxItems: 2
  25
  26   clocks:
  27     items:
  28       - description: NOC bus clock
  29       - description: Transport layer clock
  30       - description: AXI MST0 clock
  31       - description: APB clock
  32
  33   clock-names:
  34     items:
  35       - const: noc
  36       - const: tl
  37       - const: axi_mst0
  38       - const: apb
  39
  40   resets:
  41     items:
  42       - description: AXI MST0 reset
  43       - description: AXI SLAVE0 reset
  44       - description: AXI SLAVE reset
  45       - description: PCIE BRIDGE reset
  46       - description: PCIE CORE reset
  47       - description: PCIE APB reset
  48
  49   reset-names:
  50     items:
  51       - const: mst0
  52       - const: slv0
  53       - const: slv
  54       - const: brg
  55       - const: core
  56       - const: apb
  57
  58   starfive,stg-syscon:
  59     $ref: /schemas/types.yaml#/definitions/phandle-array
  60     description:
  61       The phandle to System Register Controller syscon node.
  62
  63   perst-gpios:
  64     description: GPIO controlled connection to PERST# signal
  65     maxItems: 1
  66
  67   phys:
  68     description:
  69       Specified PHY is attached to PCIe controller.
  70     maxItems: 1
  71
  72 required:
  73   - clocks
  74   - resets
  75   - starfive,stg-syscon
  76
  77 unevaluatedProperties: false
  78
  79 examples:
  80   - |
  81     #include <dt-bindings/gpio/gpio.h>
  82     soc {
  83         #address-cells = <2>;
  84         #size-cells = <2>;
  85
  86         pcie@940000000 {
  87             compatible = "starfive,jh7110-pcie";
  88             reg = <0x9 0x40000000 0x0 0x10000000>,
  89                   <0x0 0x2b000000 0x0 0x1000000>;
  90             reg-names = "cfg", "apb";
  91             #address-cells = <3>;
  92             #size-cells = <2>;
  93             #interrupt-cells = <1>;
  94             device_type = "pci";
  95             ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,
  96                      <0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;
  97             starfive,stg-syscon = <&stg_syscon>;
  98             bus-range = <0x0 0xff>;
  99             interrupt-parent = <&plic>;
 100             interrupts = <56>;
 101             interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 102             interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
 103                             <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
 104                             <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
 105                             <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
 106             msi-controller;
 107             clocks = <&syscrg 86>,
 108                      <&stgcrg 10>,
 109                      <&stgcrg 8>,
 110                      <&stgcrg 9>;
 111             clock-names = "noc", "tl", "axi_mst0", "apb";
 112             resets = <&stgcrg 11>,
 113                      <&stgcrg 12>,
 114                      <&stgcrg 13>,
 115                      <&stgcrg 14>,
 116                      <&stgcrg 15>,
 117                      <&stgcrg 16>;
 118             perst-gpios = <&gpios 26 GPIO_ACTIVE_LOW>;
 119             phys = <&pciephy0>;
 120
 121             pcie_intc0: interrupt-controller {
 122                 #address-cells = <0>;
 123                 #interrupt-cells = <1>;
 124                 interrupt-controller;
 125             };
 126         };
 127     };