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[drm/drm-misc.git] / Documentation / devicetree / bindings / remoteproc / ti,davinci-rproc.txt
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1 TI Davinci DSP devices
2 =======================
4 The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that
5 is used to offload some of the processor-intensive tasks or algorithms, for
6 achieving various system level goals.
8 The processor cores in the sub-system usually contain additional sub-modules
9 like L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory
10 controller, a dedicated local power/sleep controller etc. The DSP processor
11 core used in Davinci SoCs is usually a C674x DSP CPU.
13 DSP Device Node:
14 ================
15 Each DSP Core sub-system is represented as a single DT node.
17 Required properties:
18 --------------------
19 The following are the mandatory properties:
21 - compatible:           Should be one of the following,
22                             "ti,da850-dsp" for DSPs on OMAP-L138 SoCs
24 - reg:                  Should contain an entry for each value in 'reg-names'.
25                         Each entry should have the memory region's start address
26                         and the size of the region, the representation matching
27                         the parent node's '#address-cells' and '#size-cells' values.
29 - reg-names:            Should contain strings with the following names, each
30                         representing a specific internal memory region or a
31                         specific register space,
32                              "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig_base"
34 - interrupts:           Should contain the interrupt number used to receive the
35                         interrupts from the DSP. The value should follow the
36                         interrupt-specifier format as dictated by the
37                         'interrupt-parent' node.
39 - memory-region:        phandle to the reserved memory node to be associated
40                         with the remoteproc device. The reserved memory node
41                         can be a CMA memory node, and should be defined as
42                         per the bindings in
43                         Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
46 Example:
47 --------
49         /* DSP Reserved Memory node */
50         reserved-memory {
51                 #address-cells = <1>;
52                 #size-cells = <1>;
53                 ranges;
55                 dsp_memory_region: dsp-memory@c3000000 {
56                         compatible = "shared-dma-pool";
57                         reg = <0xc3000000 0x1000000>;
58                         reusable;
59                 };
60         };
62         /* DSP node */
63         {
64                 dsp: dsp@11800000 {
65                         compatible = "ti,da850-dsp";
66                         reg = <0x11800000 0x40000>,
67                               <0x11e00000 0x8000>,
68                               <0x11f00000 0x8000>,
69                               <0x01c14044 0x4>,
70                               <0x01c14174 0x8>;
71                         reg-names = "l2sram", "l1pram", "l1dram", "host1cfg",
72                                     "chipsig";
73                         interrupt-parent = <&intc>;
74                         interrupts = <28>;
75                         memory-region = <&dsp_memory_region>;
76                 };
77         };