Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/spmi/mtk,spmi-mtk-pmif.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Mediatek SPMI Controller
   8
   9 maintainers:
  10   - Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
  11
  12 description: |+
  13   On MediaTek SoCs the PMIC is connected via SPMI and the controller allows
  14   for multiple SoCs to control a single SPMI master.
  15
  16 allOf:
  17   - $ref: spmi.yaml
  18
  19 properties:
  20   compatible:
  21     oneOf:
  22       - enum:
  23           - mediatek,mt6873-spmi
  24           - mediatek,mt8195-spmi
  25       - items:
  26           - enum:
  27               - mediatek,mt8186-spmi
  28               - mediatek,mt8188-spmi
  29           - const: mediatek,mt8195-spmi
  30
  31   reg:
  32     maxItems: 2
  33
  34   reg-names:
  35     items:
  36       - const: pmif
  37       - const: spmimst
  38
  39   clocks:
  40     minItems: 3
  41     maxItems: 3
  42
  43   clock-names:
  44     items:
  45       - const: pmif_sys_ck
  46       - const: pmif_tmr_ck
  47       - const: spmimst_clk_mux
  48
  49   assigned-clocks:
  50     maxItems: 1
  51
  52   assigned-clock-parents:
  53     maxItems: 1
  54
  55 required:
  56   - compatible
  57   - reg
  58   - reg-names
  59   - clocks
  60   - clock-names
  61
  62 unevaluatedProperties: false
  63
  64 examples:
  65   - |
  66     #include <dt-bindings/clock/mt8192-clk.h>
  67
  68     spmi: spmi@10027000 {
  69         compatible = "mediatek,mt6873-spmi";
  70         reg = <0x10027000 0xe00>,
  71               <0x10029000 0x100>;
  72         reg-names = "pmif", "spmimst";
  73         clocks = <&infracfg CLK_INFRA_PMIC_AP>,
  74                  <&infracfg CLK_INFRA_PMIC_TMR>,
  75                  <&topckgen CLK_TOP_SPMI_MST_SEL>;
  76         clock-names = "pmif_sys_ck",
  77                       "pmif_tmr_ck",
  78                       "spmimst_clk_mux";
  79         assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
  80         assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
  81     };
  82 ...