arch/powerpc/include/asm/barrier.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
   4  */
   5 #ifndef _ASM_POWERPC_BARRIER_H
   6 #define _ASM_POWERPC_BARRIER_H
   7
   8 #include <asm/asm-const.h>
   9
  10 #ifndef __ASSEMBLY__
  11 #include <asm/ppc-opcode.h>
  12 #endif
  13
  14 /*
  15  * Memory barrier.
  16  * The sync instruction guarantees that all memory accesses initiated
  17  * by this processor have been performed (with respect to all other
  18  * mechanisms that access memory).  The eieio instruction is a barrier
  19  * providing an ordering (separately) for (a) cacheable stores and (b)
  20  * loads and stores to non-cacheable memory (e.g. I/O devices).
  21  *
  22  * mb() prevents loads and stores being reordered across this point.
  23  * rmb() prevents loads being reordered across this point.
  24  * wmb() prevents stores being reordered across this point.
  25  *
  26  * *mb() variants without smp_ prefix must order all types of memory
  27  * operations with one another. sync is the only instruction sufficient
  28  * to do this.
  29  *
  30  * For the smp_ barriers, ordering is for cacheable memory operations
  31  * only. We have to use the sync instruction for smp_mb(), since lwsync
  32  * doesn't order loads with respect to previous stores.  Lwsync can be
  33  * used for smp_rmb() and smp_wmb().
  34  *
  35  * However, on CPUs that don't support lwsync, lwsync actually maps to a
  36  * heavy-weight sync, so smp_wmb() can be a lighter-weight eieio.
  37  */
  38 #define __mb()   __asm__ __volatile__ ("sync" : : : "memory")
  39 #define __rmb()  __asm__ __volatile__ ("sync" : : : "memory")
  40 #define __wmb()  __asm__ __volatile__ ("sync" : : : "memory")
  41
  42 /* The sub-arch has lwsync */
  43 #if defined(CONFIG_PPC64) || defined(CONFIG_PPC_E500MC)
  44 #    define SMPWMB      LWSYNC
  45 #elif defined(CONFIG_BOOKE)
  46 #    define SMPWMB      mbar
  47 #else
  48 #    define SMPWMB      eieio
  49 #endif
  50
  51 /* clang defines this macro for a builtin, which will not work with runtime patching */
  52 #undef __lwsync
  53 #define __lwsync()      __asm__ __volatile__ (stringify_in_c(LWSYNC) : : :"memory")
  54 #define __dma_rmb()     __lwsync()
  55 #define __dma_wmb()     __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory")
  56
  57 #define __smp_lwsync()  __lwsync()
  58
  59 #define __smp_mb()      __mb()
  60 #define __smp_rmb()     __lwsync()
  61 #define __smp_wmb()     __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory")
  62
  63 /*
  64  * This is a barrier which prevents following instructions from being
  65  * started until the value of the argument x is known.  For example, if
  66  * x is a variable loaded from memory, this prevents following
  67  * instructions from being executed until the load has been performed.
  68  */
  69 #define data_barrier(x) \
  70         asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
  71
  72 #define __smp_store_release(p, v)                                               \
  73 do {                                                                    \
  74         compiletime_assert_atomic_type(*p);                             \
  75         __smp_lwsync();                                                 \
  76         WRITE_ONCE(*p, v);                                              \
  77 } while (0)
  78
  79 #define __smp_load_acquire(p)                                           \
  80 ({                                                                      \
  81         typeof(*p) ___p1 = READ_ONCE(*p);                               \
  82         compiletime_assert_atomic_type(*p);                             \
  83         __smp_lwsync();                                                 \
  84         ___p1;                                                          \
  85 })
  86
  87 #ifdef CONFIG_PPC_BOOK3S_64
  88 #define NOSPEC_BARRIER_SLOT   nop
  89 #elif defined(CONFIG_PPC_E500)
  90 #define NOSPEC_BARRIER_SLOT   nop; nop
  91 #endif
  92
  93 #ifdef CONFIG_PPC_BARRIER_NOSPEC
  94 /*
  95  * Prevent execution of subsequent instructions until preceding branches have
  96  * been fully resolved and are no longer executing speculatively.
  97  */
  98 #define barrier_nospec_asm NOSPEC_BARRIER_FIXUP_SECTION; NOSPEC_BARRIER_SLOT
  99
 100 // This also acts as a compiler barrier due to the memory clobber.
 101 #define barrier_nospec() asm (stringify_in_c(barrier_nospec_asm) ::: "memory")
 102
 103 #else /* !CONFIG_PPC_BARRIER_NOSPEC */
 104 #define barrier_nospec_asm
 105 #define barrier_nospec()
 106 #endif /* CONFIG_PPC_BARRIER_NOSPEC */
 107
 108 /*
 109  * pmem_wmb() ensures that all stores for which the modification
 110  * are written to persistent storage by preceding dcbfps/dcbstps
 111  * instructions have updated persistent storage before any data
 112  * access or data transfer caused by subsequent instructions is
 113  * initiated.
 114  */
 115 #define pmem_wmb() __asm__ __volatile__(PPC_PHWSYNC ::: "memory")
 116
 117 #include <asm-generic/barrier.h>
 118
 119 #endif /* _ASM_POWERPC_BARRIER_H */