arch/powerpc/include/asm/mmu.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_POWERPC_MMU_H_
   3 #define _ASM_POWERPC_MMU_H_
   4 #ifdef __KERNEL__
   5
   6 #include <linux/types.h>
   7
   8 #include <asm/asm-const.h>
   9
  10 /*
  11  * MMU features bit definitions
  12  */
  13
  14 /*
  15  * MMU families
  16  */
  17 #define MMU_FTR_HPTE_TABLE              ASM_CONST(0x00000001)
  18 #define MMU_FTR_TYPE_8xx                ASM_CONST(0x00000002)
  19 #define MMU_FTR_TYPE_44x                ASM_CONST(0x00000008)
  20 #define MMU_FTR_TYPE_FSL_E              ASM_CONST(0x00000010)
  21 #define MMU_FTR_TYPE_47x                ASM_CONST(0x00000020)
  22
  23 /* Radix page table supported and enabled */
  24 #define MMU_FTR_TYPE_RADIX              ASM_CONST(0x00000040)
  25
  26 /*
  27  * Individual features below.
  28  */
  29
  30 /*
  31  * Supports KUAP feature
  32  * key 0 controlling userspace addresses on radix
  33  * Key 3 on hash
  34  */
  35 #define MMU_FTR_KUAP            ASM_CONST(0x00000200)
  36
  37 /*
  38  * Supports KUEP feature
  39  * key 0 controlling userspace addresses on radix
  40  * Key 3 on hash
  41  */
  42 #define MMU_FTR_BOOK3S_KUEP             ASM_CONST(0x00000400)
  43
  44 /*
  45  * Support for memory protection keys.
  46  */
  47 #define MMU_FTR_PKEY                    ASM_CONST(0x00000800)
  48
  49 /* Guest Translation Shootdown Enable */
  50 #define MMU_FTR_GTSE                    ASM_CONST(0x00001000)
  51
  52 /*
  53  * Support for 68 bit VA space. We added that from ISA 2.05
  54  */
  55 #define MMU_FTR_68_BIT_VA               ASM_CONST(0x00002000)
  56 /*
  57  * Kernel read only support.
  58  * We added the ppp value 0b110 in ISA 2.04.
  59  */
  60 #define MMU_FTR_KERNEL_RO               ASM_CONST(0x00004000)
  61
  62 /*
  63  * We need to clear top 16bits of va (from the remaining 64 bits )in
  64  * tlbie* instructions
  65  */
  66 #define MMU_FTR_TLBIE_CROP_VA           ASM_CONST(0x00008000)
  67
  68 /* Enable use of high BAT registers */
  69 #define MMU_FTR_USE_HIGH_BATS           ASM_CONST(0x00010000)
  70
  71 /* Enable >32-bit physical addresses on 32-bit processor, only used
  72  * by CONFIG_PPC_BOOK3S_32 currently as BookE supports that from day 1
  73  */
  74 #define MMU_FTR_BIG_PHYS                ASM_CONST(0x00020000)
  75
  76 /* Enable use of broadcast TLB invalidations. We don't always set it
  77  * on processors that support it due to other constraints with the
  78  * use of such invalidations
  79  */
  80 #define MMU_FTR_USE_TLBIVAX_BCAST       ASM_CONST(0x00040000)
  81
  82 /* Enable use of tlbilx invalidate instructions.
  83  */
  84 #define MMU_FTR_USE_TLBILX              ASM_CONST(0x00080000)
  85
  86 /* This indicates that the processor cannot handle multiple outstanding
  87  * broadcast tlbivax or tlbsync. This makes the code use a spinlock
  88  * around such invalidate forms.
  89  */
  90 #define MMU_FTR_LOCK_BCAST_INVAL        ASM_CONST(0x00100000)
  91
  92 /* This indicates that the processor doesn't handle way selection
  93  * properly and needs SW to track and update the LRU state.  This
  94  * is specific to an errata on e300c2/c3/c4 class parts
  95  */
  96 #define MMU_FTR_NEED_DTLB_SW_LRU        ASM_CONST(0x00200000)
  97
  98 /* Doesn't support the B bit (1T segment) in SLBIE
  99  */
 100 #define MMU_FTR_NO_SLBIE_B              ASM_CONST(0x02000000)
 101
 102 /* Support 16M large pages
 103  */
 104 #define MMU_FTR_16M_PAGE                ASM_CONST(0x04000000)
 105
 106 /* Supports TLBIEL variant
 107  */
 108 #define MMU_FTR_TLBIEL                  ASM_CONST(0x08000000)
 109
 110 /* Supports tlbies w/o locking
 111  */
 112 #define MMU_FTR_LOCKLESS_TLBIE          ASM_CONST(0x10000000)
 113
 114 /* Large pages can be marked CI
 115  */
 116 #define MMU_FTR_CI_LARGE_PAGE           ASM_CONST(0x20000000)
 117
 118 /* 1T segments available
 119  */
 120 #define MMU_FTR_1T_SEGMENT              ASM_CONST(0x40000000)
 121
 122 // NX paste RMA reject in DSI
 123 #define MMU_FTR_NX_DSI                  ASM_CONST(0x80000000)
 124
 125 /* MMU feature bit sets for various CPUs */
 126 #define MMU_FTRS_DEFAULT_HPTE_ARCH_V2   (MMU_FTR_HPTE_TABLE | MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE)
 127 #define MMU_FTRS_POWER          MMU_FTRS_DEFAULT_HPTE_ARCH_V2
 128 #define MMU_FTRS_PPC970         MMU_FTRS_POWER | MMU_FTR_TLBIE_CROP_VA
 129 #define MMU_FTRS_POWER5         MMU_FTRS_POWER | MMU_FTR_LOCKLESS_TLBIE
 130 #define MMU_FTRS_POWER6         MMU_FTRS_POWER5 | MMU_FTR_KERNEL_RO | MMU_FTR_68_BIT_VA
 131 #define MMU_FTRS_POWER7         MMU_FTRS_POWER6
 132 #define MMU_FTRS_POWER8         MMU_FTRS_POWER6
 133 #define MMU_FTRS_POWER9         MMU_FTRS_POWER6
 134 #define MMU_FTRS_POWER10        MMU_FTRS_POWER6
 135 #define MMU_FTRS_POWER11        MMU_FTRS_POWER6
 136 #define MMU_FTRS_CELL           MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
 137                                 MMU_FTR_CI_LARGE_PAGE
 138 #define MMU_FTRS_PA6T           MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
 139                                 MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
 140 #ifndef __ASSEMBLY__
 141 #include <linux/bug.h>
 142 #include <asm/cputable.h>
 143 #include <asm/page.h>
 144
 145 typedef pte_t *pgtable_t;
 146
 147 enum {
 148         MMU_FTRS_POSSIBLE =
 149 #if defined(CONFIG_PPC_BOOK3S_604)
 150                 MMU_FTR_HPTE_TABLE |
 151 #endif
 152 #ifdef CONFIG_PPC_8xx
 153                 MMU_FTR_TYPE_8xx |
 154 #endif
 155 #ifdef CONFIG_PPC_47x
 156                 MMU_FTR_TYPE_47x | MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL |
 157 #elif defined(CONFIG_44x)
 158                 MMU_FTR_TYPE_44x |
 159 #endif
 160 #ifdef CONFIG_PPC_E500
 161                 MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | MMU_FTR_USE_TLBILX |
 162 #endif
 163 #ifdef CONFIG_PPC_BOOK3S_32
 164                 MMU_FTR_USE_HIGH_BATS |
 165 #endif
 166 #ifdef CONFIG_PPC_83xx
 167                 MMU_FTR_NEED_DTLB_SW_LRU |
 168 #endif
 169 #ifdef CONFIG_PPC_BOOK3S_64
 170                 MMU_FTR_KERNEL_RO |
 171 #ifdef CONFIG_PPC_64S_HASH_MMU
 172                 MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL |
 173                 MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE |
 174                 MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA |
 175                 MMU_FTR_68_BIT_VA | MMU_FTR_HPTE_TABLE |
 176 #endif
 177 #ifdef CONFIG_PPC_RADIX_MMU
 178                 MMU_FTR_TYPE_RADIX |
 179                 MMU_FTR_GTSE | MMU_FTR_NX_DSI |
 180 #endif /* CONFIG_PPC_RADIX_MMU */
 181 #endif
 182 #ifdef CONFIG_PPC_KUAP
 183         MMU_FTR_KUAP |
 184 #endif /* CONFIG_PPC_KUAP */
 185 #ifdef CONFIG_PPC_MEM_KEYS
 186         MMU_FTR_PKEY |
 187 #endif
 188 #ifdef CONFIG_PPC_KUEP
 189         MMU_FTR_BOOK3S_KUEP |
 190 #endif /* CONFIG_PPC_KUAP */
 191
 192                 0,
 193 };
 194
 195 #if defined(CONFIG_PPC_BOOK3S_604) && !defined(CONFIG_PPC_BOOK3S_603)
 196 #define MMU_FTRS_ALWAYS         MMU_FTR_HPTE_TABLE
 197 #endif
 198 #ifdef CONFIG_PPC_8xx
 199 #define MMU_FTRS_ALWAYS         MMU_FTR_TYPE_8xx
 200 #endif
 201 #ifdef CONFIG_PPC_47x
 202 #define MMU_FTRS_ALWAYS         MMU_FTR_TYPE_47x
 203 #elif defined(CONFIG_44x)
 204 #define MMU_FTRS_ALWAYS         MMU_FTR_TYPE_44x
 205 #endif
 206 #ifdef CONFIG_PPC_E500
 207 #define MMU_FTRS_ALWAYS         MMU_FTR_TYPE_FSL_E
 208 #endif
 209
 210 /* BOOK3S_64 options */
 211 #if defined(CONFIG_PPC_RADIX_MMU) && !defined(CONFIG_PPC_64S_HASH_MMU)
 212 #define MMU_FTRS_ALWAYS         MMU_FTR_TYPE_RADIX
 213 #elif !defined(CONFIG_PPC_RADIX_MMU) && defined(CONFIG_PPC_64S_HASH_MMU)
 214 #define MMU_FTRS_ALWAYS         MMU_FTR_HPTE_TABLE
 215 #endif
 216
 217 #ifndef MMU_FTRS_ALWAYS
 218 #define MMU_FTRS_ALWAYS         0
 219 #endif
 220
 221 static __always_inline bool early_mmu_has_feature(unsigned long feature)
 222 {
 223         if (MMU_FTRS_ALWAYS & feature)
 224                 return true;
 225
 226         return !!(MMU_FTRS_POSSIBLE & cur_cpu_spec->mmu_features & feature);
 227 }
 228
 229 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
 230 #include <linux/jump_label.h>
 231
 232 #define NUM_MMU_FTR_KEYS        32
 233
 234 extern struct static_key_true mmu_feature_keys[NUM_MMU_FTR_KEYS];
 235
 236 extern void mmu_feature_keys_init(void);
 237
 238 static __always_inline bool mmu_has_feature(unsigned long feature)
 239 {
 240         int i;
 241
 242         BUILD_BUG_ON(!__builtin_constant_p(feature));
 243         BUILD_BUG_ON(__builtin_popcountl(feature) > 1);
 244
 245 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECK_DEBUG
 246         if (!static_key_feature_checks_initialized) {
 247                 printk("Warning! mmu_has_feature() used prior to jump label init!\n");
 248                 dump_stack();
 249                 return early_mmu_has_feature(feature);
 250         }
 251 #endif
 252
 253         if (MMU_FTRS_ALWAYS & feature)
 254                 return true;
 255
 256         if (!(MMU_FTRS_POSSIBLE & feature))
 257                 return false;
 258
 259         i = __builtin_ctzl(feature);
 260         return static_branch_likely(&mmu_feature_keys[i]);
 261 }
 262
 263 static inline void mmu_clear_feature(unsigned long feature)
 264 {
 265         int i;
 266
 267         i = __builtin_ctzl(feature);
 268         cur_cpu_spec->mmu_features &= ~feature;
 269         static_branch_disable(&mmu_feature_keys[i]);
 270 }
 271 #else
 272
 273 static inline void mmu_feature_keys_init(void)
 274 {
 275
 276 }
 277
 278 static __always_inline bool mmu_has_feature(unsigned long feature)
 279 {
 280         return early_mmu_has_feature(feature);
 281 }
 282
 283 static inline void mmu_clear_feature(unsigned long feature)
 284 {
 285         cur_cpu_spec->mmu_features &= ~feature;
 286 }
 287 #endif /* CONFIG_JUMP_LABEL */
 288
 289 extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
 290
 291 #ifdef CONFIG_PPC64
 292 /* This is our real memory area size on ppc64 server, on embedded, we
 293  * make it match the size our of bolted TLB area
 294  */
 295 extern u64 ppc64_rma_size;
 296
 297 /* Cleanup function used by kexec */
 298 extern void mmu_cleanup_all(void);
 299 extern void radix__mmu_cleanup_all(void);
 300
 301 /* Functions for creating and updating partition table on POWER9 */
 302 extern void mmu_partition_table_init(void);
 303 extern void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,
 304                                           unsigned long dw1, bool flush);
 305 #endif /* CONFIG_PPC64 */
 306
 307 struct mm_struct;
 308 #ifdef CONFIG_DEBUG_VM
 309 extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr);
 310 #else /* CONFIG_DEBUG_VM */
 311 static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
 312 {
 313 }
 314 #endif /* !CONFIG_DEBUG_VM */
 315
 316 static __always_inline bool radix_enabled(void)
 317 {
 318         return mmu_has_feature(MMU_FTR_TYPE_RADIX);
 319 }
 320
 321 static __always_inline bool early_radix_enabled(void)
 322 {
 323         return early_mmu_has_feature(MMU_FTR_TYPE_RADIX);
 324 }
 325
 326 static inline bool strict_kernel_rwx_enabled(void)
 327 {
 328         return IS_ENABLED(CONFIG_STRICT_KERNEL_RWX) && rodata_enabled;
 329 }
 330
 331 static inline bool strict_module_rwx_enabled(void)
 332 {
 333         return IS_ENABLED(CONFIG_STRICT_MODULE_RWX) && strict_kernel_rwx_enabled();
 334 }
 335 #endif /* !__ASSEMBLY__ */
 336
 337 /* The kernel use the constants below to index in the page sizes array.
 338  * The use of fixed constants for this purpose is better for performances
 339  * of the low level hash refill handlers.
 340  *
 341  * A non supported page size has a "shift" field set to 0
 342  *
 343  * Any new page size being implemented can get a new entry in here. Whether
 344  * the kernel will use it or not is a different matter though. The actual page
 345  * size used by hugetlbfs is not defined here and may be made variable
 346  *
 347  * Note: This array ended up being a false good idea as it's growing to the
 348  * point where I wonder if we should replace it with something different,
 349  * to think about, feedback welcome. --BenH.
 350  */
 351
 352 /* These are #defines as they have to be used in assembly */
 353 #define MMU_PAGE_4K     0
 354 #define MMU_PAGE_16K    1
 355 #define MMU_PAGE_64K    2
 356 #define MMU_PAGE_64K_AP 3       /* "Admixed pages" (hash64 only) */
 357 #define MMU_PAGE_256K   4
 358 #define MMU_PAGE_512K   5
 359 #define MMU_PAGE_1M     6
 360 #define MMU_PAGE_2M     7
 361 #define MMU_PAGE_4M     8
 362 #define MMU_PAGE_8M     9
 363 #define MMU_PAGE_16M    10
 364 #define MMU_PAGE_64M    11
 365 #define MMU_PAGE_256M   12
 366 #define MMU_PAGE_1G     13
 367 #define MMU_PAGE_16G    14
 368 #define MMU_PAGE_64G    15
 369
 370 /*
 371  * N.B. we need to change the type of hpte_page_sizes if this gets to be > 16
 372  * Also we need to change he type of mm_context.low/high_slices_psize.
 373  */
 374 #define MMU_PAGE_COUNT  16
 375
 376 #ifdef CONFIG_PPC_BOOK3S_64
 377 #include <asm/book3s/64/mmu.h>
 378 #else /* CONFIG_PPC_BOOK3S_64 */
 379
 380 #ifndef __ASSEMBLY__
 381 /* MMU initialization */
 382 extern void early_init_mmu(void);
 383 extern void early_init_mmu_secondary(void);
 384 extern void setup_initial_memory_limit(phys_addr_t first_memblock_base,
 385                                        phys_addr_t first_memblock_size);
 386 static inline void mmu_early_init_devtree(void) { }
 387
 388 static inline void pkey_early_init_devtree(void) {}
 389
 390 extern void *abatron_pteptrs[2];
 391 #endif /* __ASSEMBLY__ */
 392 #endif
 393
 394 #if defined(CONFIG_PPC_BOOK3S_32)
 395 /* 32-bit classic hash table MMU */
 396 #include <asm/book3s/32/mmu-hash.h>
 397 #elif defined(CONFIG_PPC_MMU_NOHASH)
 398 #include <asm/nohash/mmu.h>
 399 #endif
 400
 401 #endif /* __KERNEL__ */
 402 #endif /* _ASM_POWERPC_MMU_H_ */