arch/powerpc/include/asm/paca.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * This control block defines the PACA which defines the processor
   4  * specific data for each logical processor on the system.
   5  * There are some pointers defined that are utilized by PLIC.
   6  *
   7  * C 2001 PPC 64 Team, IBM Corp
   8  */
   9 #ifndef _ASM_POWERPC_PACA_H
  10 #define _ASM_POWERPC_PACA_H
  11 #ifdef __KERNEL__
  12
  13 #ifdef CONFIG_PPC64
  14
  15 #include <linux/cache.h>
  16 #include <linux/string.h>
  17 #include <asm/types.h>
  18 #include <asm/mmu.h>
  19 #include <asm/page.h>
  20 #ifdef CONFIG_PPC_BOOK3E_64
  21 #include <asm/exception-64e.h>
  22 #else
  23 #include <asm/exception-64s.h>
  24 #endif
  25 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
  26 #include <asm/kvm_book3s_asm.h>
  27 #endif
  28 #include <asm/accounting.h>
  29 #include <asm/hmi.h>
  30 #include <asm/cpuidle.h>
  31 #include <asm/atomic.h>
  32 #include <asm/mce.h>
  33
  34 #include <asm-generic/mmiowb_types.h>
  35
  36 register struct paca_struct *local_paca asm("r13");
  37
  38 #if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP)
  39 extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */
  40 /*
  41  * Add standard checks that preemption cannot occur when using get_paca():
  42  * otherwise the paca_struct it points to may be the wrong one just after.
  43  */
  44 #define get_paca()      ((void) debug_smp_processor_id(), local_paca)
  45 #else
  46 #define get_paca()      local_paca
  47 #endif
  48
  49 #define get_slb_shadow()        (get_paca()->slb_shadow_ptr)
  50
  51 struct task_struct;
  52 struct rtas_args;
  53 struct lppaca;
  54
  55 /*
  56  * Defines the layout of the paca.
  57  *
  58  * This structure is not directly accessed by firmware or the service
  59  * processor.
  60  */
  61 struct paca_struct {
  62 #ifdef CONFIG_PPC_PSERIES
  63         /*
  64          * Because hw_cpu_id, unlike other paca fields, is accessed
  65          * routinely from other CPUs (from the IRQ code), we stick to
  66          * read-only (after boot) fields in the first cacheline to
  67          * avoid cacheline bouncing.
  68          */
  69
  70         struct lppaca *lppaca_ptr;      /* Pointer to LpPaca for PLIC */
  71 #endif /* CONFIG_PPC_PSERIES */
  72
  73         /*
  74          * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c
  75          * load lock_token and paca_index with a single lwz
  76          * instruction.  They must travel together and be properly
  77          * aligned.
  78          */
  79 #ifdef __BIG_ENDIAN__
  80         u16 lock_token;                 /* Constant 0x8000, used in locks */
  81         u16 paca_index;                 /* Logical processor number */
  82 #else
  83         u16 paca_index;                 /* Logical processor number */
  84         u16 lock_token;                 /* Constant 0x8000, used in locks */
  85 #endif
  86
  87 #ifndef CONFIG_PPC_KERNEL_PCREL
  88         u64 kernel_toc;                 /* Kernel TOC address */
  89 #endif
  90         u64 kernelbase;                 /* Base address of kernel */
  91         u64 kernel_msr;                 /* MSR while running in kernel */
  92         void *emergency_sp;             /* pointer to emergency stack */
  93         u64 data_offset;                /* per cpu data offset */
  94         s16 hw_cpu_id;                  /* Physical processor number */
  95         u8 cpu_start;                   /* At startup, processor spins until */
  96                                         /* this becomes non-zero. */
  97         u8 kexec_state;         /* set when kexec down has irqs off */
  98 #ifdef CONFIG_PPC_BOOK3S_64
  99 #ifdef CONFIG_PPC_64S_HASH_MMU
 100         struct slb_shadow *slb_shadow_ptr;
 101 #endif
 102         struct dtl_entry *dispatch_log;
 103         struct dtl_entry *dispatch_log_end;
 104 #endif
 105         u64 dscr_default;               /* per-CPU default DSCR */
 106
 107 #ifdef CONFIG_PPC_BOOK3S_64
 108         /*
 109          * Now, starting in cacheline 2, the exception save areas
 110          */
 111         /* used for most interrupts/exceptions */
 112         u64 exgen[EX_SIZE] __attribute__((aligned(0x80)));
 113
 114 #ifdef CONFIG_PPC_64S_HASH_MMU
 115         /* SLB related definitions */
 116         u16 vmalloc_sllp;
 117         u8 slb_cache_ptr;
 118         u8 stab_rr;                     /* stab/slb round-robin counter */
 119 #ifdef CONFIG_DEBUG_VM
 120         u8 in_kernel_slb_handler;
 121 #endif
 122         u32 slb_used_bitmap;            /* Bitmaps for first 32 SLB entries. */
 123         u32 slb_kern_bitmap;
 124         u32 slb_cache[SLB_CACHE_ENTRIES];
 125 #endif
 126 #endif /* CONFIG_PPC_BOOK3S_64 */
 127
 128 #ifdef CONFIG_PPC_BOOK3E_64
 129         u64 exgen[8] __aligned(0x40);
 130         /* Keep pgd in the same cacheline as the start of extlb */
 131         pgd_t *pgd __aligned(0x40); /* Current PGD */
 132         pgd_t *kernel_pgd;              /* Kernel PGD */
 133
 134         /* Shared by all threads of a core -- points to tcd of first thread */
 135         struct tlb_core_data *tcd_ptr;
 136
 137         /*
 138          * We can have up to 3 levels of reentrancy in the TLB miss handler,
 139          * in each of four exception levels (normal, crit, mcheck, debug).
 140          */
 141         u64 extlb[12][EX_TLB_SIZE / sizeof(u64)];
 142         u64 exmc[8];            /* used for machine checks */
 143         u64 excrit[8];          /* used for crit interrupts */
 144         u64 exdbg[8];           /* used for debug interrupts */
 145
 146         /* Kernel stack pointers for use by special exceptions */
 147         void *mc_kstack;
 148         void *crit_kstack;
 149         void *dbg_kstack;
 150
 151         struct tlb_core_data tcd;
 152 #endif /* CONFIG_PPC_BOOK3E_64 */
 153
 154 #ifdef CONFIG_PPC_64S_HASH_MMU
 155         unsigned char mm_ctx_low_slices_psize[BITS_PER_LONG / BITS_PER_BYTE];
 156         unsigned char mm_ctx_high_slices_psize[SLICE_ARRAY_SIZE];
 157 #endif
 158
 159         /*
 160          * then miscellaneous read-write fields
 161          */
 162         struct task_struct *__current;  /* Pointer to current */
 163         u64 kstack;                     /* Saved Kernel stack addr */
 164         u64 saved_r1;                   /* r1 save for RTAS calls or PM or EE=0 */
 165         u64 saved_msr;                  /* MSR saved here by enter_rtas */
 166         u64 exit_save_r1;               /* Syscall/interrupt R1 save */
 167 #ifdef CONFIG_PPC_BOOK3E_64
 168         u16 trap_save;                  /* Used when bad stack is encountered */
 169 #endif
 170 #ifdef CONFIG_PPC_BOOK3S_64
 171         u8 hsrr_valid;                  /* HSRRs set for HRFID */
 172         u8 srr_valid;                   /* SRRs set for RFID */
 173 #endif
 174         u8 irq_soft_mask;               /* mask for irq soft masking */
 175         u8 irq_happened;                /* irq happened while soft-disabled */
 176         u8 irq_work_pending;            /* IRQ_WORK interrupt while soft-disable */
 177 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
 178         u8 pmcregs_in_use;              /* pseries puts this in lppaca */
 179 #endif
 180         u64 sprg_vdso;                  /* Saved user-visible sprg */
 181 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 182         u64 tm_scratch;                 /* TM scratch area for reclaim */
 183 #endif
 184
 185 #ifdef CONFIG_PPC_POWERNV
 186         /* PowerNV idle fields */
 187         /* PNV_CORE_IDLE_* bits, all siblings work on thread 0 paca */
 188         unsigned long idle_lock; /* A value of 1 means acquired */
 189         unsigned long idle_state;
 190         union {
 191                 /* P7/P8 specific fields */
 192                 struct {
 193                         /* PNV_THREAD_RUNNING/NAP/SLEEP */
 194                         u8 thread_idle_state;
 195                         /* Mask to denote subcore sibling threads */
 196                         u8 subcore_sibling_mask;
 197                 };
 198
 199                 /* P9 specific fields */
 200                 struct {
 201 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
 202                         /* The PSSCR value that the kernel requested before going to stop */
 203                         u64 requested_psscr;
 204                         /* Flag to request this thread not to stop */
 205                         atomic_t dont_stop;
 206 #endif
 207                 };
 208         };
 209 #endif
 210
 211 #ifdef CONFIG_PPC_BOOK3S_64
 212         /* Non-maskable exceptions that are not performance critical */
 213         u64 exnmi[EX_SIZE];     /* used for system reset (nmi) */
 214         u64 exmc[EX_SIZE];      /* used for machine checks */
 215         /* Exclusive stacks for system reset and machine check exception. */
 216         void *nmi_emergency_sp;
 217         void *mc_emergency_sp;
 218
 219         u16 in_nmi;                     /* In nmi handler */
 220
 221         /*
 222          * Flag to check whether we are in machine check early handler
 223          * and already using emergency stack.
 224          */
 225         u16 in_mce;
 226         u8 hmi_event_available;         /* HMI event is available */
 227         u8 hmi_p9_special_emu;          /* HMI P9 special emulation */
 228         u32 hmi_irqs;                   /* HMI irq stat */
 229 #endif
 230         u8 ftrace_enabled;              /* Hard disable ftrace */
 231
 232         /* Stuff for accurate time accounting */
 233         struct cpu_accounting_data accounting;
 234         u64 dtl_ridx;                   /* read index in dispatch log */
 235         struct dtl_entry *dtl_curr;     /* pointer corresponding to dtl_ridx */
 236
 237 #ifdef CONFIG_KVM_BOOK3S_HANDLER
 238 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
 239         /* We use this to store guest state in */
 240         struct kvmppc_book3s_shadow_vcpu shadow_vcpu;
 241 #endif
 242         struct kvmppc_host_state kvm_hstate;
 243 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
 244         /*
 245          * Bitmap for sibling subcore status. See kvm/book3s_hv_ras.c for
 246          * more details
 247          */
 248         struct sibling_subcore_state *sibling_subcore_state;
 249 #endif
 250 #endif
 251 #ifdef CONFIG_PPC_BOOK3S_64
 252         /*
 253          * rfi fallback flush must be in its own cacheline to prevent
 254          * other paca data leaking into the L1d
 255          */
 256         u64 exrfi[EX_SIZE] __aligned(0x80);
 257         void *rfi_flush_fallback_area;
 258         u64 l1d_flush_size;
 259 #endif
 260 #ifdef CONFIG_PPC_PSERIES
 261         u8 *mce_data_buf;               /* buffer to hold per cpu rtas errlog */
 262 #endif /* CONFIG_PPC_PSERIES */
 263
 264 #ifdef CONFIG_PPC_BOOK3S_64
 265 #ifdef CONFIG_PPC_64S_HASH_MMU
 266         /* Capture SLB related old contents in MCE handler. */
 267         struct slb_entry *mce_faulty_slbs;
 268         u16 slb_save_cache_ptr;
 269 #endif
 270 #endif /* CONFIG_PPC_BOOK3S_64 */
 271 #ifdef CONFIG_STACKPROTECTOR
 272         unsigned long canary;
 273 #endif
 274 #ifdef CONFIG_MMIOWB
 275         struct mmiowb_state mmiowb_state;
 276 #endif
 277 #ifdef CONFIG_PPC_BOOK3S_64
 278         struct mce_info *mce_info;
 279         u8 mce_pending_irq_work;
 280 #endif /* CONFIG_PPC_BOOK3S_64 */
 281 } ____cacheline_aligned;
 282
 283 extern void copy_mm_to_paca(struct mm_struct *mm);
 284 extern struct paca_struct **paca_ptrs;
 285 extern void initialise_paca(struct paca_struct *new_paca, int cpu);
 286 extern void setup_paca(struct paca_struct *new_paca);
 287 extern void allocate_paca_ptrs(void);
 288 extern void allocate_paca(int cpu);
 289 extern void free_unused_pacas(void);
 290
 291 #else /* CONFIG_PPC64 */
 292
 293 static inline void allocate_paca(int cpu) { }
 294 static inline void free_unused_pacas(void) { }
 295
 296 #endif /* CONFIG_PPC64 */
 297
 298 #endif /* __KERNEL__ */
 299 #endif /* _ASM_POWERPC_PACA_H */