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printf: Remove unused 'bprintf'
[drm/drm-misc.git] / drivers / clk / clk-si5341.c
blob5004888c7eca5f85a444ec6de684b8dd79635622
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Silicon Labs Si5340, Si5341, Si5342, Si5344 and Si5345
4 * Copyright (C) 2019 Topic Embedded Products
5 * Author: Mike Looijmans <mike.looijmans@topic.nl>
6 *
7 * The Si5341 has 10 outputs and 5 synthesizers.
8 * The Si5340 is a smaller version of the Si5341 with only 4 outputs.
9 * The Si5345 is similar to the Si5341, with the addition of fractional input
10 * dividers and automatic input selection.
11 * The Si5342 and Si5344 are smaller versions of the Si5345.
12 */
13
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
16 #include <linux/delay.h>
17 #include <linux/gcd.h>
18 #include <linux/math64.h>
19 #include <linux/i2c.h>
20 #include <linux/module.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <linux/unaligned.h>
25
26 #define SI5341_NUM_INPUTS 4
27
28 #define SI5340_MAX_NUM_OUTPUTS 4
29 #define SI5341_MAX_NUM_OUTPUTS 10
30 #define SI5342_MAX_NUM_OUTPUTS 2
31 #define SI5344_MAX_NUM_OUTPUTS 4
32 #define SI5345_MAX_NUM_OUTPUTS 10
33
34 #define SI5340_NUM_SYNTH 4
35 #define SI5341_NUM_SYNTH 5
36 #define SI5342_NUM_SYNTH 2
37 #define SI5344_NUM_SYNTH 4
38 #define SI5345_NUM_SYNTH 5
39
40 /* Range of the synthesizer fractional divider */
41 #define SI5341_SYNTH_N_MIN 10
42 #define SI5341_SYNTH_N_MAX 4095
43
44 /* The chip can get its input clock from 3 input pins or an XTAL */
45
46 /* There is one PLL running at 13500–14256 MHz */
47 #define SI5341_PLL_VCO_MIN 13500000000ull
48 #define SI5341_PLL_VCO_MAX 14256000000ull
49
50 /* The 5 frequency synthesizers obtain their input from the PLL */
51 struct clk_si5341_synth {
52 struct clk_hw hw;
53 struct clk_si5341 *data;
54 u8 index;
55 };
56 #define to_clk_si5341_synth(_hw) \
57 container_of(_hw, struct clk_si5341_synth, hw)
58
59 /* The output stages can be connected to any synth (full mux) */
60 struct clk_si5341_output {
61 struct clk_hw hw;
62 struct clk_si5341 *data;
63 struct regulator *vddo_reg;
64 u8 index;
65 };
66 #define to_clk_si5341_output(_hw) \
67 container_of(_hw, struct clk_si5341_output, hw)
68
69 struct clk_si5341 {
70 struct clk_hw hw;
71 struct regmap *regmap;
72 struct i2c_client *i2c_client;
73 struct clk_si5341_synth synth[SI5341_NUM_SYNTH];
74 struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS];
75 struct clk *input_clk[SI5341_NUM_INPUTS];
76 const char *input_clk_name[SI5341_NUM_INPUTS];
77 const u16 *reg_output_offset;
78 const u16 *reg_rdiv_offset;
79 u64 freq_vco; /* 13500–14256 MHz */
80 u8 num_outputs;
81 u8 num_synth;
82 u16 chip_id;
83 bool xaxb_ext_clk;
84 bool iovdd_33;
85 };
86 #define to_clk_si5341(_hw) container_of(_hw, struct clk_si5341, hw)
87
88 struct clk_si5341_output_config {
89 u8 out_format_drv_bits;
90 u8 out_cm_ampl_bits;
91 u8 vdd_sel_bits;
92 bool synth_master;
93 bool always_on;
94 };
95
96 #define SI5341_PAGE 0x0001
97 #define SI5341_PN_BASE 0x0002
98 #define SI5341_DEVICE_REV 0x0005
99 #define SI5341_STATUS 0x000C
100 #define SI5341_LOS 0x000D
101 #define SI5341_STATUS_STICKY 0x0011
102 #define SI5341_LOS_STICKY 0x0012
103 #define SI5341_SOFT_RST 0x001C
104 #define SI5341_IN_SEL 0x0021
105 #define SI5341_DEVICE_READY 0x00FE
106 #define SI5341_XAXB_CFG 0x090E
107 #define SI5341_IO_VDD_SEL 0x0943
108 #define SI5341_IN_EN 0x0949
109 #define SI5341_INX_TO_PFD_EN 0x094A
110
111 /* Status bits */
112 #define SI5341_STATUS_SYSINCAL BIT(0)
113 #define SI5341_STATUS_LOSXAXB BIT(1)
114 #define SI5341_STATUS_LOSREF BIT(2)
115 #define SI5341_STATUS_LOL BIT(3)
116
117 /* Input selection */
118 #define SI5341_IN_SEL_MASK 0x06
119 #define SI5341_IN_SEL_SHIFT 1
120 #define SI5341_IN_SEL_REGCTRL 0x01
121 #define SI5341_INX_TO_PFD_SHIFT 4
122
123 /* XTAL config bits */
124 #define SI5341_XAXB_CFG_EXTCLK_EN BIT(0)
125 #define SI5341_XAXB_CFG_PDNB BIT(1)
126
127 /* Input dividers (48-bit) */
128 #define SI5341_IN_PDIV(x) (0x0208 + ((x) * 10))
129 #define SI5341_IN_PSET(x) (0x020E + ((x) * 10))
130 #define SI5341_PX_UPD 0x0230
131
132 /* PLL configuration */
133 #define SI5341_PLL_M_NUM 0x0235
134 #define SI5341_PLL_M_DEN 0x023B
135
136 /* Output configuration */
137 #define SI5341_OUT_CONFIG(output) \
138 ((output)->data->reg_output_offset[(output)->index])
139 #define SI5341_OUT_FORMAT(output) (SI5341_OUT_CONFIG(output) + 1)
140 #define SI5341_OUT_CM(output) (SI5341_OUT_CONFIG(output) + 2)
141 #define SI5341_OUT_MUX_SEL(output) (SI5341_OUT_CONFIG(output) + 3)
142 #define SI5341_OUT_R_REG(output) \
143 ((output)->data->reg_rdiv_offset[(output)->index])
144
145 #define SI5341_OUT_MUX_VDD_SEL_MASK 0x38
146
147 /* Synthesize N divider */
148 #define SI5341_SYNTH_N_NUM(x) (0x0302 + ((x) * 11))
149 #define SI5341_SYNTH_N_DEN(x) (0x0308 + ((x) * 11))
150 #define SI5341_SYNTH_N_UPD(x) (0x030C + ((x) * 11))
151
152 /* Synthesizer output enable, phase bypass, power mode */
153 #define SI5341_SYNTH_N_CLK_TO_OUTX_EN 0x0A03
154 #define SI5341_SYNTH_N_PIBYP 0x0A04
155 #define SI5341_SYNTH_N_PDNB 0x0A05
156 #define SI5341_SYNTH_N_CLK_DIS 0x0B4A
157
158 #define SI5341_REGISTER_MAX 0xBFF
159
160 /* SI5341_OUT_CONFIG bits */
161 #define SI5341_OUT_CFG_PDN BIT(0)
162 #define SI5341_OUT_CFG_OE BIT(1)
163 #define SI5341_OUT_CFG_RDIV_FORCE2 BIT(2)
164
165 /* Static configuration (to be moved to firmware) */
166 struct si5341_reg_default {
167 u16 address;
168 u8 value;
169 };
170
171 static const char * const si5341_input_clock_names[] = {
172 "in0", "in1", "in2", "xtal"
173 };
174
175 /* Output configuration registers 0..9 are not quite logically organized */
176 /* Also for si5345 */
177 static const u16 si5341_reg_output_offset[] = {
178 0x0108,
179 0x010D,
180 0x0112,
181 0x0117,
182 0x011C,
183 0x0121,
184 0x0126,
185 0x012B,
186 0x0130,
187 0x013A,
188 };
189
190 /* for si5340, si5342 and si5344 */
191 static const u16 si5340_reg_output_offset[] = {
192 0x0112,
193 0x0117,
194 0x0126,
195 0x012B,
196 };
197
198 /* The location of the R divider registers */
199 static const u16 si5341_reg_rdiv_offset[] = {
200 0x024A,
201 0x024D,
202 0x0250,
203 0x0253,
204 0x0256,
205 0x0259,
206 0x025C,
207 0x025F,
208 0x0262,
209 0x0268,
210 };
211 static const u16 si5340_reg_rdiv_offset[] = {
212 0x0250,
213 0x0253,
214 0x025C,
215 0x025F,
216 };
217
218 /*
219 * Programming sequence from ClockBuilder, settings to initialize the system
220 * using only the XTAL input, without pre-divider.
221 * This also contains settings that aren't mentioned anywhere in the datasheet.
222 * The "known" settings like synth and output configuration are done later.
223 */
224 static const struct si5341_reg_default si5341_reg_defaults[] = {
225 { 0x0017, 0x3A }, /* INT mask (disable interrupts) */
226 { 0x0018, 0xFF }, /* INT mask */
227 { 0x0021, 0x0F }, /* Select XTAL as input */
228 { 0x0022, 0x00 }, /* Not in datasheet */
229 { 0x002B, 0x02 }, /* SPI config */
230 { 0x002C, 0x20 }, /* LOS enable for XTAL */
231 { 0x002D, 0x00 }, /* LOS timing */
232 { 0x002E, 0x00 },
233 { 0x002F, 0x00 },
234 { 0x0030, 0x00 },
235 { 0x0031, 0x00 },
236 { 0x0032, 0x00 },
237 { 0x0033, 0x00 },
238 { 0x0034, 0x00 },
239 { 0x0035, 0x00 },
240 { 0x0036, 0x00 },
241 { 0x0037, 0x00 },
242 { 0x0038, 0x00 }, /* LOS setting (thresholds) */
243 { 0x0039, 0x00 },
244 { 0x003A, 0x00 },
245 { 0x003B, 0x00 },
246 { 0x003C, 0x00 },
247 { 0x003D, 0x00 }, /* LOS setting (thresholds) end */
248 { 0x0041, 0x00 }, /* LOS0_DIV_SEL */
249 { 0x0042, 0x00 }, /* LOS1_DIV_SEL */
250 { 0x0043, 0x00 }, /* LOS2_DIV_SEL */
251 { 0x0044, 0x00 }, /* LOS3_DIV_SEL */
252 { 0x009E, 0x00 }, /* Not in datasheet */
253 { 0x0102, 0x01 }, /* Enable outputs */
254 { 0x013F, 0x00 }, /* Not in datasheet */
255 { 0x0140, 0x00 }, /* Not in datasheet */
256 { 0x0141, 0x40 }, /* OUT LOS */
257 { 0x0202, 0x00 }, /* XAXB_FREQ_OFFSET (=0)*/
258 { 0x0203, 0x00 },
259 { 0x0204, 0x00 },
260 { 0x0205, 0x00 },
261 { 0x0206, 0x00 }, /* PXAXB (2^x) */
262 { 0x0208, 0x00 }, /* Px divider setting (usually 0) */
263 { 0x0209, 0x00 },
264 { 0x020A, 0x00 },
265 { 0x020B, 0x00 },
266 { 0x020C, 0x00 },
267 { 0x020D, 0x00 },
268 { 0x020E, 0x00 },
269 { 0x020F, 0x00 },
270 { 0x0210, 0x00 },
271 { 0x0211, 0x00 },
272 { 0x0212, 0x00 },
273 { 0x0213, 0x00 },
274 { 0x0214, 0x00 },
275 { 0x0215, 0x00 },
276 { 0x0216, 0x00 },
277 { 0x0217, 0x00 },
278 { 0x0218, 0x00 },
279 { 0x0219, 0x00 },
280 { 0x021A, 0x00 },
281 { 0x021B, 0x00 },
282 { 0x021C, 0x00 },
283 { 0x021D, 0x00 },
284 { 0x021E, 0x00 },
285 { 0x021F, 0x00 },
286 { 0x0220, 0x00 },
287 { 0x0221, 0x00 },
288 { 0x0222, 0x00 },
289 { 0x0223, 0x00 },
290 { 0x0224, 0x00 },
291 { 0x0225, 0x00 },
292 { 0x0226, 0x00 },
293 { 0x0227, 0x00 },
294 { 0x0228, 0x00 },
295 { 0x0229, 0x00 },
296 { 0x022A, 0x00 },
297 { 0x022B, 0x00 },
298 { 0x022C, 0x00 },
299 { 0x022D, 0x00 },
300 { 0x022E, 0x00 },
301 { 0x022F, 0x00 }, /* Px divider setting (usually 0) end */
302 { 0x026B, 0x00 }, /* DESIGN_ID (ASCII string) */
303 { 0x026C, 0x00 },
304 { 0x026D, 0x00 },
305 { 0x026E, 0x00 },
306 { 0x026F, 0x00 },
307 { 0x0270, 0x00 },
308 { 0x0271, 0x00 },
309 { 0x0272, 0x00 }, /* DESIGN_ID (ASCII string) end */
310 { 0x0339, 0x1F }, /* N_FSTEP_MSK */
311 { 0x033B, 0x00 }, /* Nx_FSTEPW (Frequency step) */
312 { 0x033C, 0x00 },
313 { 0x033D, 0x00 },
314 { 0x033E, 0x00 },
315 { 0x033F, 0x00 },
316 { 0x0340, 0x00 },
317 { 0x0341, 0x00 },
318 { 0x0342, 0x00 },
319 { 0x0343, 0x00 },
320 { 0x0344, 0x00 },
321 { 0x0345, 0x00 },
322 { 0x0346, 0x00 },
323 { 0x0347, 0x00 },
324 { 0x0348, 0x00 },
325 { 0x0349, 0x00 },
326 { 0x034A, 0x00 },
327 { 0x034B, 0x00 },
328 { 0x034C, 0x00 },
329 { 0x034D, 0x00 },
330 { 0x034E, 0x00 },
331 { 0x034F, 0x00 },
332 { 0x0350, 0x00 },
333 { 0x0351, 0x00 },
334 { 0x0352, 0x00 },
335 { 0x0353, 0x00 },
336 { 0x0354, 0x00 },
337 { 0x0355, 0x00 },
338 { 0x0356, 0x00 },
339 { 0x0357, 0x00 },
340 { 0x0358, 0x00 }, /* Nx_FSTEPW (Frequency step) end */
341 { 0x0359, 0x00 }, /* Nx_DELAY */
342 { 0x035A, 0x00 },
343 { 0x035B, 0x00 },
344 { 0x035C, 0x00 },
345 { 0x035D, 0x00 },
346 { 0x035E, 0x00 },
347 { 0x035F, 0x00 },
348 { 0x0360, 0x00 },
349 { 0x0361, 0x00 },
350 { 0x0362, 0x00 }, /* Nx_DELAY end */
351 { 0x0802, 0x00 }, /* Not in datasheet */
352 { 0x0803, 0x00 }, /* Not in datasheet */
353 { 0x0804, 0x00 }, /* Not in datasheet */
354 { 0x090E, 0x02 }, /* XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL) */
355 { 0x091C, 0x04 }, /* ZDM_EN=4 (Normal mode) */
356 { 0x0949, 0x00 }, /* IN_EN (disable input clocks) */
357 { 0x094A, 0x00 }, /* INx_TO_PFD_EN (disabled) */
358 { 0x0A02, 0x00 }, /* Not in datasheet */
359 { 0x0B44, 0x0F }, /* PDIV_ENB (datasheet does not mention what it is) */
360 { 0x0B57, 0x10 }, /* VCO_RESET_CALCODE (not described in datasheet) */
361 { 0x0B58, 0x05 }, /* VCO_RESET_CALCODE (not described in datasheet) */
362 };
363
364 /* Read and interpret a 44-bit followed by a 32-bit value in the regmap */
365 static int si5341_decode_44_32(struct regmap *regmap, unsigned int reg,
366 u64 *val1, u32 *val2)
367 {
368 int err;
369 u8 r[10];
370
371 err = regmap_bulk_read(regmap, reg, r, 10);
372 if (err < 0)
373 return err;
374
375 *val1 = ((u64)((r[5] & 0x0f) << 8 | r[4]) << 32) |
376 (get_unaligned_le32(r));
377 *val2 = get_unaligned_le32(&r[6]);
378
379 return 0;
380 }
381
382 static int si5341_encode_44_32(struct regmap *regmap, unsigned int reg,
383 u64 n_num, u32 n_den)
384 {
385 u8 r[10];
386
387 /* Shift left as far as possible without overflowing */
388 while (!(n_num & BIT_ULL(43)) && !(n_den & BIT(31))) {
389 n_num <<= 1;
390 n_den <<= 1;
391 }
392
393 /* 44 bits (6 bytes) numerator */
394 put_unaligned_le32(n_num, r);
395 r[4] = (n_num >> 32) & 0xff;
396 r[5] = (n_num >> 40) & 0x0f;
397 /* 32 bits denominator */
398 put_unaligned_le32(n_den, &r[6]);
399
400 /* Program the fraction */
401 return regmap_bulk_write(regmap, reg, r, sizeof(r));
402 }
403
404 /* VCO, we assume it runs at a constant frequency */
405 static unsigned long si5341_clk_recalc_rate(struct clk_hw *hw,
406 unsigned long parent_rate)
407 {
408 struct clk_si5341 *data = to_clk_si5341(hw);
409 int err;
410 u64 res;
411 u64 m_num;
412 u32 m_den;
413 unsigned int shift;
414
415 /* Assume that PDIV is not being used, just read the PLL setting */
416 err = si5341_decode_44_32(data->regmap, SI5341_PLL_M_NUM,
417 &m_num, &m_den);
418 if (err < 0)
419 return 0;
420
421 if (!m_num || !m_den)
422 return 0;
423
424 /*
425 * Though m_num is 64-bit, only the upper bits are actually used. While
426 * calculating m_num and m_den, they are shifted as far as possible to
427 * the left. To avoid 96-bit division here, we just shift them back so
428 * we can do with just 64 bits.
429 */
430 shift = 0;
431 res = m_num;
432 while (res & 0xffff00000000ULL) {
433 ++shift;
434 res >>= 1;
435 }
436 res *= parent_rate;
437 do_div(res, (m_den >> shift));
438
439 /* We cannot return the actual frequency in 32 bit, store it locally */
440 data->freq_vco = res;
441
442 /* Report kHz since the value is out of range */
443 do_div(res, 1000);
444
445 return (unsigned long)res;
446 }
447
448 static int si5341_clk_get_selected_input(struct clk_si5341 *data)
449 {
450 int err;
451 u32 val;
452
453 err = regmap_read(data->regmap, SI5341_IN_SEL, &val);
454 if (err < 0)
455 return err;
456
457 return (val & SI5341_IN_SEL_MASK) >> SI5341_IN_SEL_SHIFT;
458 }
459
460 static u8 si5341_clk_get_parent(struct clk_hw *hw)
461 {
462 struct clk_si5341 *data = to_clk_si5341(hw);
463 int res = si5341_clk_get_selected_input(data);
464
465 if (res < 0)
466 return 0; /* Apparently we cannot report errors */
467
468 return res;
469 }
470
471 static int si5341_clk_reparent(struct clk_si5341 *data, u8 index)
472 {
473 int err;
474 u8 val;
475
476 val = (index << SI5341_IN_SEL_SHIFT) & SI5341_IN_SEL_MASK;
477 /* Enable register-based input selection */
478 val |= SI5341_IN_SEL_REGCTRL;
479
480 err = regmap_update_bits(data->regmap,
481 SI5341_IN_SEL, SI5341_IN_SEL_REGCTRL | SI5341_IN_SEL_MASK, val);
482 if (err < 0)
483 return err;
484
485 if (index < 3) {
486 /* Enable input buffer for selected input */
487 err = regmap_update_bits(data->regmap,
488 SI5341_IN_EN, 0x07, BIT(index));
489 if (err < 0)
490 return err;
491
492 /* Enables the input to phase detector */
493 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
494 0x7 << SI5341_INX_TO_PFD_SHIFT,
495 BIT(index + SI5341_INX_TO_PFD_SHIFT));
496 if (err < 0)
497 return err;
498
499 /* Power down XTAL oscillator and buffer */
500 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
501 SI5341_XAXB_CFG_PDNB, 0);
502 if (err < 0)
503 return err;
504
505 /*
506 * Set the P divider to "1". There's no explanation in the
507 * datasheet of these registers, but the clockbuilder software
508 * programs a "1" when the input is being used.
509 */
510 err = regmap_write(data->regmap, SI5341_IN_PDIV(index), 1);
511 if (err < 0)
512 return err;
513
514 err = regmap_write(data->regmap, SI5341_IN_PSET(index), 1);
515 if (err < 0)
516 return err;
517
518 /* Set update PDIV bit */
519 err = regmap_write(data->regmap, SI5341_PX_UPD, BIT(index));
520 if (err < 0)
521 return err;
522 } else {
523 /* Disable all input buffers */
524 err = regmap_update_bits(data->regmap, SI5341_IN_EN, 0x07, 0);
525 if (err < 0)
526 return err;
527
528 /* Disable input to phase detector */
529 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
530 0x7 << SI5341_INX_TO_PFD_SHIFT, 0);
531 if (err < 0)
532 return err;
533
534 /* Power up XTAL oscillator and buffer, select clock mode */
535 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
536 SI5341_XAXB_CFG_PDNB | SI5341_XAXB_CFG_EXTCLK_EN,
537 SI5341_XAXB_CFG_PDNB | (data->xaxb_ext_clk ?
538 SI5341_XAXB_CFG_EXTCLK_EN : 0));
539 if (err < 0)
540 return err;
541 }
542
543 return 0;
544 }
545
546 static int si5341_clk_set_parent(struct clk_hw *hw, u8 index)
547 {
548 struct clk_si5341 *data = to_clk_si5341(hw);
549
550 return si5341_clk_reparent(data, index);
551 }
552
553 static const struct clk_ops si5341_clk_ops = {
554 .determine_rate = clk_hw_determine_rate_no_reparent,
555 .set_parent = si5341_clk_set_parent,
556 .get_parent = si5341_clk_get_parent,
557 .recalc_rate = si5341_clk_recalc_rate,
558 };
559
560 /* Synthesizers, there are 5 synthesizers that connect to any of the outputs */
561
562 /* The synthesizer is on if all power and enable bits are set */
563 static int si5341_synth_clk_is_on(struct clk_hw *hw)
564 {
565 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
566 int err;
567 u32 val;
568 u8 index = synth->index;
569
570 err = regmap_read(synth->data->regmap,
571 SI5341_SYNTH_N_CLK_TO_OUTX_EN, &val);
572 if (err < 0)
573 return 0;
574
575 if (!(val & BIT(index)))
576 return 0;
577
578 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val);
579 if (err < 0)
580 return 0;
581
582 if (!(val & BIT(index)))
583 return 0;
584
585 /* This bit must be 0 for the synthesizer to receive clock input */
586 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val);
587 if (err < 0)
588 return 0;
589
590 return !(val & BIT(index));
591 }
592
593 static void si5341_synth_clk_unprepare(struct clk_hw *hw)
594 {
595 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
596 u8 index = synth->index; /* In range 0..5 */
597 u8 mask = BIT(index);
598
599 /* Disable output */
600 regmap_update_bits(synth->data->regmap,
601 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, 0);
602 /* Power down */
603 regmap_update_bits(synth->data->regmap,
604 SI5341_SYNTH_N_PDNB, mask, 0);
605 /* Disable clock input to synth (set to 1 to disable) */
606 regmap_update_bits(synth->data->regmap,
607 SI5341_SYNTH_N_CLK_DIS, mask, mask);
608 }
609
610 static int si5341_synth_clk_prepare(struct clk_hw *hw)
611 {
612 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
613 int err;
614 u8 index = synth->index;
615 u8 mask = BIT(index);
616
617 /* Power up */
618 err = regmap_update_bits(synth->data->regmap,
619 SI5341_SYNTH_N_PDNB, mask, mask);
620 if (err < 0)
621 return err;
622
623 /* Enable clock input to synth (set bit to 0 to enable) */
624 err = regmap_update_bits(synth->data->regmap,
625 SI5341_SYNTH_N_CLK_DIS, mask, 0);
626 if (err < 0)
627 return err;
628
629 /* Enable output */
630 return regmap_update_bits(synth->data->regmap,
631 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, mask);
632 }
633
634 /* Synth clock frequency: Fvco * n_den / n_den, with Fvco in 13500-14256 MHz */
635 static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw,
636 unsigned long parent_rate)
637 {
638 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
639 u64 f;
640 u64 n_num;
641 u32 n_den;
642 int err;
643
644 err = si5341_decode_44_32(synth->data->regmap,
645 SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den);
646 if (err < 0)
647 return err;
648 /* Check for bogus/uninitialized settings */
649 if (!n_num || !n_den)
650 return 0;
651
652 /*
653 * n_num and n_den are shifted left as much as possible, so to prevent
654 * overflow in 64-bit math, we shift n_den 4 bits to the right
655 */
656 f = synth->data->freq_vco;
657 f *= n_den >> 4;
658
659 /* Now we need to do 64-bit division: f/n_num */
660 /* And compensate for the 4 bits we dropped */
661 f = div64_u64(f, (n_num >> 4));
662
663 return f;
664 }
665
666 static long si5341_synth_clk_round_rate(struct clk_hw *hw, unsigned long rate,
667 unsigned long *parent_rate)
668 {
669 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
670 u64 f;
671
672 /* The synthesizer accuracy is such that anything in range will work */
673 f = synth->data->freq_vco;
674 do_div(f, SI5341_SYNTH_N_MAX);
675 if (rate < f)
676 return f;
677
678 f = synth->data->freq_vco;
679 do_div(f, SI5341_SYNTH_N_MIN);
680 if (rate > f)
681 return f;
682
683 return rate;
684 }
685
686 static int si5341_synth_program(struct clk_si5341_synth *synth,
687 u64 n_num, u32 n_den, bool is_integer)
688 {
689 int err;
690 u8 index = synth->index;
691
692 err = si5341_encode_44_32(synth->data->regmap,
693 SI5341_SYNTH_N_NUM(index), n_num, n_den);
694
695 err = regmap_update_bits(synth->data->regmap,
696 SI5341_SYNTH_N_PIBYP, BIT(index), is_integer ? BIT(index) : 0);
697 if (err < 0)
698 return err;
699
700 return regmap_write(synth->data->regmap,
701 SI5341_SYNTH_N_UPD(index), 0x01);
702 }
703
704
705 static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate,
706 unsigned long parent_rate)
707 {
708 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
709 u64 n_num;
710 u32 n_den;
711 u32 r;
712 u32 g;
713 bool is_integer;
714
715 n_num = synth->data->freq_vco;
716
717 /* see if there's an integer solution */
718 r = do_div(n_num, rate);
719 is_integer = (r == 0);
720 if (is_integer) {
721 /* Integer divider equal to n_num */
722 n_den = 1;
723 } else {
724 /* Calculate a fractional solution */
725 g = gcd(r, rate);
726 n_den = rate / g;
727 n_num *= n_den;
728 n_num += r / g;
729 }
730
731 dev_dbg(&synth->data->i2c_client->dev,
732 "%s(%u): n=0x%llx d=0x%x %s\n", __func__,
733 synth->index, n_num, n_den,
734 is_integer ? "int" : "frac");
735
736 return si5341_synth_program(synth, n_num, n_den, is_integer);
737 }
738
739 static const struct clk_ops si5341_synth_clk_ops = {
740 .is_prepared = si5341_synth_clk_is_on,
741 .prepare = si5341_synth_clk_prepare,
742 .unprepare = si5341_synth_clk_unprepare,
743 .recalc_rate = si5341_synth_clk_recalc_rate,
744 .round_rate = si5341_synth_clk_round_rate,
745 .set_rate = si5341_synth_clk_set_rate,
746 };
747
748 static int si5341_output_clk_is_on(struct clk_hw *hw)
749 {
750 struct clk_si5341_output *output = to_clk_si5341_output(hw);
751 int err;
752 u32 val;
753
754 err = regmap_read(output->data->regmap,
755 SI5341_OUT_CONFIG(output), &val);
756 if (err < 0)
757 return err;
758
759 /* Bit 0=PDN, 1=OE so only a value of 0x2 enables the output */
760 return (val & 0x03) == SI5341_OUT_CFG_OE;
761 }
762
763 /* Disables and then powers down the output */
764 static void si5341_output_clk_unprepare(struct clk_hw *hw)
765 {
766 struct clk_si5341_output *output = to_clk_si5341_output(hw);
767
768 regmap_update_bits(output->data->regmap,
769 SI5341_OUT_CONFIG(output),
770 SI5341_OUT_CFG_OE, 0);
771 regmap_update_bits(output->data->regmap,
772 SI5341_OUT_CONFIG(output),
773 SI5341_OUT_CFG_PDN, SI5341_OUT_CFG_PDN);
774 }
775
776 /* Powers up and then enables the output */
777 static int si5341_output_clk_prepare(struct clk_hw *hw)
778 {
779 struct clk_si5341_output *output = to_clk_si5341_output(hw);
780 int err;
781
782 err = regmap_update_bits(output->data->regmap,
783 SI5341_OUT_CONFIG(output),
784 SI5341_OUT_CFG_PDN, 0);
785 if (err < 0)
786 return err;
787
788 return regmap_update_bits(output->data->regmap,
789 SI5341_OUT_CONFIG(output),
790 SI5341_OUT_CFG_OE, SI5341_OUT_CFG_OE);
791 }
792
793 static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw,
794 unsigned long parent_rate)
795 {
796 struct clk_si5341_output *output = to_clk_si5341_output(hw);
797 int err;
798 u32 val;
799 u32 r_divider;
800 u8 r[3];
801
802 err = regmap_read(output->data->regmap,
803 SI5341_OUT_CONFIG(output), &val);
804 if (err < 0)
805 return err;
806
807 /* If SI5341_OUT_CFG_RDIV_FORCE2 is set, r_divider is 2 */
808 if (val & SI5341_OUT_CFG_RDIV_FORCE2)
809 return parent_rate / 2;
810
811 err = regmap_bulk_read(output->data->regmap,
812 SI5341_OUT_R_REG(output), r, 3);
813 if (err < 0)
814 return err;
815
816 /* Calculate value as 24-bit integer*/
817 r_divider = r[2] << 16 | r[1] << 8 | r[0];
818
819 /* If Rx_REG is zero, the divider is disabled, so return a "0" rate */
820 if (!r_divider)
821 return 0;
822
823 /* Divider is 2*(Rx_REG+1) */
824 r_divider += 1;
825 r_divider <<= 1;
826
827
828 return parent_rate / r_divider;
829 }
830
831 static int si5341_output_clk_determine_rate(struct clk_hw *hw,
832 struct clk_rate_request *req)
833 {
834 unsigned long rate = req->rate;
835 unsigned long r;
836
837 if (!rate)
838 return 0;
839
840 r = req->best_parent_rate >> 1;
841
842 /* If rate is an even divisor, no changes to parent required */
843 if (r && !(r % rate))
844 return 0;
845
846 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
847 if (rate > 200000000) {
848 /* minimum r-divider is 2 */
849 r = 2;
850 } else {
851 /* Take a parent frequency near 400 MHz */
852 r = (400000000u / rate) & ~1;
853 }
854 req->best_parent_rate = r * rate;
855 } else {
856 /* We cannot change our parent's rate, report what we can do */
857 r /= rate;
858 rate = req->best_parent_rate / (r << 1);
859 }
860
861 req->rate = rate;
862 return 0;
863 }
864
865 static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate,
866 unsigned long parent_rate)
867 {
868 struct clk_si5341_output *output = to_clk_si5341_output(hw);
869 u32 r_div;
870 int err;
871 u8 r[3];
872
873 if (!rate)
874 return -EINVAL;
875
876 /* Frequency divider is (r_div + 1) * 2 */
877 r_div = (parent_rate / rate) >> 1;
878
879 if (r_div <= 1)
880 r_div = 0;
881 else if (r_div >= BIT(24))
882 r_div = BIT(24) - 1;
883 else
884 --r_div;
885
886 /* For a value of "2", we set the "OUT0_RDIV_FORCE2" bit */
887 err = regmap_update_bits(output->data->regmap,
888 SI5341_OUT_CONFIG(output),
889 SI5341_OUT_CFG_RDIV_FORCE2,
890 (r_div == 0) ? SI5341_OUT_CFG_RDIV_FORCE2 : 0);
891 if (err < 0)
892 return err;
893
894 /* Always write Rx_REG, because a zero value disables the divider */
895 r[0] = r_div ? (r_div & 0xff) : 1;
896 r[1] = (r_div >> 8) & 0xff;
897 r[2] = (r_div >> 16) & 0xff;
898 return regmap_bulk_write(output->data->regmap,
899 SI5341_OUT_R_REG(output), r, 3);
900 }
901
902 static int si5341_output_reparent(struct clk_si5341_output *output, u8 index)
903 {
904 return regmap_update_bits(output->data->regmap,
905 SI5341_OUT_MUX_SEL(output), 0x07, index);
906 }
907
908 static int si5341_output_set_parent(struct clk_hw *hw, u8 index)
909 {
910 struct clk_si5341_output *output = to_clk_si5341_output(hw);
911
912 if (index >= output->data->num_synth)
913 return -EINVAL;
914
915 return si5341_output_reparent(output, index);
916 }
917
918 static u8 si5341_output_get_parent(struct clk_hw *hw)
919 {
920 struct clk_si5341_output *output = to_clk_si5341_output(hw);
921 u32 val;
922
923 regmap_read(output->data->regmap, SI5341_OUT_MUX_SEL(output), &val);
924
925 return val & 0x7;
926 }
927
928 static const struct clk_ops si5341_output_clk_ops = {
929 .is_prepared = si5341_output_clk_is_on,
930 .prepare = si5341_output_clk_prepare,
931 .unprepare = si5341_output_clk_unprepare,
932 .recalc_rate = si5341_output_clk_recalc_rate,
933 .determine_rate = si5341_output_clk_determine_rate,
934 .set_rate = si5341_output_clk_set_rate,
935 .set_parent = si5341_output_set_parent,
936 .get_parent = si5341_output_get_parent,
937 };
938
939 /*
940 * The chip can be bought in a pre-programmed version, or one can program the
941 * NVM in the chip to boot up in a preset mode. This routine tries to determine
942 * if that's the case, or if we need to reset and program everything from
943 * scratch. Returns negative error, or true/false.
944 */
945 static int si5341_is_programmed_already(struct clk_si5341 *data)
946 {
947 int err;
948 u8 r[4];
949
950 /* Read the PLL divider value, it must have a non-zero value */
951 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_DEN,
952 r, ARRAY_SIZE(r));
953 if (err < 0)
954 return err;
955
956 return !!get_unaligned_le32(r);
957 }
958
959 static struct clk_hw *
960 of_clk_si5341_get(struct of_phandle_args *clkspec, void *_data)
961 {
962 struct clk_si5341 *data = _data;
963 unsigned int idx = clkspec->args[1];
964 unsigned int group = clkspec->args[0];
965
966 switch (group) {
967 case 0:
968 if (idx >= data->num_outputs) {
969 dev_err(&data->i2c_client->dev,
970 "invalid output index %u\n", idx);
971 return ERR_PTR(-EINVAL);
972 }
973 return &data->clk[idx].hw;
974 case 1:
975 if (idx >= data->num_synth) {
976 dev_err(&data->i2c_client->dev,
977 "invalid synthesizer index %u\n", idx);
978 return ERR_PTR(-EINVAL);
979 }
980 return &data->synth[idx].hw;
981 case 2:
982 if (idx > 0) {
983 dev_err(&data->i2c_client->dev,
984 "invalid PLL index %u\n", idx);
985 return ERR_PTR(-EINVAL);
986 }
987 return &data->hw;
988 default:
989 dev_err(&data->i2c_client->dev, "invalid group %u\n", group);
990 return ERR_PTR(-EINVAL);
991 }
992 }
993
994 static int si5341_probe_chip_id(struct clk_si5341 *data)
995 {
996 int err;
997 u8 reg[4];
998 u16 model;
999
1000 err = regmap_bulk_read(data->regmap, SI5341_PN_BASE, reg,
1001 ARRAY_SIZE(reg));
1002 if (err < 0) {
1003 dev_err(&data->i2c_client->dev, "Failed to read chip ID\n");
1004 return err;
1005 }
1006
1007 model = get_unaligned_le16(reg);
1008
1009 dev_info(&data->i2c_client->dev, "Chip: %x Grade: %u Rev: %u\n",
1010 model, reg[2], reg[3]);
1011
1012 switch (model) {
1013 case 0x5340:
1014 data->num_outputs = SI5340_MAX_NUM_OUTPUTS;
1015 data->num_synth = SI5340_NUM_SYNTH;
1016 data->reg_output_offset = si5340_reg_output_offset;
1017 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1018 break;
1019 case 0x5341:
1020 data->num_outputs = SI5341_MAX_NUM_OUTPUTS;
1021 data->num_synth = SI5341_NUM_SYNTH;
1022 data->reg_output_offset = si5341_reg_output_offset;
1023 data->reg_rdiv_offset = si5341_reg_rdiv_offset;
1024 break;
1025 case 0x5342:
1026 data->num_outputs = SI5342_MAX_NUM_OUTPUTS;
1027 data->num_synth = SI5342_NUM_SYNTH;
1028 data->reg_output_offset = si5340_reg_output_offset;
1029 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1030 break;
1031 case 0x5344:
1032 data->num_outputs = SI5344_MAX_NUM_OUTPUTS;
1033 data->num_synth = SI5344_NUM_SYNTH;
1034 data->reg_output_offset = si5340_reg_output_offset;
1035 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1036 break;
1037 case 0x5345:
1038 data->num_outputs = SI5345_MAX_NUM_OUTPUTS;
1039 data->num_synth = SI5345_NUM_SYNTH;
1040 data->reg_output_offset = si5341_reg_output_offset;
1041 data->reg_rdiv_offset = si5341_reg_rdiv_offset;
1042 break;
1043 default:
1044 dev_err(&data->i2c_client->dev, "Model '%x' not supported\n",
1045 model);
1046 return -EINVAL;
1047 }
1048
1049 data->chip_id = model;
1050
1051 return 0;
1052 }
1053
1054 /* Read active settings into the regmap cache for later reference */
1055 static int si5341_read_settings(struct clk_si5341 *data)
1056 {
1057 int err;
1058 u8 i;
1059 u8 r[10];
1060
1061 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_NUM, r, 10);
1062 if (err < 0)
1063 return err;
1064
1065 err = regmap_bulk_read(data->regmap,
1066 SI5341_SYNTH_N_CLK_TO_OUTX_EN, r, 3);
1067 if (err < 0)
1068 return err;
1069
1070 err = regmap_bulk_read(data->regmap,
1071 SI5341_SYNTH_N_CLK_DIS, r, 1);
1072 if (err < 0)
1073 return err;
1074
1075 for (i = 0; i < data->num_synth; ++i) {
1076 err = regmap_bulk_read(data->regmap,
1077 SI5341_SYNTH_N_NUM(i), r, 10);
1078 if (err < 0)
1079 return err;
1080 }
1081
1082 for (i = 0; i < data->num_outputs; ++i) {
1083 err = regmap_bulk_read(data->regmap,
1084 data->reg_output_offset[i], r, 4);
1085 if (err < 0)
1086 return err;
1087
1088 err = regmap_bulk_read(data->regmap,
1089 data->reg_rdiv_offset[i], r, 3);
1090 if (err < 0)
1091 return err;
1092 }
1093
1094 return 0;
1095 }
1096
1097 static int si5341_write_multiple(struct clk_si5341 *data,
1098 const struct si5341_reg_default *values, unsigned int num_values)
1099 {
1100 unsigned int i;
1101 int res;
1102
1103 for (i = 0; i < num_values; ++i) {
1104 res = regmap_write(data->regmap,
1105 values[i].address, values[i].value);
1106 if (res < 0) {
1107 dev_err(&data->i2c_client->dev,
1108 "Failed to write %#x:%#x\n",
1109 values[i].address, values[i].value);
1110 return res;
1111 }
1112 }
1113
1114 return 0;
1115 }
1116
1117 static const struct si5341_reg_default si5341_preamble[] = {
1118 { 0x0B25, 0x00 },
1119 { 0x0502, 0x01 },
1120 { 0x0505, 0x03 },
1121 { 0x0957, 0x17 },
1122 { 0x0B4E, 0x1A },
1123 };
1124
1125 static const struct si5341_reg_default si5345_preamble[] = {
1126 { 0x0B25, 0x00 },
1127 { 0x0540, 0x01 },
1128 };
1129
1130 static int si5341_send_preamble(struct clk_si5341 *data)
1131 {
1132 int res;
1133 u32 revision;
1134
1135 /* For revision 2 and up, the values are slightly different */
1136 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
1137 if (res < 0)
1138 return res;
1139
1140 /* Write "preamble" as specified by datasheet */
1141 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xD8 : 0xC0);
1142 if (res < 0)
1143 return res;
1144
1145 /* The si5342..si5345 require a different preamble */
1146 if (data->chip_id > 0x5341)
1147 res = si5341_write_multiple(data,
1148 si5345_preamble, ARRAY_SIZE(si5345_preamble));
1149 else
1150 res = si5341_write_multiple(data,
1151 si5341_preamble, ARRAY_SIZE(si5341_preamble));
1152 if (res < 0)
1153 return res;
1154
1155 /* Datasheet specifies a 300ms wait after sending the preamble */
1156 msleep(300);
1157
1158 return 0;
1159 }
1160
1161 /* Perform a soft reset and write post-amble */
1162 static int si5341_finalize_defaults(struct clk_si5341 *data)
1163 {
1164 int res;
1165 u32 revision;
1166
1167 res = regmap_write(data->regmap, SI5341_IO_VDD_SEL,
1168 data->iovdd_33 ? 1 : 0);
1169 if (res < 0)
1170 return res;
1171
1172 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
1173 if (res < 0)
1174 return res;
1175
1176 dev_dbg(&data->i2c_client->dev, "%s rev=%u\n", __func__, revision);
1177
1178 res = regmap_write(data->regmap, SI5341_SOFT_RST, 0x01);
1179 if (res < 0)
1180 return res;
1181
1182 /* The si5342..si5345 have an additional post-amble */
1183 if (data->chip_id > 0x5341) {
1184 res = regmap_write(data->regmap, 0x540, 0x0);
1185 if (res < 0)
1186 return res;
1187 }
1188
1189 /* Datasheet does not explain these nameless registers */
1190 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xDB : 0xC3);
1191 if (res < 0)
1192 return res;
1193 res = regmap_write(data->regmap, 0x0B25, 0x02);
1194 if (res < 0)
1195 return res;
1196
1197 return 0;
1198 }
1199
1200
1201 static const struct regmap_range si5341_regmap_volatile_range[] = {
1202 regmap_reg_range(0x000C, 0x0012), /* Status */
1203 regmap_reg_range(0x001C, 0x001E), /* reset, finc/fdec */
1204 regmap_reg_range(0x00E2, 0x00FE), /* NVM, interrupts, device ready */
1205 /* Update bits for P divider and synth config */
1206 regmap_reg_range(SI5341_PX_UPD, SI5341_PX_UPD),
1207 regmap_reg_range(SI5341_SYNTH_N_UPD(0), SI5341_SYNTH_N_UPD(0)),
1208 regmap_reg_range(SI5341_SYNTH_N_UPD(1), SI5341_SYNTH_N_UPD(1)),
1209 regmap_reg_range(SI5341_SYNTH_N_UPD(2), SI5341_SYNTH_N_UPD(2)),
1210 regmap_reg_range(SI5341_SYNTH_N_UPD(3), SI5341_SYNTH_N_UPD(3)),
1211 regmap_reg_range(SI5341_SYNTH_N_UPD(4), SI5341_SYNTH_N_UPD(4)),
1212 };
1213
1214 static const struct regmap_access_table si5341_regmap_volatile = {
1215 .yes_ranges = si5341_regmap_volatile_range,
1216 .n_yes_ranges = ARRAY_SIZE(si5341_regmap_volatile_range),
1217 };
1218
1219 /* Pages 0, 1, 2, 3, 9, A, B are valid, so there are 12 pages */
1220 static const struct regmap_range_cfg si5341_regmap_ranges[] = {
1221 {
1222 .range_min = 0,
1223 .range_max = SI5341_REGISTER_MAX,
1224 .selector_reg = SI5341_PAGE,
1225 .selector_mask = 0xff,
1226 .selector_shift = 0,
1227 .window_start = 0,
1228 .window_len = 256,
1229 },
1230 };
1231
1232 static int si5341_wait_device_ready(struct i2c_client *client)
1233 {
1234 int count;
1235
1236 /* Datasheet warns: Any attempt to read or write any register other
1237 * than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt the
1238 * NVM programming and may corrupt the register contents, as they are
1239 * read from NVM. Note that this includes accesses to the PAGE register.
1240 * Also: DEVICE_READY is available on every register page, so no page
1241 * change is needed to read it.
1242 * Do this outside regmap to avoid automatic PAGE register access.
1243 * May take up to 300ms to complete.
1244 */
1245 for (count = 0; count < 15; ++count) {
1246 s32 result = i2c_smbus_read_byte_data(client,
1247 SI5341_DEVICE_READY);
1248 if (result < 0)
1249 return result;
1250 if (result == 0x0F)
1251 return 0;
1252 msleep(20);
1253 }
1254 dev_err(&client->dev, "timeout waiting for DEVICE_READY\n");
1255 return -EIO;
1256 }
1257
1258 static const struct regmap_config si5341_regmap_config = {
1259 .reg_bits = 8,
1260 .val_bits = 8,
1261 .cache_type = REGCACHE_MAPLE,
1262 .ranges = si5341_regmap_ranges,
1263 .num_ranges = ARRAY_SIZE(si5341_regmap_ranges),
1264 .max_register = SI5341_REGISTER_MAX,
1265 .volatile_table = &si5341_regmap_volatile,
1266 };
1267
1268 static int si5341_dt_parse_dt(struct clk_si5341 *data,
1269 struct clk_si5341_output_config *config)
1270 {
1271 struct device_node *child;
1272 struct device_node *np = data->i2c_client->dev.of_node;
1273 u32 num;
1274 u32 val;
1275
1276 memset(config, 0, sizeof(struct clk_si5341_output_config) *
1277 SI5341_MAX_NUM_OUTPUTS);
1278
1279 for_each_child_of_node(np, child) {
1280 if (of_property_read_u32(child, "reg", &num)) {
1281 dev_err(&data->i2c_client->dev, "missing reg property of %s\n",
1282 child->name);
1283 goto put_child;
1284 }
1285
1286 if (num >= SI5341_MAX_NUM_OUTPUTS) {
1287 dev_err(&data->i2c_client->dev, "invalid clkout %d\n", num);
1288 goto put_child;
1289 }
1290
1291 if (!of_property_read_u32(child, "silabs,format", &val)) {
1292 /* Set cm and ampl conservatively to 3v3 settings */
1293 switch (val) {
1294 case 1: /* normal differential */
1295 config[num].out_cm_ampl_bits = 0x33;
1296 break;
1297 case 2: /* low-power differential */
1298 config[num].out_cm_ampl_bits = 0x13;
1299 break;
1300 case 4: /* LVCMOS */
1301 config[num].out_cm_ampl_bits = 0x33;
1302 /* Set SI recommended impedance for LVCMOS */
1303 config[num].out_format_drv_bits |= 0xc0;
1304 break;
1305 default:
1306 dev_err(&data->i2c_client->dev,
1307 "invalid silabs,format %u for %u\n",
1308 val, num);
1309 goto put_child;
1310 }
1311 config[num].out_format_drv_bits &= ~0x07;
1312 config[num].out_format_drv_bits |= val & 0x07;
1313 /* Always enable the SYNC feature */
1314 config[num].out_format_drv_bits |= 0x08;
1315 }
1316
1317 if (!of_property_read_u32(child, "silabs,common-mode", &val)) {
1318 if (val > 0xf) {
1319 dev_err(&data->i2c_client->dev,
1320 "invalid silabs,common-mode %u\n",
1321 val);
1322 goto put_child;
1323 }
1324 config[num].out_cm_ampl_bits &= 0xf0;
1325 config[num].out_cm_ampl_bits |= val & 0x0f;
1326 }
1327
1328 if (!of_property_read_u32(child, "silabs,amplitude", &val)) {
1329 if (val > 0xf) {
1330 dev_err(&data->i2c_client->dev,
1331 "invalid silabs,amplitude %u\n",
1332 val);
1333 goto put_child;
1334 }
1335 config[num].out_cm_ampl_bits &= 0x0f;
1336 config[num].out_cm_ampl_bits |= (val << 4) & 0xf0;
1337 }
1338
1339 if (of_property_read_bool(child, "silabs,disable-high"))
1340 config[num].out_format_drv_bits |= 0x10;
1341
1342 config[num].synth_master =
1343 of_property_read_bool(child, "silabs,synth-master");
1344
1345 config[num].always_on =
1346 of_property_read_bool(child, "always-on");
1347
1348 config[num].vdd_sel_bits = 0x08;
1349 if (data->clk[num].vddo_reg) {
1350 int vdd = regulator_get_voltage(data->clk[num].vddo_reg);
1351
1352 switch (vdd) {
1353 case 3300000:
1354 config[num].vdd_sel_bits |= 0 << 4;
1355 break;
1356 case 1800000:
1357 config[num].vdd_sel_bits |= 1 << 4;
1358 break;
1359 case 2500000:
1360 config[num].vdd_sel_bits |= 2 << 4;
1361 break;
1362 default:
1363 dev_err(&data->i2c_client->dev,
1364 "unsupported vddo voltage %d for %s\n",
1365 vdd, child->name);
1366 goto put_child;
1367 }
1368 } else {
1369 /* chip seems to default to 2.5V when not set */
1370 dev_warn(&data->i2c_client->dev,
1371 "no regulator set, defaulting vdd_sel to 2.5V for %s\n",
1372 child->name);
1373 config[num].vdd_sel_bits |= 2 << 4;
1374 }
1375 }
1376
1377 return 0;
1378
1379 put_child:
1380 of_node_put(child);
1381 return -EINVAL;
1382 }
1383
1384 /*
1385 * If not pre-configured, calculate and set the PLL configuration manually.
1386 * For low-jitter performance, the PLL should be set such that the synthesizers
1387 * only need integer division.
1388 * Without any user guidance, we'll set the PLL to 14GHz, which still allows
1389 * the chip to generate any frequency on its outputs, but jitter performance
1390 * may be sub-optimal.
1391 */
1392 static int si5341_initialize_pll(struct clk_si5341 *data)
1393 {
1394 struct device_node *np = data->i2c_client->dev.of_node;
1395 u32 m_num = 0;
1396 u32 m_den = 0;
1397 int sel;
1398
1399 if (of_property_read_u32(np, "silabs,pll-m-num", &m_num)) {
1400 dev_err(&data->i2c_client->dev,
1401 "PLL configuration requires silabs,pll-m-num\n");
1402 }
1403 if (of_property_read_u32(np, "silabs,pll-m-den", &m_den)) {
1404 dev_err(&data->i2c_client->dev,
1405 "PLL configuration requires silabs,pll-m-den\n");
1406 }
1407
1408 if (!m_num || !m_den) {
1409 dev_err(&data->i2c_client->dev,
1410 "PLL configuration invalid, assume 14GHz\n");
1411 sel = si5341_clk_get_selected_input(data);
1412 if (sel < 0)
1413 return sel;
1414
1415 m_den = clk_get_rate(data->input_clk[sel]) / 10;
1416 m_num = 1400000000;
1417 }
1418
1419 return si5341_encode_44_32(data->regmap,
1420 SI5341_PLL_M_NUM, m_num, m_den);
1421 }
1422
1423 static int si5341_clk_select_active_input(struct clk_si5341 *data)
1424 {
1425 int res;
1426 int err;
1427 int i;
1428
1429 res = si5341_clk_get_selected_input(data);
1430 if (res < 0)
1431 return res;
1432
1433 /* If the current register setting is invalid, pick the first input */
1434 if (!data->input_clk[res]) {
1435 dev_dbg(&data->i2c_client->dev,
1436 "Input %d not connected, rerouting\n", res);
1437 res = -ENODEV;
1438 for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
1439 if (data->input_clk[i]) {
1440 res = i;
1441 break;
1442 }
1443 }
1444 if (res < 0) {
1445 dev_err(&data->i2c_client->dev,
1446 "No clock input available\n");
1447 return res;
1448 }
1449 }
1450
1451 /* Make sure the selected clock is also enabled and routed */
1452 err = si5341_clk_reparent(data, res);
1453 if (err < 0)
1454 return err;
1455
1456 err = clk_prepare_enable(data->input_clk[res]);
1457 if (err < 0)
1458 return err;
1459
1460 return res;
1461 }
1462
1463 static ssize_t input_present_show(struct device *dev,
1464 struct device_attribute *attr,
1465 char *buf)
1466 {
1467 struct clk_si5341 *data = dev_get_drvdata(dev);
1468 u32 status;
1469 int res = regmap_read(data->regmap, SI5341_STATUS, &status);
1470
1471 if (res < 0)
1472 return res;
1473 res = !(status & SI5341_STATUS_LOSREF);
1474 return sysfs_emit(buf, "%d\n", res);
1475 }
1476 static DEVICE_ATTR_RO(input_present);
1477
1478 static ssize_t input_present_sticky_show(struct device *dev,
1479 struct device_attribute *attr,
1480 char *buf)
1481 {
1482 struct clk_si5341 *data = dev_get_drvdata(dev);
1483 u32 status;
1484 int res = regmap_read(data->regmap, SI5341_STATUS_STICKY, &status);
1485
1486 if (res < 0)
1487 return res;
1488 res = !(status & SI5341_STATUS_LOSREF);
1489 return sysfs_emit(buf, "%d\n", res);
1490 }
1491 static DEVICE_ATTR_RO(input_present_sticky);
1492
1493 static ssize_t pll_locked_show(struct device *dev,
1494 struct device_attribute *attr,
1495 char *buf)
1496 {
1497 struct clk_si5341 *data = dev_get_drvdata(dev);
1498 u32 status;
1499 int res = regmap_read(data->regmap, SI5341_STATUS, &status);
1500
1501 if (res < 0)
1502 return res;
1503 res = !(status & SI5341_STATUS_LOL);
1504 return sysfs_emit(buf, "%d\n", res);
1505 }
1506 static DEVICE_ATTR_RO(pll_locked);
1507
1508 static ssize_t pll_locked_sticky_show(struct device *dev,
1509 struct device_attribute *attr,
1510 char *buf)
1511 {
1512 struct clk_si5341 *data = dev_get_drvdata(dev);
1513 u32 status;
1514 int res = regmap_read(data->regmap, SI5341_STATUS_STICKY, &status);
1515
1516 if (res < 0)
1517 return res;
1518 res = !(status & SI5341_STATUS_LOL);
1519 return sysfs_emit(buf, "%d\n", res);
1520 }
1521 static DEVICE_ATTR_RO(pll_locked_sticky);
1522
1523 static ssize_t clear_sticky_store(struct device *dev,
1524 struct device_attribute *attr,
1525 const char *buf, size_t count)
1526 {
1527 struct clk_si5341 *data = dev_get_drvdata(dev);
1528 long val;
1529
1530 if (kstrtol(buf, 10, &val))
1531 return -EINVAL;
1532 if (val) {
1533 int res = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0);
1534
1535 if (res < 0)
1536 return res;
1537 }
1538 return count;
1539 }
1540 static DEVICE_ATTR_WO(clear_sticky);
1541
1542 static const struct attribute *si5341_attributes[] = {
1543 &dev_attr_input_present.attr,
1544 &dev_attr_input_present_sticky.attr,
1545 &dev_attr_pll_locked.attr,
1546 &dev_attr_pll_locked_sticky.attr,
1547 &dev_attr_clear_sticky.attr,
1548 NULL
1549 };
1550
1551 static int si5341_probe(struct i2c_client *client)
1552 {
1553 struct clk_si5341 *data;
1554 struct clk_init_data init;
1555 struct clk *input;
1556 const char *root_clock_name;
1557 const char *synth_clock_names[SI5341_NUM_SYNTH] = { NULL };
1558 int err;
1559 unsigned int i;
1560 struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS];
1561 bool initialization_required;
1562 u32 status;
1563
1564 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
1565 if (!data)
1566 return -ENOMEM;
1567
1568 data->i2c_client = client;
1569
1570 /* Must be done before otherwise touching hardware */
1571 err = si5341_wait_device_ready(client);
1572 if (err)
1573 return err;
1574
1575 for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
1576 input = devm_clk_get(&client->dev, si5341_input_clock_names[i]);
1577 if (IS_ERR(input)) {
1578 if (PTR_ERR(input) == -EPROBE_DEFER)
1579 return -EPROBE_DEFER;
1580 data->input_clk_name[i] = si5341_input_clock_names[i];
1581 } else {
1582 data->input_clk[i] = input;
1583 data->input_clk_name[i] = __clk_get_name(input);
1584 }
1585 }
1586
1587 for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) {
1588 char reg_name[10];
1589
1590 snprintf(reg_name, sizeof(reg_name), "vddo%d", i);
1591 data->clk[i].vddo_reg = devm_regulator_get_optional(
1592 &client->dev, reg_name);
1593 if (IS_ERR(data->clk[i].vddo_reg)) {
1594 err = PTR_ERR(data->clk[i].vddo_reg);
1595 data->clk[i].vddo_reg = NULL;
1596 if (err == -ENODEV)
1597 continue;
1598 goto cleanup;
1599 } else {
1600 err = regulator_enable(data->clk[i].vddo_reg);
1601 if (err) {
1602 dev_err(&client->dev,
1603 "failed to enable %s regulator: %d\n",
1604 reg_name, err);
1605 data->clk[i].vddo_reg = NULL;
1606 goto cleanup;
1607 }
1608 }
1609 }
1610
1611 err = si5341_dt_parse_dt(data, config);
1612 if (err)
1613 goto cleanup;
1614
1615 if (of_property_read_string(client->dev.of_node, "clock-output-names",
1616 &init.name))
1617 init.name = client->dev.of_node->name;
1618 root_clock_name = init.name;
1619
1620 data->regmap = devm_regmap_init_i2c(client, &si5341_regmap_config);
1621 if (IS_ERR(data->regmap)) {
1622 err = PTR_ERR(data->regmap);
1623 goto cleanup;
1624 }
1625
1626 i2c_set_clientdata(client, data);
1627
1628 err = si5341_probe_chip_id(data);
1629 if (err < 0)
1630 goto cleanup;
1631
1632 if (of_property_read_bool(client->dev.of_node, "silabs,reprogram")) {
1633 initialization_required = true;
1634 } else {
1635 err = si5341_is_programmed_already(data);
1636 if (err < 0)
1637 goto cleanup;
1638
1639 initialization_required = !err;
1640 }
1641 data->xaxb_ext_clk = of_property_read_bool(client->dev.of_node,
1642 "silabs,xaxb-ext-clk");
1643 data->iovdd_33 = of_property_read_bool(client->dev.of_node,
1644 "silabs,iovdd-33");
1645
1646 if (initialization_required) {
1647 /* Populate the regmap cache in preparation for "cache only" */
1648 err = si5341_read_settings(data);
1649 if (err < 0)
1650 goto cleanup;
1651
1652 err = si5341_send_preamble(data);
1653 if (err < 0)
1654 goto cleanup;
1655
1656 /*
1657 * We intend to send all 'final' register values in a single
1658 * transaction. So cache all register writes until we're done
1659 * configuring.
1660 */
1661 regcache_cache_only(data->regmap, true);
1662
1663 /* Write the configuration pairs from the firmware blob */
1664 err = si5341_write_multiple(data, si5341_reg_defaults,
1665 ARRAY_SIZE(si5341_reg_defaults));
1666 if (err < 0)
1667 goto cleanup;
1668 }
1669
1670 /* Input must be up and running at this point */
1671 err = si5341_clk_select_active_input(data);
1672 if (err < 0)
1673 goto cleanup;
1674
1675 if (initialization_required) {
1676 /* PLL configuration is required */
1677 err = si5341_initialize_pll(data);
1678 if (err < 0)
1679 goto cleanup;
1680 }
1681
1682 /* Register the PLL */
1683 init.parent_names = data->input_clk_name;
1684 init.num_parents = SI5341_NUM_INPUTS;
1685 init.ops = &si5341_clk_ops;
1686 init.flags = 0;
1687 data->hw.init = &init;
1688
1689 err = devm_clk_hw_register(&client->dev, &data->hw);
1690 if (err) {
1691 dev_err(&client->dev, "clock registration failed\n");
1692 goto cleanup;
1693 }
1694
1695 init.num_parents = 1;
1696 init.parent_names = &root_clock_name;
1697 init.ops = &si5341_synth_clk_ops;
1698 for (i = 0; i < data->num_synth; ++i) {
1699 synth_clock_names[i] = devm_kasprintf(&client->dev, GFP_KERNEL,
1700 "%s.N%u", client->dev.of_node->name, i);
1701 if (!synth_clock_names[i]) {
1702 err = -ENOMEM;
1703 goto free_clk_names;
1704 }
1705 init.name = synth_clock_names[i];
1706 data->synth[i].index = i;
1707 data->synth[i].data = data;
1708 data->synth[i].hw.init = &init;
1709 err = devm_clk_hw_register(&client->dev, &data->synth[i].hw);
1710 if (err) {
1711 dev_err(&client->dev,
1712 "synth N%u registration failed\n", i);
1713 goto free_clk_names;
1714 }
1715 }
1716
1717 init.num_parents = data->num_synth;
1718 init.parent_names = synth_clock_names;
1719 init.ops = &si5341_output_clk_ops;
1720 for (i = 0; i < data->num_outputs; ++i) {
1721 init.name = kasprintf(GFP_KERNEL, "%s.%d",
1722 client->dev.of_node->name, i);
1723 if (!init.name) {
1724 err = -ENOMEM;
1725 goto free_clk_names;
1726 }
1727 init.flags = config[i].synth_master ? CLK_SET_RATE_PARENT : 0;
1728 data->clk[i].index = i;
1729 data->clk[i].data = data;
1730 data->clk[i].hw.init = &init;
1731 if (config[i].out_format_drv_bits & 0x07) {
1732 regmap_write(data->regmap,
1733 SI5341_OUT_FORMAT(&data->clk[i]),
1734 config[i].out_format_drv_bits);
1735 regmap_write(data->regmap,
1736 SI5341_OUT_CM(&data->clk[i]),
1737 config[i].out_cm_ampl_bits);
1738 regmap_update_bits(data->regmap,
1739 SI5341_OUT_MUX_SEL(&data->clk[i]),
1740 SI5341_OUT_MUX_VDD_SEL_MASK,
1741 config[i].vdd_sel_bits);
1742 }
1743 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw);
1744 kfree(init.name); /* clock framework made a copy of the name */
1745 if (err) {
1746 dev_err(&client->dev,
1747 "output %u registration failed\n", i);
1748 goto free_clk_names;
1749 }
1750 if (config[i].always_on)
1751 clk_prepare(data->clk[i].hw.clk);
1752 }
1753
1754 err = devm_of_clk_add_hw_provider(&client->dev, of_clk_si5341_get,
1755 data);
1756 if (err) {
1757 dev_err(&client->dev, "unable to add clk provider\n");
1758 goto free_clk_names;
1759 }
1760
1761 if (initialization_required) {
1762 /* Synchronize */
1763 regcache_cache_only(data->regmap, false);
1764 err = regcache_sync(data->regmap);
1765 if (err < 0)
1766 goto free_clk_names;
1767
1768 err = si5341_finalize_defaults(data);
1769 if (err < 0)
1770 goto free_clk_names;
1771 }
1772
1773 /* wait for device to report input clock present and PLL lock */
1774 err = regmap_read_poll_timeout(data->regmap, SI5341_STATUS, status,
1775 !(status & (SI5341_STATUS_LOSREF | SI5341_STATUS_LOL)),
1776 10000, 250000);
1777 if (err) {
1778 dev_err(&client->dev, "Error waiting for input clock or PLL lock\n");
1779 goto free_clk_names;
1780 }
1781
1782 /* clear sticky alarm bits from initialization */
1783 err = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0);
1784 if (err) {
1785 dev_err(&client->dev, "unable to clear sticky status\n");
1786 goto free_clk_names;
1787 }
1788
1789 err = sysfs_create_files(&client->dev.kobj, si5341_attributes);
1790 if (err)
1791 dev_err(&client->dev, "unable to create sysfs files\n");
1792
1793 free_clk_names:
1794 /* Free the names, clk framework makes copies */
1795 for (i = 0; i < data->num_synth; ++i)
1796 devm_kfree(&client->dev, (void *)synth_clock_names[i]);
1797
1798 cleanup:
1799 if (err) {
1800 for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) {
1801 if (data->clk[i].vddo_reg)
1802 regulator_disable(data->clk[i].vddo_reg);
1803 }
1804 }
1805 return err;
1806 }
1807
1808 static void si5341_remove(struct i2c_client *client)
1809 {
1810 struct clk_si5341 *data = i2c_get_clientdata(client);
1811 int i;
1812
1813 sysfs_remove_files(&client->dev.kobj, si5341_attributes);
1814
1815 for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) {
1816 if (data->clk[i].vddo_reg)
1817 regulator_disable(data->clk[i].vddo_reg);
1818 }
1819 }
1820
1821 static const struct i2c_device_id si5341_id[] = {
1822 { "si5340", 0 },
1823 { "si5341", 1 },
1824 { "si5342", 2 },
1825 { "si5344", 4 },
1826 { "si5345", 5 },
1827 { }
1828 };
1829 MODULE_DEVICE_TABLE(i2c, si5341_id);
1830
1831 static const struct of_device_id clk_si5341_of_match[] = {
1832 { .compatible = "silabs,si5340" },
1833 { .compatible = "silabs,si5341" },
1834 { .compatible = "silabs,si5342" },
1835 { .compatible = "silabs,si5344" },
1836 { .compatible = "silabs,si5345" },
1837 { }
1838 };
1839 MODULE_DEVICE_TABLE(of, clk_si5341_of_match);
1840
1841 static struct i2c_driver si5341_driver = {
1842 .driver = {
1843 .name = "si5341",
1844 .of_match_table = clk_si5341_of_match,
1845 },
1846 .probe = si5341_probe,
1847 .remove = si5341_remove,
1848 .id_table = si5341_id,
1849 };
1850 module_i2c_driver(si5341_driver);
1851
1852 MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
1853 MODULE_DESCRIPTION("Si5341 driver");
1854 MODULE_LICENSE("GPL");
Kernel DRM miscellaneous fixes and cross-tree changes